JPS6367025A - Code converter - Google Patents

Abstract

PURPOSE:To execute the high density recording by using ternary patterns (729 kinds) consisting of six ternary symbols, and making them correspond to 256 kinds of 8-bit patterns. CONSTITUTION:8 bits are held in a holding circuit 1, and converted to six ternary symbols by a code converting circuit 2, a P/S conversion 3, and a binary/ternary converting circuit 11. This symbol pattern consists of 729 kinds, and on the other hand, the 8-bit pattern consists of 256 kinds, therefore, they can be made to correspond to each other. Also, in the code converting circuit 2, a disparity is generated, sent to an adder 10 for executing a cumulative addition, a holding circuit 6 and an inversion control circuit 7, ans when a cumulative addition value and the polarity of the disparity are equal, an inversion control signal is outputted. In this way, a ternary code which contains no DC component is obtained. By six ternary symbols, the high density recording can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to B12 recording of digital signals. The present invention relates to a code conversion device for realizing a ternary code suitable for IJ.

Conventional technology Conventionally, 3B-2 is one of the well-known three-value stroke symbols.
There is a T code. 1.3 bits (B1
．． B2, us) (Bi (i=1-3): binary)
37, -2・ are divided into two symbols (T1゜T2
) can be obtained by converting to

As is clear from the code conversion table for generating the 3B-2T code shown in Table 1, 3 bits (B1.B2
+B3), eight kinds of symbol patterns are selected from nine kinds of symbol patterns made up of 2 symbols (Tj+'r2) and made to correspond one-to-one. By doing so, it is possible to uniquely determine a symbol pattern of two symbols in sequence with a three-bit bit pattern.

(Left below) Table 1 0.1: Binary values M, Z, P: Ternary level x: Unrelated value 1 If the bit length is TI), then 3 B -, 2T
The length of one symbol after conversion Ts is Ts = 1.5 (=-372) Tb 5.

becomes. Therefore, bit frequency fb(-1/Tb)
For symbol frequency fs (-1/TS) = 2/3
fb, and the frequency band of the 3B-2T code is reduced to 2/3 of the bit frequency.

As a result, in the 3B-2T code, the noise power is reduced and the symbol length Ts is also larger than the bit length Tb, which has the advantage over binary coding that it is more resistant to time axis fluctuations such as peak shift and jitter. have.

Problems to be Solved by the Invention As shown above, the 3B-2T code is an excellent code in theory, but it cannot be used for high-density recording due to the following serious problems. .

(1) There is no self-clock function.

(2) There is a DC component.

(3) Error propagation occurs.

The self-clock function is a function that extracts the clock from the level change information of the reproduced signal itself, rather than recording the clock information separately. Therefore, 3B-2T
d: Codes that often do not have a level change for a long period of time, such as codes, do not have a self-clock function.

Since the 3B-2T code includes a DC component, the digital VT
When information is transmitted through a system that has the characteristic of blocking low frequency components, such as the rotary transformer in R, both recording and reproduction waveforms are distorted. As a result, the symbol error rate during reproduction deteriorates significantly.

Digital image data is typically represented in 8 bits.

Therefore, the 3 bits in the 3B-2T code may span two pieces of image data.

In such a case, a symbol error during reproduction becomes a 3-bit error due to 2T-3B conversion, resulting in errors in two image data.

Means for Solving the Problems The present invention has a first holding means for holding an 8-bit data word, and 8 bits of the output of the holding means are input, and each word corresponding to the 8 bits is 7. Conversion means for converting into six ternary symbols, and each of the six symbols output from said conversion means.7. - level inverting means for inverting the first level to a third level and inverting the third level to the first level; and a first level inverting means for switching between the output of the converting means and the output of the level inverting means. switch and -1 to the first level of the ternary symbol
, assign 0 to the second level and +1 to the third level,
disparity generating means for generating a disparity defined by the sum of the level values regarding the six symbols of the output of the converting means; a polarity inverting means for inverting the polarity of the output of the disparity generating means; a second switch for switching between the output of the parity generation means and the output of the polarity inversion means; an adder for cumulatively adding the outputs of the second switch; and a second holding device for holding the output of the adder. the first switch selects the output of the polarity reversing means only when the output of the disparity generating means and the output of the second holding means are both positive or negative; The switch is characterized by comprising switching signal generating means for generating a switching signal for selecting the output of the polarity inverting means, and waveform converting means for converting the output of the first switch into a ternary waveform.

6 ternary symbols (Ti l T21 T31 T4
+T5 +T6) There are 36=729 combinations W of ternary patterns. (~Therefore, six 3
There are 2 = 258 8-bit value symbol patterns.

pattern (J, “2 +B5 +B4 +B5+B
6+B7+Ba) at least one-on-one,
8B-6T conversion is possible. This completely solves the conventional problem where one symbol error spreads to errors in two image data.Furthermore, in the present invention, 729
By combining the same 6-symbol patterns and selecting and using the combined symbol patterns so that the cumulative disparity value never diverges, it is possible to construct a three-value symbol without a DC component, and moreover, it is easier than a binary symbol. You can also lower the maximum frequency.

There are 36 = '729 patterns of 6 symbols in which each embodiment takes 3 positions. here,
When assigning -1 to the first level (9), the second level (ADZ)Ko, and +1 to the third level (P) in a ternary stroke symbol, the sum of the levels for each symbol of a symbol pattern consisting of 6 symbols is , is called the disparity of the symbol pattern. For example, (T1+T2,
T3 + T4 + T5 + T6 ) −(P +
The disparity of the symbol pattern 'r Z+p, p, z) is +1+(-1)+oz+1 〇=2.

In this way, the disparity related to the symbol pattern
When defining , if the accumulated sum of the disk IJ tees of the symbol patterns recorded sequentially does not diverge, the recorded symbol pattern series does not include a DC component. In other words, if it is possible to control the accumulated sum of disparities in the series of recorded symbol patterns so as not to diverge, it is possible to form a three-value symbol that does not contain a DC component.

In the present invention, the symbol 107. with zero disparity.
7. Patterns correspond one-to-one to 8-bit, 1. data, and for symbol patterns with non-zero disparity,
The symbol pattern obtained by inverting the first level (9) to the third level (P) and the third level (P) to the first level (hereinafter referred to as +iL back pattern) and -
They are paired to correspond to an 8-bit data word. for example,
The disparity is -1 (T1+T2tT5+T
4. T5. T6) = (P+P+M, M, Z, M) symbol pattern ir, i, (-) The back pattern discovery is 1-1 (Ti +T2, T3
, T4 +T5 +T6 )= (M + M+ P+
p, z, p).

As a result, if a symbol pattern sequence having a disparity of opposite polarity to the polarity of the cumulative sum of disparities of the already recorded symbol patterns is selected and recorded, the cumulative sum of disparities will not diverge. , Therefore, the recorded symbol sequence does not include a DC component.

Regarding the symbol pattern of disparity-0,
Disparity 11A without any control.

Since the cumulative addition value of - does not diverge, it is possible to have a one-to-one correspondence with 8-bit data.

Table 2 shows the number of combinations of symbol patterns combined based on such criteria for each disparity. Second
As seen in the table, the total number of combinations is 434, 8
It can handle all bit data. Table 2 shows 6 of the symbol patterns with disparity -=0.
A symbol pattern in which all symbols are at the second level (Z) is not included. If such a symbol pattern continues, the self-clock function cannot be obtained. All 6 symbols are at the 1st level. Ifc is at the 3rd level? ), there is no need to specifically exclude symbol patterns because, for example, symbol patterns that are all at the third level will not continue by controlling the cumulative addition value of disparity.

(Left below) Table 2 rJP: Disparity DP: Disparity - 13/,,--n Table 3 shows the symbol patterns when a restriction is added to prevent three or more of the same symbol from consecutively. The number of combinations of is shown for each disparity.

Even with such restrictions, the number of combinations of symbol patterns is 304, which can accommodate all 8-bit data. Furthermore, even if the symbol patterns in Table 3 are limited to use only those symbol patterns in which the absolute value of the disk IJ tee is 2 or less, it is possible to correspond to all 8-bit data.

In either case, there are more than 256 (=2) symbol pattern sets, from which 266 appropriate symbol pattern sets necessary to correspond to 8-bit data can be selected. Next, a circuit configuration for performing 8B-6T conversion while removing DC components for the selected 256 symbol patterns will be described with reference to the drawings.

The figure shows a block diagram of an 8B-6T transform encoding circuit. In the figure, a holding circuit 1 holds 8 bits of input, and its output is sent to a code conversion circuit 2.

In code conversion circuit 2, 614 corresponding to 8 bits of input,
− Generate symbols.

It is assumed that each symbol generated by the code conversion circuit 2 is represented by two bits that can distinguish three levels from each other. For example, the first level (M) is set to 01, the second level (Z) to 11, and the third level (P) to 'c10. In this way, each symbol pattern of 6 symbols is represented by 2 bits, so the code conversion circuit 2
Outputs 2 bits.

The six parallel symbols output from the code conversion circuit 2 are converted into six serial symbols by a parallel-to-serial conversion (P/S) circuit 3. As a result, the two bits representing the level of each symbol appear sequentially at the output of the parallel-serial conversion circuit 3.

The signal is sent to the output 1- of the parallel-to-serial conversion circuit 3, the switch 4, and the inverting circuit 6, respectively. The inverting circuit 5 is a circuit for negating each of the two bits output from the parallel-serial conversion circuit 3, and the two bits output from the inverting circuit 6 are sent to the switch 4.

On the other hand, the code conversion circuit 2 generates a 16-page symbol pattern consisting of 6 symbols and also generates a disparity regarding this symbol pattern. This value of disharity is sent to the inversion control circuit 7 together with the output of the holding circuit 6 that holds the cumulative addition value of the disharity. The inversion control circuit 7 outputs an inversion control signal Y which becomes 0 when the polarity of the accumulated value of disparity and the polarity of disparity is equal, and becomes 1 when they are different.

The switch 4 selects the output of the parallel-serial conversion circuit 3 when the value of the inversion control signal Y is 00, and selects the output of the inversion circuit 5 when the value of the inversion control signal Y is 1. Similarly, the switch 8 selects the disparity value from the code conversion circuit 2 when the value of the inversion control signal Y is O, and selects the disparity value from the code conversion circuit 2 when the value of the inversion control signal Y is 1. The output of the polarity inversion circuit 9 that inverts the polarity of the - value is selected. The output of the switch 8 is added to the output of the holding circuit 6 by an adder 10, and is held in the holding circuit 6 after sending out the symbol pattern of 6 symbols.

That is, when the inversion control signal Y is ○, the symbol pattern appearing in the output of the sign S3 conversion circuit 2 is sent out as is, and the disparity of this symbol pattern is
Mosono! r, 1 Add to the cumulative addition value of disparity. Conversely, when the inversion control signal Y is 1, the code conversion circuit 2
Since the reverse pattern of the symbol pattern appearing in the output of is transmitted, the value of disparity added to the cumulative addition value of disparity is also inverted.

The ternary symbols, each represented by 2 bits, appearing at the output of the switch 4 are converted by the binary/ternary conversion circuit 11 into a ternary level corresponding to the 2 bits of the input, and are recorded. As shown above, the present invention is a very simple circuit with 0
'8B-6T can be realized without combining the 1-wave component.

Effects of the Invention The present invention eliminates the drawbacks of the conventional ternary code 51 that made it difficult to apply to high-density recording, and
New model 3 with performance suitable for high-density recording than value recording.
This makes it possible to realize value-adding with an extremely small circuit of 17 circuits. The present invention is effective not only for digital VTRs, but also for optical discs, digital audio, and other recording media and signals to be recorded, and has very great practical effects.

In this specification, 8B-6T has been described as an example, but it is needless to say that the present invention can also be applied to a general three-value design that does not include a direct current component. Furthermore, although the circuit configuration of the embodiment is based on the premise of using a general-purpose logic circuit, it can be implemented in almost the same way with a ternary logic circuit.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of a circuit configuration for realizing the present invention. DESCRIPTION OF SYMBOLS 1... (first) holding means, 2... code conversion circuit, 4... (first) switch, 6...
... (level) inversion circuit, 6 ... linear chain 2) holding circuit, 7 ... inversion control circuit (switching signal generation means), 8 ... river... (second) switch,
9... Polarity inversion circuit, 1°... Adder, 11... Binary/ternary value conversion circuit (waveform conversion means).

Claims (1)

[Claims] a first holding means for holding an 8-bit data word; a converting means for inputting the 8 bits of the output of the holding means and converting the 8 bits into six symbols each having a ternary value; Level inverting means for inverting a first level to a third level and inverting the third level to the first level for each of the six symbols output from the converting means; and the output of the converting means and the level inverting means. a first switch for switching the output of the ternary symbol, -1 is assigned to the first level of the ternary symbol, 0 is assigned to the second level, and +1 is assigned to the third level, and this level value for the six symbols output from the conversion means is assigned; a disparity generating means for generating disparity defined by the sum of the disparity generating means; a polarity reversing means for reversing the polarity of the output of the disparity generating means; and a polarity reversing means for switching the output of the disparity generating means and the output of the polarity reversing means. a second switch, an adder for cumulatively adding the output of the second switch, a second holding means for holding the output of the adder, and an output of the disparity generating means and the second holding means; The first switch selects the output of the polarity reversing means only when the outputs of the means are both positive or both negative, and the second switch generates a switching signal that selects the output of the polarity reversing means. A code conversion device comprising a switching signal generation means and a waveform conversion means for converting the output of the first switch into a ternary waveform.