JPS6366953A - Polymer planar-metallization type semiconductor device and manufacture threrof - Google Patents

Polymer planar-metallization type semiconductor device and manufacture threrof

Info

Publication number
JPS6366953A
JPS6366953A JP61210995A JP21099586A JPS6366953A JP S6366953 A JPS6366953 A JP S6366953A JP 61210995 A JP61210995 A JP 61210995A JP 21099586 A JP21099586 A JP 21099586A JP S6366953 A JPS6366953 A JP S6366953A
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
shape
metallic frame
heat dissipation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61210995A
Other languages
Japanese (ja)
Other versions
JP2507343B2 (en
Inventor
Takao Emoto
江本 孝朗
Toshihiro Kato
加藤 俊博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61210995A priority Critical patent/JP2507343B2/en
Publication of JPS6366953A publication Critical patent/JPS6366953A/en
Application granted granted Critical
Publication of JP2507343B2 publication Critical patent/JP2507343B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve the adhesive strength of a metallic frame and a molding resin, and to enhance heat-dissipating characteristics by forming irregularities on the radiating surface of the metallic frame while executing blast treatment. CONSTITUTION:In a semiconductor device having a shape that the radiating surface (the rear) of a metallic frame 1 on which a semiconductor chip 2 is mounted is electrically insulated by a resin 3, irregularities are formed to the radiating surface M of the metallic frame 1 while blast treatment is executed. The radiating surface M of the metallic frame 1 for a discrete power element is stamping-worked (irregularly-worked) on one surface in size of the square of 0.1mm depth and 0.5mm width, and roughened-surface working is executed to the surface of the radiating surface M through blast treatment. In this case, the working shape of irregularities may take a V shape, or a plane shape may take a striped, polygonal, circular or rectangular shape, etc.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は樹脂絶縁型半導体装置及びその製造方法に関す
るもので、特に大形装置の絶縁特性及び放熱特性の改善
時に使用されるものである。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a resin-insulated semiconductor device and a method for manufacturing the same, and is particularly used for improving the insulation characteristics and heat dissipation characteristics of large-sized devices. It is something that

(従来の技術) 絶縁型パワートランジスタの略図は例えば第4図の如く
である。同図(a)は平面的構成図、同図(b)は同構
成の断面図で1は金属フレーム、2はチップ、3は樹脂
、4はポンディングワイヤである。
(Prior Art) A schematic diagram of an insulated power transistor is shown in FIG. 4, for example. 1A is a plan view of the configuration, and FIG. 1B is a cross-sectional view of the same configuration, in which 1 is a metal frame, 2 is a chip, 3 is a resin, and 4 is a bonding wire.

ここで図示されていないが、普通フレーム1は横に複数
個並んだ形で連なっており、樹脂封止の後、接続個所を
切断して第4図のような形とする。
Although not shown here, a plurality of frames 1 are normally arranged in a row in a row, and after being sealed with resin, the connecting portions are cut to form the shape as shown in FIG.

上記のものはトランジスタチップを固着し、Auまたは
At等の細線によシ配線されたフレーム部品をトランス
ファ成形により樹脂封止されるのが普通である。本方法
はフレーム1の裏面(放熱面)も同時に包み込む形で成
形されることを特徴とする。
In the above-mentioned device, the transistor chip is usually fixed and the frame component, which is wired with thin wires such as Au or At, is sealed with a resin by transfer molding. This method is characterized in that the back surface (heat dissipation surface) of the frame 1 is also molded to be wrapped at the same time.

即ちこの方法は樹脂厚とその熱伝導率により決まり、樹
脂材料は高熱伝導樹脂と呼ばれるλ=40−60X10
−’cal/crn−s・’cの樹脂例えば東芝ケミカ
ル社製KE550Tが樹脂厚t=0.5〜0.6籠程度
で使われる。この様な方法は非常に量産性に富み熱特性
や絶縁耐圧特性等がほぼ外付けの絶縁シート(例えばマ
イカ、マイラ等)に劣らず実用レベルに達してお夛、主
にデスクリートパワー素子に使用されている。また、フ
レームが分離した形の例えば第6図の様な複合素子フレ
ームでの製造では、特に構造的強度の面から第5図に示
す様な放熱フィン5を追加した形が採用されている。
That is, this method is determined by the resin thickness and its thermal conductivity, and the resin material is λ = 40-60X10, which is called a high thermal conductive resin.
-'cal/crn-s/'c resin, for example, KE550T manufactured by Toshiba Chemical Co., Ltd., is used with a resin thickness t of about 0.5 to 0.6 cm. This method is highly suitable for mass production, and its thermal characteristics and dielectric strength characteristics have reached a practical level comparable to that of external insulation sheets (e.g., mica, mylar, etc.), and are mainly used in discrete power devices. It is used. In addition, in the manufacture of a composite element frame with separate frames, for example, as shown in FIG. 6, a structure in which heat dissipation fins 5 are added as shown in FIG. 5 is adopted especially from the viewpoint of structural strength.

(発明が解決しようとする問題点) これらの構造においては金属フレームと成形樹脂又は金
属板との熱膨張係数(α)の相違や樹脂の成形収縮率等
によシ製品に反シが発生するが、金属フレームや金属板
を予めその反シ方向と反対方向に湾曲させておく方法等
で外形寸法は実用上充分な補正が出来る。しかし乍ら、
金属−樹脂間には歪が残存し、今まで以上に放熱特性を
向上させたシ、大型の装置を開発しようとすると、フレ
ーム放熱面(裏面)樹脂層を更に薄く設定しなければな
らないので増々歪は増大し、樹脂層が割れたり、剥がれ
たりする不都合が生じる。
(Problems to be solved by the invention) In these structures, cracks occur in the product due to the difference in thermal expansion coefficient (α) between the metal frame and the molded resin or metal plate, the molding shrinkage rate of the resin, etc. However, the external dimensions can be corrected sufficiently for practical purposes by bending the metal frame or metal plate in the opposite direction in advance. However,
Strain still remains between the metal and the resin, and if we try to develop a large-scale device with improved heat dissipation characteristics than ever before, the resin layer on the heat dissipation surface (back side) of the frame must be made even thinner, so this will increase. The strain increases, causing problems such as cracking or peeling of the resin layer.

本発明は上記実情に鑑みてなされたもので、絶縁型半導
体装置の絶縁樹脂層の接着強度を上げ、放熱特性を向上
させようとするものである。
The present invention has been made in view of the above circumstances, and is intended to increase the adhesive strength of the insulating resin layer of an insulated semiconductor device and improve the heat dissipation characteristics.

[発明の構成] (問題点を解決するための手段と作用)本発明は、金属
フレームの放熱面(裏面)を樹脂により電気的に絶縁し
た形の半導体装置において、金属フレームの放熱面に凹
凸を付けると共にブラスト処理を施こして粗面にするこ
とによシ、金属フレームと成形樹脂の接着強度を向上さ
せ、結果として放熱特性の向上を図るものである。
[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a semiconductor device in which the heat dissipation surface (back surface) of a metal frame is electrically insulated with a resin, in which unevenness is formed on the heat dissipation surface of the metal frame. By adding a rough surface to the metal frame and roughening it by blasting, the adhesive strength between the metal frame and the molded resin is improved, and as a result, the heat dissipation characteristics are improved.

(実施例) 以下図面を参照して本発明の一実施例を説明する。第1
図は同実施例の断面図である。複合素子等の要素子分離
形装置についても考え方は同じなので、説明を判シ易く
するためデスクリート素子を例にあげる。また従来のも
のと対応する個所には同一符号を付して説明を省略し、
特徴とする個所の説明を行なう。ここでは金属フレーム
1の放熱面Mは、例えば深さ0.1■1幅0.5 m口
の寸法で一面に刻印加工(凹凸加工)され、更に図では
明らかではないがその表面はブラスト処理により粗面加
工が施される所が特徴である。ここで凹凸の加工形状は
V字形でも良いし、平面形状はストライプや多角形、円
形又は短冊形等でも良く、表面積を増やすのが目的であ
る。
(Example) An example of the present invention will be described below with reference to the drawings. 1st
The figure is a sectional view of the same embodiment. The concept is the same for element-separated devices such as composite devices, so to make the explanation easier to understand, we will use discrete devices as an example. In addition, parts corresponding to the conventional ones are given the same symbols and explanations are omitted.
I will explain the features. Here, the heat dissipation surface M of the metal frame 1 has dimensions of, for example, 0.1 m in depth and 0.5 m in width, and is engraved (irregularly processed) on one side, and furthermore, although it is not clear in the figure, the surface is blasted. It is characterized by a rough surface finish. Here, the processed shape of the unevenness may be V-shaped, and the planar shape may be striped, polygonal, circular, or rectangular, and the purpose is to increase the surface area.

製造方法に於いて、樹脂封止を2回に分けて行う謂る二
重モールド形式を採ることも可能で、製造加工工数は増
えるが、放熱面M側絶縁樹脂層厚さのコントロールが容
易で、よシ樹脂層の薄い製品の製造が可能である。この
様な製造方法を採る場合は、第1樹脂封止(フレーム上
側の成形)が終了し、第2樹脂封止前にブラスト処理を
行うのが、第1樹脂封止での薄パリ、離型油の除去が同
時に行え効果的である。
Regarding the manufacturing method, it is also possible to adopt a so-called double molding method in which resin sealing is performed in two steps, which increases the number of manufacturing steps, but makes it easier to control the thickness of the insulating resin layer on the heat dissipation surface M side. , it is possible to manufacture products with a thin resin layer. When using such a manufacturing method, blasting is performed after the first resin sealing (molding of the upper side of the frame) and before the second resin sealing to prevent thin flakes and separation in the first resin seal. It is effective because mold oil can be removed at the same time.

第2図は本発明の変形例で、金属放熱フィン5が付加さ
れたタイプであシ、金属放熱フィンも、同様な思想で加
工が施されても良い。
FIG. 2 shows a modification of the present invention, in which metal radiation fins 5 are added, and the metal radiation fins may also be processed based on the same idea.

放熱面積的100s112のフレームでの試作結果を第
3図に示す。ここで刻印形状は深さ0.1■、幅0.3
0−モザイク状、ブラストはメディアががラスビーズ(
粒径約80μm、圧力5 kg7cm2の加工条件であ
る。第3図では、A;加工なし、B;ブラスト処理のみ
、C;刻印加工のみ、D;刻印、ブラスト処理(本発明
)で、Aを「1」とした場合の樹脂剥し強度(イ)と、
熱抵抗Rth (ロ)の比較データである。樹脂剥し強
度では、A′)まり加工なしに比べ、Dつまり、本発明
では5〜8倍の強度を有し、熱抵抗Rthの比較では、
約半分の値が観測された。
Figure 3 shows the results of a trial production using a frame with a heat dissipation area of 100s112. Here, the engraving shape is 0.1cm deep and 0.3cm wide.
0 - Mosaic, blasting media is made of rasp beads (
The processing conditions were a particle size of approximately 80 μm and a pressure of 5 kg 7 cm2. In Figure 3, A: no processing, B: blasting only, C: stamping only, D: stamping and blasting (invention), and the resin peeling strength (A) when A is set to "1". ,
This is comparative data of thermal resistance Rth (b). In terms of resin peel strength, A') compared to the non-marinated one, D, that is, the strength of the present invention is 5 to 8 times higher, and in comparison of thermal resistance Rth,
Approximately half the value was observed.

尚A、Bでは完全に樹脂剥離現象が見られ、Cでは一部
完全なものもありたが、A、Hの半分程(ギャップ〜1
0μm)の剥離があった。
In addition, complete resin peeling phenomenon was observed in A and B, and there was some complete resin peeling in C, but about half of A and H (gap ~ 1
There was peeling of 0 μm).

この様な半導体装置の放熱特性の向上は、凹凸加工によ
る放熱面樹脂層厚の増大を負特性を保持したまま最少に
留め、金属フレーム−樹脂間の接着強度を上げることが
出来たためと考えられる。
This improvement in the heat dissipation characteristics of semiconductor devices is thought to be due to the fact that the increase in the thickness of the resin layer on the heat dissipation surface due to the uneven processing was kept to a minimum while maintaining negative characteristics, and the adhesive strength between the metal frame and the resin was increased. .

[発明の効果コ 以上説明した如く本発明によれば、絶縁型半導体装置の
?!、縁樹脂層の接着強度を上げ、放熱特性を向上させ
ることができるものである。
[Effects of the Invention] As explained above, according to the present invention, an insulated semiconductor device can be produced. ! , the adhesive strength of the edge resin layer can be increased and the heat dissipation properties can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の断面図、第2図は本発明の
他の実施例の断面図、第3図は本発明の実施例の効果を
示す特性図、第4図、第5図は従来の樹脂絶縁型半導体
装置の構成図、第6図は複合素子フレームの構成図であ
る。 l・・・金属フレーム、2・・・チップ、3・・・樹脂
、4・・・?ンディングワイヤ、5・・・金属放熱フィ
ン。 出願人代理人 弁理士 鈴 江 武 彦第1図 第2図 BCO 第3図 (a)         (b) 第4区 第5区 o     OO 第 6 因
FIG. 1 is a cross-sectional view of one embodiment of the present invention, FIG. 2 is a cross-sectional view of another embodiment of the present invention, FIG. 3 is a characteristic diagram showing the effects of the embodiment of the present invention, and FIGS. FIG. 5 is a block diagram of a conventional resin-insulated semiconductor device, and FIG. 6 is a block diagram of a composite element frame. l...metal frame, 2...chip, 3...resin, 4...? 5...metal heat dissipation fin. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 BCO Figure 3 (a) (b) 4th Ward 5th Ward o OO 6th cause

Claims (2)

【特許請求の範囲】[Claims] (1)半導体チップをマウントする金属フレームの放熱
面(裏面)を樹脂により電気的に絶縁した形の半導体装
置において、前記金属フレームの放熱面に凹凸を設ける
と共にブラスト処理を施こしたものであることを特徴と
する樹脂絶縁型半導体装置。
(1) A semiconductor device in which the heat dissipation surface (back surface) of a metal frame on which a semiconductor chip is mounted is electrically insulated with resin, in which unevenness is provided on the heat dissipation surface of the metal frame and a blasting process is performed. A resin insulated semiconductor device characterized by:
(2)半導体チップをマウントする金属フレームの放熱
面(裏面)を樹脂により電気的に絶縁した形の半導体装
置の製造方法において、樹脂成形をフレーム上側の第1
樹脂成形と金属フレーム放熱面(裏面)への第2樹脂成
形とを別々に行なう場合、前記放熱面への凹凸形成及び
第1樹脂成形終了後にブラスト処理を行なうことを特徴
とする樹脂絶縁型半導体装置の製造方法。
(2) In a method for manufacturing a semiconductor device in which the heat dissipation surface (back surface) of a metal frame on which a semiconductor chip is mounted is electrically insulated with resin, the resin molding is performed on the first
A resin-insulated semiconductor characterized in that, when resin molding and second resin molding on the heat radiating surface (back surface) of the metal frame are performed separately, a blasting process is performed after forming irregularities on the heat radiating surface and completing the first resin molding. Method of manufacturing the device.
JP61210995A 1986-09-08 1986-09-08 Resin-sealed semiconductor device Expired - Fee Related JP2507343B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61210995A JP2507343B2 (en) 1986-09-08 1986-09-08 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61210995A JP2507343B2 (en) 1986-09-08 1986-09-08 Resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPS6366953A true JPS6366953A (en) 1988-03-25
JP2507343B2 JP2507343B2 (en) 1996-06-12

Family

ID=16598582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61210995A Expired - Fee Related JP2507343B2 (en) 1986-09-08 1986-09-08 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JP2507343B2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0350342U (en) * 1989-09-25 1991-05-16
JPH0477261U (en) * 1990-11-19 1992-07-06
US5514913A (en) * 1991-12-05 1996-05-07 Consorzio Per La Ricerca Sulla Microelettronica Net Mezzogiorno Resin-encapsulated semiconductor device having improved adhesion
JP2000269415A (en) * 1999-03-18 2000-09-29 Hitachi Ltd Resin-sealed type electronic device for internal combustion engine
JP2001015682A (en) * 1999-06-28 2001-01-19 Hitachi Ltd Resin sealed electronic device
US7294912B2 (en) 2004-08-06 2007-11-13 Denso Corporation Semiconductor device
JP2009302526A (en) * 2008-05-16 2009-12-24 Denso Corp Electronic circuit device and manufacturing method thereof
JP2011097060A (en) * 2009-10-28 2011-05-12 Samsung Electro-Mechanics Co Ltd Flip-chip package and method of manufacturing the same
JP2014107519A (en) * 2012-11-30 2014-06-09 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60118252U (en) * 1984-01-18 1985-08-09 沖電気工業株式会社 Lead frame for resin-sealed semiconductor devices
JPS60186044A (en) * 1983-12-12 1985-09-21 テキサス インスツルメンツ インコ−ポレイテツド Integrated circuit device
JPS60244052A (en) * 1984-05-17 1985-12-03 Toshiba Corp Lead frame for semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60186044A (en) * 1983-12-12 1985-09-21 テキサス インスツルメンツ インコ−ポレイテツド Integrated circuit device
JPS60118252U (en) * 1984-01-18 1985-08-09 沖電気工業株式会社 Lead frame for resin-sealed semiconductor devices
JPS60244052A (en) * 1984-05-17 1985-12-03 Toshiba Corp Lead frame for semiconductor device

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0350342U (en) * 1989-09-25 1991-05-16
JPH0477261U (en) * 1990-11-19 1992-07-06
US5514913A (en) * 1991-12-05 1996-05-07 Consorzio Per La Ricerca Sulla Microelettronica Net Mezzogiorno Resin-encapsulated semiconductor device having improved adhesion
US5766985A (en) * 1991-12-05 1998-06-16 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Process for encapsulating a semiconductor device having a heat sink
JP2000269415A (en) * 1999-03-18 2000-09-29 Hitachi Ltd Resin-sealed type electronic device for internal combustion engine
JP2001015682A (en) * 1999-06-28 2001-01-19 Hitachi Ltd Resin sealed electronic device
US7294912B2 (en) 2004-08-06 2007-11-13 Denso Corporation Semiconductor device
JP2009302526A (en) * 2008-05-16 2009-12-24 Denso Corp Electronic circuit device and manufacturing method thereof
JP2011097060A (en) * 2009-10-28 2011-05-12 Samsung Electro-Mechanics Co Ltd Flip-chip package and method of manufacturing the same
US8558360B2 (en) 2009-10-28 2013-10-15 Samsung Electro-Mechanics Co., Ltd. Flip chip package and method of manufacturing the same
US8809122B2 (en) 2009-10-28 2014-08-19 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing flip chip package
JP2014107519A (en) * 2012-11-30 2014-06-09 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same

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Publication number Publication date
JP2507343B2 (en) 1996-06-12

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