JPS6365794A - Video digital multiple demultiplexer - Google Patents

Abstract

PURPOSE:To decrease the transmission speed by a small sized circuit with less picture quality deterioration by applying multiplex alternately in signal multiplex so that the brightness of the adjacent sampling points and the line and a chrominance signal are not of the same kind. CONSTITUTION:A luminance signal Y and chrominance signals I, Q in a video signal are inputted to sample-and-hold circuits 6-8. A horizontal synchronizing signal separated from a composite synchronizing signal is multipled by a clock period and inputted to a 4-adic counter 12 and an A/D converter 14. A counter 12 holds the signal Y at the circuit 6 by clock periods 0, 2. The signal I is held by the circuit 7 at period 1 and the signal Q is held by the circuit 8 at a period 3. Outputs of the circuits 6-8 are converted by the converter 14 at the clock period and multiplexed. Component signals Y, I, Q at the sampling point use a field offset sampling so as to make the kind with the component signal at the same horizontal location as adjacent scanning lines in other video field different.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an apparatus that can digitally multiplex and separate analog component color video signals with little deterioration in image quality.

(Prior Art) Conventionally, a method for digitally multiplexing analog component color images involves digitizing each component at the time of sampling and time-division multiplexing. For example, CCI
Recommendation for studio digital television in R (“Enko
ding Parameters of Digital
Te1evision for 5tudios”
CCIRItecommendation, 601
), the multiplexing ratio of each component is Y: (R-
Y): (B-Y)=4:2:2, the sampling frequency is 13.5 KHz, and the number of ht child conversion bits is 8 bits, which is linear ω child conversion. Furthermore, the sampling frequency of the luminance signal [Y] is a grid-like point as shown in FIG.

(B-Y)] is one sampling point, and the points are arranged in a grid pattern.

(Problem to be solved by the invention) To digitally multiplex and transmit signals of this standard, 2
A 16 Mb/s transmission line is required, and although the video quality is very good, the amount of information to be transmitted is large, so a high-speed transmission line is required.

(Object of the Invention) An object of the present invention is to provide a device that can transmit digitized component color video signals, which conventionally required a high-speed transmission line, at less than half the speed of the conventional method.

(Means for Solving the Problems) The present invention provides a method in which luminance signals and color signals of adjacent sampling points and adjacent lines (scanning lines) are of the same type (Y, I) in signal multiplexing.
. This allows the transmission speed of digitized component color video signals to be reduced with a small-scale circuit and minimal deterioration in image quality, and the multiplexed luminance and chrominance signals are converted using a single pipeline predictive encoder. By doing so, the transmission speed can be further reduced.

Conventional multiplexing of component color video signals after digitization results in the speed of the sum of each signal, and to achieve this with -2 A/D converters, a sampling frequency twice that of the luminance signal is required; A high-speed A/D converter with a sampling frequency and a changeover switch for each signal are required. Furthermore, when A/D converters for luminance signals and color signals are used, two A/D converters for sampling frequencies and a changeover switch for each signal are required. To reduce the transmission speed of this signal, a total of three predictive encoders are required: one for the luminance signal (Y) and one for the color signal (1, Q or R-Y, B-Y). The difference between conventional techniques is that they require a high-speed A/D converter and multiple converters/predictive encoders.

(Actual 7II! iP/4> Figure 1 shows the NTS as the horizontal synchronization frequency and vertical synchronization frequency.
Using the C system value, set the sampling frequency to 13.5MH2
This is an embodiment of the multiplexing section and demultiplexing section used in the present invention, and FIG. 1 is a multiplexing unit, 2 is a luminance signal (Y) input terminal, 3 is a chrominance signal (1) input terminal, 4 is a chrominance signal (Q) input terminal, 5 is a composite synchronization signal input terminal, 6, 7.8 are samples Hold circuit (S&H), 9 is even number, odd number field detection circuit, 1
0 is horizontal synchronization signal separation circuit, 11 is multiplication (858 times)
12 is a quaternary counter, 13 is an OR circuit, 14 is an analog-to-digital converter (A10), 15 is a data output, 16 is a clock output, and 17 is a composite synchronization signal output terminal.

FIG. 2B shows a demultiplexing section of a video digital multiplexing and demultiplexing apparatus. 21 is a separation unit, 22 is a data input terminal, 23 is a clock input terminal, 24 is a composite synchronization signal input terminal, 25 is a digital/analog converter (D/A), 26 is an even/odd field detection circuit, 27, 28 , 29 is a sample and hold (S&H) circuit, 30 is a quaternary counter, and 31 is an O
In the R circuit, 32 is a luminance signal (Y) output terminal, 33 is a chrominance signal (1) output terminal, 34 is a chrominance signal (Q) output terminal, and 35 is a composite synchronization signal output terminal.

The operation of this multiplexing section (A) will be described below.

The luminance signal (Y) and color signal @ (1, Q) of the video signal are input from the respective input terminals 2 and 3.4 to each sample hold (S
&)() is input to circuit 6.7.8.

A composite synchronization signal obtained by combining the horizontal synchronization signal and the vertical synchronization signal is input to the input terminal 5. This composite synchronization signal is input to an even/odd field detection circuit 9 and a horizontal synchronization signal separation circuit 10. Furthermore, it is output as is to the output terminal 17 as a composite synchronization signal.

The horizontal synchronization signal @ (frequency: fl) separated from the composite synchronization signal by the horizontal synchronization signal separation circuit 10 is converted to 85 by the multiplier circuit 11.
It is multiplied by 8 and becomes the clock period (fS), which is divided into a quaternary counter 12 and an analog-to-digital converter (A/D'') 14.
is input. Furthermore, it is outputted to the output terminal 16 as a clock. The quaternary counter 12 has a clock period (fs
) is divided by 4.

The OR circuit 13 performs the logical sum of the outputs of O++ and 2'', and at that timing, the luminance signal (Y) of the input video signal is held in the sample and hold (S&H) circuit 6.11''
At the output, sample and hold the color signal (1) (S &) I)
It is held in circuit 7, and the 113 II ratio output is the color signal (Q
) is held in sample and hold (S&H>circuit 8.These sample and hold (S&H) circuits 6.7.8
The output of
It is output from the data output terminal 15 as a multiplexed video digital signal. When transmitting these output signals (digital signals, clock signals, composite synchronization signals), they can be digitally time-division multiplexed and sent.

Component signals (Y, I.

Q) uses field offset sampling in which the order is shifted for each scanning line so that the type of component signal at the same horizontal position is different from that of an adjacent scanning line in another video field. Therefore, the output of the even/odd field detection circuit 9 resets the quaternary counter 12 at the beginning of the odd field, and sets it to "1'° at the beginning of the even field. The relationship between these input signals and the output (sampling output) of the data output terminal shown in FIG. 15 is shown in the third diagram, and the sampling arrangement of each component on both sides is shown in FIG. It has been reported that this kind of video signal sampling arrangement (field offset sub-sampling format) causes little deterioration in image quality evaluation experiments (Kuyama, Yano:
“Schemes and Image Quality of Component Coding Low-Level Family”, Journal of the Society of Television Engineers, Vol. 1.39. no, 10.
pp941-948.1985). However, if a small amount of deterioration is allowed, the luminance signal and the chrominance signal may be arranged in consecutive sampling positions. In this case, the outputs "1" and "2" of the quaternary counter 12 may be interchanged.

Additionally, many consecutive sampling arrangements and 16
The period of the quaternary counter 12 may be increased.

Next, the operation of the separating section (B) will be described below.

The multiplexed video digital signal is sent to the arter input terminal 22.
The signal is input to the digital-to-analog converter 25. The output of the digital to analog converter 25 is input to each sample and hold (S&H) circuit 27°28.29. The clock (fS) signal is input from the clock input terminal 23 to the digital-to-analog converter 25 and the quaternary counter 3o.

The composite synchronization signal is input to the even/odd field detection circuit 26 and also output to the composite signal output terminal 35. Protection against input errors in the even/odd field detection circuit 26 can be achieved by adding a synchronization protection circuit.

Divide the frequency of the quaternary counter 3o beams Otsu') (fs) by 4,
The OR circuit 31 performs the output logical sum of 11011 and 2″,
At that timing, the digital/analog converter 25"c
The luminance signal (Y) portion of the converted video signal is held in a sample hold <S&H) circuit 27. II 1
11 output, the color signal (1) part is sampled and held (S
&H) circuit 28, and the color signal (
Q) portion is held by a number hold (S&H) circuit 29. The outputs of these sample and hold (S & 1-1) circuits 27, 28, and 29 are separated as video analog signals and sent to the Y output terminal 21, ■output terminal 33, and Q.
It is output from the output terminal 34.

As shown above, the video digital demultiplexer can be realized with a simple configuration consisting of a sample and hold (S&I-1) circuit, a circuit that controls its timing, and a digital/analog converter, and can separate luminance signals and color signals. Even if it is included, the sampling period of the video does not change.From this, when one sample is digitized with 8 bits, it becomes 108 Mb/s, and the information can be easily compressed by 1/2.

Another configuration in Figure 1 is the sample hold (
The S&H) circuit can be replaced with an analog switch when the digital-to-analog converter is of flash conversion type. In addition, in the multiplexing section and the separation section, the sample and hold (S&H) circuit in the multiplexing section is replaced with a digital-to-analog converter (A/D) having a wired-OR connection output, and the sample and hold (S&H) circuit in the separation section is replaced with a digital one. - By replacing it with an analog converter, the same operation is possible even if the converter in the original position is removed.

FIG. 5 shows a pipeline-type D P CM (difference P
In an embodiment of the present invention in which CM) is added, FIG. Codes 1 to 17 are the same as in Figure 1, and 4
0 is a code part, 41 (15) is a code part input terminal, 42 and 45 are adders, 43 is a quantization circuit, 44 is a local muntinization decoder, 46 is a predictor, and 47 is an output terminal. The same figure (B
) is the separator and decoder. 21 to 35 are the same as in FIG. 1, 50 is a decoding section, 51 is an input terminal, 52 is an M-child decoder, 53 is an adder, 54 is a predictor, and 55 (22) is a decoding section output terminal. be.

The operation of this multiplex code section in FIG. 5 (△) will be described below.

The operation of the multi-m section is the same as that described in FIG. The difference between this signal and the output signal from the predictor 46 is calculated by the adder 42, and the result is input to the ω child conversion circuit 43. The quantization circuit 43 nonlinearly quantizes the number of input bits (number of levels) to reduce the number of output bits. The output of the quantization circuit 43 is outputted from an output terminal 47 as DPCM encoded data. Further, the signal is input to a local decoder 44 having an inverse characteristic to that of the J-coding circuit 43. The sum of the output signal of the local decoder 44 and the output signal from the predictor 46 is calculated by the adder 45, and the result is input to the predictor 46.

In this way, the signals at the video input terminals 2.3.4 are multiplexed by the multiplexing section 1, and the difference (error) with the prediction from the encoding section 40 is multiplied and outputted to the output terminal 47. In order to compress the encoder 40 to 1/2 using the multiplexing method shown in FIG.
can be non-linearly approximated to output 4 bits (16 levels). With these, video information can be compressed to 1/4.

Next, the operation of the separator and decoder in FIG. 5(B) will be described below.

The DPCM-encoded data is input from an input terminal 51 to an a-coding decoder 52 (having the same characteristics as the local decoder 44) of the decoding section 50, linearly restored, and input to an adder 53. The sum of this signal and the output signal from the predictor 54 is calculated by the adder 53, and the result is input to the separation unit 21 as a DPCM-decoded data output. Additionally, this data is also input to predictor 54.

In this way, the DPCM-encoded data at the input terminal 51 is DPCM-encoded by the decoder 50, and the data from the demultiplexer 21
The video output terminals 32, 3 are separated into a luminance signal and a color signal.
Output from 3.34.

As shown above, the multiplexed video digital signal input to the encoder section is the data string (...
...Y IYQY IYQ...).

FIG. 6 shows an example of the configuration of a Vibration type predictor 46, 54 that processes this data string using one encoder.

The figure shows an example in which the prediction formula (P) is as follows.

Time of dichroic signal (fs/2) In the above equation, z−n indicates data before n-type hydration time. 6(A) shows the overall configuration of the predictor, and FIG. 6(B) occupies the configuration of the delay circuit necessary for prediction, 60 is the predictor, 61
is a predictor input terminal, 62, 65.67 is a delay device, 63.
68 is a coefficient unit, 64° 66 is an adder, 69 is a prediction output terminal, s o t is a delay device, 81 is a delay input terminal, 82
is a delay device (2D), 83 is a switch, 84 is a delay device (D
), 85 is a delay output terminal, 86 is a color signal timing input terminal, 87 is a clock input terminal, and 88 is a reset input terminal.

The operation of this predictor will be described below.

The configuration of the predictor in FIG. 6(A) is a block diagram in which the prediction formula (P) is directly replaced, and the explanation of the operation will be omitted. The delay devices 62, 65, and 67 used in the predictor adjust the luminance signal timing (f
The basic delay times are different depending on the color signal timing (fS/2) and the color signal timing (fS/2).

FIG. 6(B) shows a delay circuit configuration that switches the delay time depending on the luminance signal timing and color signal timing. A delay input terminal 81 is connected to a delay device (20>82 (a two-stage D-
The data input to the FF) is output after 2 clocks (2 sampling time intervals) by driving the clock input terminal 87, and is output to the switch 83 and the delay device (D) 84 (color signal C1
, Q] can be configured with a one-stage D-FF using a dedicated delay device). The delay device (D) 84 takes in data at the color signal timing from the color signal timing input terminal 86 and outputs it to the switch 83 after one color signal cycle (two sampling times).

The switch 83 is controlled by the input from the color signal timing input terminal 86, and the delay device (D) 84 is controlled at the color signal timing.
Then, the luminance signal timing is switched to a delay device (2D) 82 and outputted to a delay output terminal 85.

By controlling the delay device 80 at such timing, it is possible to delay the luminance signal and the color signal without mixing them. Similarly, when the luminance signal and the color signal are each input as consecutive data, it is also possible to use a delay device corresponding to the number of consecutive data.

In addition, initialization of prediction is performed by using the horizontal synchronization signal of the decoded signal and the delay device (2D) 82 and delay device (2D) 82, which are the components of delay.
D) 84 can be reset. Color signal timing (fs
/2) is °゛2'' of the quaternary counter 12.13 in Figure 1.
It can be generated from the logical sum (OR) of the outputs of and 3''.

In this way, by adding a vibrating type DPCM circuit that switches only each delay element between the luminance signal and the color signal to the first embodiment, three circuits are required for each component, and one PCM circuit can handle the video signal. can be compressed. Although the above prediction is intra-scanline prediction, it is clear that it can also be applied to inter-scanline prediction or inter-frame prediction using a one-scanline delay or one-field delay as a delay device.

In the above embodiment, 13.5MHz sampling was used in the NTSC system, but other systems (PAL, SECAM,
It is clear that horizontal and vertical synchronization frequencies (such as ) and different sampling frequencies are also possible.

(Effects of the Invention) As explained above, according to the present invention, a component color video signal can be compressed with a simple configuration with little quality deterioration, and furthermore, by converting the signal into Vibration type DPCM, a single converter can be used. It also has the advantage of being easy to compress.

[Brief explanation of the drawing]

1A and 1B are block diagrams of an embodiment of the multiplexing section and separation section used in the present invention, FIG. The figure shows the relationship between the input signal and output signal in Figure 1, Figure 4 shows the sampling arrangement of each component on both sides, and Figure 5 (
A) and (B) are vibrine-type DPCMs in the multiplexing section and demultiplexing section of the video digital multiplexing and demultiplexing device shown in Figure 1 (A>(B)).
A configuration diagram of another embodiment of the present invention including (differential PCM),
6(A) and 6(B) are block diagrams of the predictor used in FIG. 5. 6.7.8 ~ Sample and hold (S&H) circuit, 9 ~ Even/odd field detection circuit, 10 ~ Horizontal synchronization signal separation circuit, 11 ~ Multiplier (858 times), 12 ~ Quaternary counter,
13 - OR circuit, 14 - Analog-digital conversion (A
/D) Vessel.

Claims (2)

[Claims] (1) In a video digital multiplexing and demultiplexing device for analog component color video signals consisting of luminance and color using the interlaced scanning method, the sampling points to be digitized are points on scanning lines arranged in a grid, and the signals to be multiplexed are , time-division multiplexing is performed in the repeating order of the luminance signal and color signal from the beginning of a certain period of the video field, and the component signal at the sampling point is of the same type as the component signal at the same horizontal position as the adjacent scanning line in the adjacent video field. The method is characterized in that time-division multiplexing is performed while shifting the order for each scanning line so that the video signals are different, and by detecting the beginning of the video field, the repeating order of multiplexing is synchronized and separated into analog component color video signals. Video digital demultiplexer. (2) The sampling points to be digitized are points on the scanning lines arranged in a grid pattern, and the signals to be multiplexed are time-division multiplexed in the repeating order of the luminance signal and chrominance signal from the beginning of a certain period of the video field. The point component signal is time-division multiplexed by shifting the order for each scanning line so that the type of component signal at the same horizontal position is different from that of the adjacent scanning line in the adjacent video field, and the beginning of the video field is detected. In a video digital demultiplexer that synchronizes the repeat order of multiplexing and separates it into analog component color video signals by
Differential PCM) is used, and the delay time of the delay device used for the prediction calculation is set to the sampling time interval of the luminance signal at the time of the luminance signal, and the field is set to the sampling time interval of the chrominance signal at the time of the chrominance signal. 1. A video digital demultiplexing device characterized in that a delay device is switched in synchronization at the beginning of each scanning line, and the value of the delay device used for prediction calculation is initialized at the beginning or end of each field or each frame of each scanning line.