JPS6364831B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic head movement speed detector in a magnetic disk device.

Magnetic disk drives form a large number of data tracks on the information recording surface.
During reading, it is necessary to position the magnetic head over a desired data track at high speed and accurately. As a magnetic head drive method for this purpose, a so-called track servo system (track servo system) uses one of the multiple information recording surfaces as a servo surface.
servo system).

FIG. 1 is a block diagram showing the structure of a track servo system, in which numeral 1 denotes a magnetic disk, both sides of which are provided with magnetic films as recording media. 1st
In the example shown in the figure, two magnetic disks 1 are provided, and thus there are four recording surfaces, of which the lower surface of the lower magnetic disk is used as a servo surface. The recording surface other than this servo surface is a data surface. 2 and 3 are magnetic heads, 2 is called a servo head, and 3 is called a data head. 4 is a head holder, 5 is a head holding mechanism, 6 is a motor, 7 is a position detector, 8 is a speed detector, 9 is a driver, 10 is a speed indicator, and 20
generally indicates a magnetic disk head assembly. The motor 6 drives the head holding mechanism 5 in the radial direction of the magnetic disk 1, but each head holder 4 is fixed to the head holding mechanism 5, and the servo head 2
Since both the servo head 2 and the data head 3 are fixed to the head holder 4, the servo head 2 and each data head 3 move in conjunction with each other. Therefore, if the servo head 2 is positioned correctly, the data head 3
can also be positioned with the same accuracy.

The signal read out by the servo head 2 is converted by the position detector 7 into a position signal representing the location where the servo head 2 is present. This position signal is
The current signal obtained from the driver 9 is sent to the speed detector 8, and the speed detector 8 converts and combines both signals to obtain a speed signal. Both the position signal and speed signal described above are input to the driver 9 and used as control signals for driving the motor 6.
A target signal is input to the driver 9 from a speed indicator 10 . This target signal indicates the target value of the speed at which the magnetic head moves.

FIG. 2 is an explanatory diagram showing the arrangement of servo tracks on the servo surface and the position signal waveform after processing the signals read from the servo tracks.
is a servo head like 2 in FIG. A first servo track 11, a second servo track 12, and a third servo track 13 are installed on the servo surface in advance.
and fourth servo track 14 are written adjacently in sequence. The servo head 2 is movable across these servo tracks. Let x be the positional displacement in the direction across the servo track,
The position signals obtained when the servo head 2 moves in the x direction have waveforms as shown by E _X1 and E _X2 ,
Two position signals having a phase difference of 1/4 period are obtained. W is the width of the servo track, and the core width of the servo head is approximately 2W.

FIG. 3 is a block diagram of a conventional speed detector, and FIG. 4 is an explanatory diagram showing waveforms of various parts of the speed detector shown in FIG. A position signal _EX1 is input to the input terminal a of the speed detector 8, and a position signal _EX2 is input to the input terminal b. FIG. 4 shows the waveforms of various parts when the head starts moving from a stopped state, seeks 16 tracks, and then stops again. Since the moving speed of the head is given as the time differential of the head position, the position signals _EX1 ,
By time-differentiating E _X2 , the speed signal can be obtained. Based on this principle, the speed detector 8 has differentiating circuits 21 and 22 installed at the first stage to differentiate the position signals _EX1 and _EX2 . If perfect line formation is maintained between both the head position and the position signal, the differential signal can be regarded as a velocity signal, but in reality linearity is maintained between the head position and the position signal. This is limited to a range in which the absolute value of the position signal is below a certain value. Therefore, the range in which velocity can be detected by differentiation from a single position signal also becomes discrete. Speed is detected by performing the waveform manipulation described. In the speed detector 8 shown in FIG. 3, the first differentiation circuit 21 differentiates the first position signal E _X1 and outputs the first differentiation signal D _X1 to the output point c, and the second differentiation circuit 22 The second position signal E _X2 is differentiated at and the second differential signal D _X2 is outputted to the output point d. This differential signal correctly detects the speed near its peak point, so if only this portion is sampled and connected, it can be regarded as a speed signal. First inverting circuit 2
3, the first differential signal D _X1 is inverted and outputted to the output point e, and the second inversion circuit 24 inverts the second differential signal D _X2 and outputted to the output point f. To the signal selection circuit 25, the first differentiation circuit output point c,
The second differentiating circuit output point d, the first inverting circuit output point e, and the second inverting circuit output point f are connected as input points, respectively, and the two differential signals D _X1 ,
D _X2 and their inverted signals are input. This signal selection circuit 25 selects only the peak points of these four signals and connects them to form one detection signal.
Output from output point g as E _S. In order to control the selection of signals, an external control input is required, which is generated by checking the voltage levels of the two position signals _EX1 and _EX2 by the voltage comparator circuit 26. via point h, the control signal
Entered as P _C. The control signal P _C is usually given as a single or multiple digital signals, and the combination of these signals determines the signal to be selected. In FIG. 4, the control signal P _C is shown not as an electrical signal waveform but as a symbol representing the signal to be selected. That is, when the state of the control signal P _C is c, the differential signal D _X1 from the input point c is connected to the output point g. The same is true when the states are d, e, and f, and one of the differential signal and the inverted signal is sequentially selected and connected to the output point g. Therefore, the output point g
A detection signal E _S is obtained by connecting these signals. This detection signal E _S is a position signal as described above.
Since it is a result of differentiating and connecting the linear parts of E _X1 and E _X2 , it can be regarded as a speed signal. However, since this detection signal E _S includes high frequency noise, spikes at the time of selection switching, etc., the adder circuit 27 is used for the purpose of removing these. Since this adder circuit 27 has low-pass characteristics, it is possible to remove the above-mentioned high frequency noise and spikes. However, this degrades the speed detection performance during high-speed movement, so in order to correct this, a current signal I _D (not shown) proportional to the motor drive current is introduced from the input point i, and this is used as the detection signal. Speed signal at output point k by adding to E _S
I'm getting _EV .

In the speed detector 8 described with reference to FIG. 3, the characteristics of the differentiating circuits 21 and 22 greatly influence the overall performance. A conventionally used differentiator circuit is generally a combination of an operational amplifier, a resistor, and a capacitor, and the transfer function G _d is expressed by the following equation.

G _d = sT ₀ /(1+sT ₁ )(1+sT ₂ ) [T ₁ >T ₂ ] Here, s=j(2π) (: frequency, j: imaginary unit).

FIG. 5 shows the frequency characteristics of the amplitude and phase of G _d . ₁ indicates the differential upper limit frequency, _{and 2} indicates the integral frequency. Normally, ₁ is approximately several + KHz, and the highest frequency of the position signals EX ₁ and EX ₂ during head movement is a fraction of this. Due to the recent trend toward higher speed magnetic disk devices, the head movement speed continues to increase, and the highest frequency of the position signals _EX1 and _EX2 also increases and approaches the differential upper limit frequency ₁ . This indicates that the phase delay of the differential signals D _X1 and D _X2 after passing through the differentiating circuits 21 and 22 becomes large, making it impossible to accurately detect the speed.
FIG. 6 is a diagram showing the relationship between this phase lag and speed detection, and shows the case where the moving speed of the head is constant. In the figure, D _X1 ', D _X2 ' and E _S ' are all signal waveforms in an ideal case without phase lag caused by the differentiating circuits 21 and 22, and the detection signal E _S ' has a substantially constant value. In reality, as shown in Figure 5, as the signal frequency approaches the differential upper limit frequency, the phase delay increases, so that the peak positions of the differential signals D _X1 and D _X2 are delayed with respect to the timing of the control signal P _C. As a result, the detection signal E _S does not accurately represent the speed. The waveform distortion thus generated cannot be corrected by the low-pass characteristics of the adder circuit 27, and accurate speed detection using the speed signal _EV (not shown in FIG. 6) cannot be performed. As described above, the conventional speed detector has the disadvantage that when the head moves at high speed, the speed detection sensitivity decreases and the waveform quality deteriorates, making it impossible to perform highly accurate speed control.

The present invention has been made to overcome the above-mentioned drawbacks, and provides a speed detector that has sufficient speed detection performance even when moving at high speed.

FIG. 7 is a block diagram showing the configuration of an embodiment of the present invention. The speed detector 8 shown in FIG. 7 differs from the conventional one in that it includes first and second phase shift circuits 28 and 29. Phase shift circuit 2 shown here
8 and 29 are circuits having a transfer characteristic G _p expressed by the following equation.

G _p =1-sT _p /1+sT _pThe transfer characteristic expressed by this equation is as shown in FIG. 8, where the amplitude is constant over the entire frequency range and only the phase changes. Therefore, the phase shift circuit 28,
If the phase characteristics of the differential circuit 29 and the phase characteristics of the differentiating circuits 21 and 22 are set to be approximately the same, the differential signals D _{X1 and} D The phase leads the delayed signals E _D1 and E _D2 by +90°, and can have sufficient differential characteristics. FIG. 9 is an explanatory diagram of the operation in this embodiment. The phase lag B _D of the delayed signals E _D1 and E _D1 with respect to the position signals E _X1 and E _X2 is determined by B _D = 2tan ^-1 / _p . Therefore, the delay time τ _D is τ _D =1/πtan ⁻¹ / _p . On the other hand, _{the phase} lag B _X of _the differential signals D _X1 and D _X2 ^with respect to the position signals E _X1 and ^E _{X2 is} given by _B 1/ _2π (tan ^-1/1 + _tan ^-1/2 ). In the _{embodiment of} the present invention, each circuit constant is set so as to satisfy the relationship _1≈2≈p . In that case, as is clear from the above explanation, the relationship τ _D ≒ τ _X holds true. Therefore, as shown in FIG. 9, the control signal P _C generated based on the delayed signals E _D1 and E _D2 samples the peak points of the differential signals D _X1 and D _X2 and their inverted signals. The speed signal E _V (not shown in FIG. 9) finally obtained is also ideal.

Instead of the above-mentioned all-pass circuit whose transfer characteristic is expressed by G _p , the phase shift circuits 28 and 29 shown in _FIG.
You can also use a low pass filter with

G _L = 1/(1 + sT _p ) ² This transfer characteristic is shown in Figure 10, and the phase delay B _L becomes B _L = 2 tan ^-1 / _p , which provides the same effect as the all-pass circuit described above. It will be done.

FIG. 11 is a block diagram showing the configuration of another embodiment of the present invention. In this example, the seventh
In the embodiment shown in the figure, the adder circuit 27 is replaced with a low-pass filter 30, and correction using the current signal is omitted. As mentioned above, the role of the current signal in the present invention does not extend to the basic principle of the speed detector 8, but is merely an auxiliary one. Therefore, depending on the quality of the input position signals E _X1 and _E Become.

As explained above, in the speed detector according to the present invention, a phase shift circuit is used as a circuit to compensate for the signal delay caused by the differentiating circuit, and by matching the delay characteristics of the two, timing deviations during sampling can be eliminated. , speed can be detected with high accuracy even when moving at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a track servo system, FIG. 2 is an explanatory diagram showing the arrangement of servo tracks and changes in position signals, and FIG. 3 is a block diagram showing an example of a conventional speed detector. Fig. 4 is an explanatory diagram showing an example of waveforms of each part in the speed detector, Fig. 5 is an explanatory diagram showing an example of the frequency characteristics of the differential circuit, and Fig. 6 is an illustration showing the influence of phase lag in a conventional speed detector. 7 is a block diagram showing an embodiment of the present invention, FIG. 8 is an explanatory diagram showing the frequency characteristics of the phase shift circuit of the present invention, and FIG. 9 is a diagram showing the phase compensation effect in an embodiment of the present invention. FIG. 10 is an explanatory diagram showing the frequency characteristics of a phase shift circuit in another embodiment of the invention, and FIG. 11 is a block diagram showing another embodiment of the invention. 1... Magnetic disc, 2... Servo head, 3...
Data head, 4... Head holder, 5... Head holding mechanism, 6... Motor, 7... Position detector,
8...Speed detector, 9...Driver, 10...Speed indicator, 21, 22...Differential circuit, 23, 24...
... Inversion circuit, 25 ... Signal selection circuit, 26 ... Voltage comparison circuit, 27 ... Addition circuit, 28, 29 ...
Phase shift circuit, 30...Low pass filter, E _X1 , E _X2
...Position signal, D _X1 , D _X2 ... Differential signal, P _C ...
Control signal, E _S ... detection signal, E _V ... speed signal,
E _D1 , E _D2 ... Delayed signal. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a magnetic head movement speed detector of a type that detects speed by electrical signal processing from two magnetic head position signals having different phases, a magnetic head movement speed detector for differentiating the first position signal 1 differentiating circuit, a second differentiating circuit for differentiating the second position signal, a first inverting circuit for inverting the output of the first differentiating circuit, and the second differentiating circuit. a second inversion circuit for inverting an output; a first phase shift circuit for delaying the first position signal; and a second phase shift circuit for delaying the first position signal.
a second phase shift circuit for delaying the position signal; and a voltage comparison circuit for detecting the output levels of the first phase shift circuit and the second phase shift circuit to set signal selection timing. , a signal selection circuit for inputting the outputs of the first and second differentiating circuits and the outputs of the first and second inverting circuits and selectively outputting one signal according to the signal from the voltage comparison circuit; an addition circuit for adding the selection circuit output and the current signal, the first differentiation circuit, the second differentiation circuit, the first phase shift circuit and the second
A magnetic head movement speed detector characterized in that the phase delay characteristics of the respective transfer characteristics in the phase shift circuit are approximately equal. 2. In a magnetic head movement speed detector that detects speed by electrical signal processing from two magnetic head position signals having different phases, a first differentiation circuit for differentiating the first position signal; a second differentiating circuit for differentiating a second position signal; a first inverting circuit for inverting the output of the first differentiating circuit; and a first inverting circuit for inverting the output of the second differentiating circuit. a second inversion circuit; a first phase shift circuit for delaying the first position signal;
a second phase shift circuit for delaying the position signal; and a voltage comparison circuit for detecting the output levels of the first phase shift circuit and the second phase shift circuit to set signal selection timing. , a signal selection circuit for inputting the outputs of the first and second differentiating circuits and the outputs of the first and second inverting circuits and selectively outputting one signal according to the signal from the voltage comparison circuit; and a low-pass filter that passes only the low frequency component of the selection circuit output, and the phase of each transfer characteristic in the first differentiating circuit, the second differentiating circuit, the first phase shift circuit, and the second phase shift circuit is provided. A magnetic head movement speed detector characterized by almost equal delay characteristics.