JPS6364149A - Program loading method - Google Patents

Abstract

PURPOSE:To eliminate the removing and actual loading works of a ROM at the time of changing a program and to prevent the generation of the imperfect contact by providing a RAM for accommodating the program, a bus changing- over part, a bus separating part and an address control part at a second substrate. CONSTITUTION:A first substrate 9 to load a CPU to control a device as a whole and the second substrate 10 to load a CPU 12 to realize a part of the function of the device are connected through an external bus line 11. At the time of the rise of the device, the substrate 9 writes the program of the substrate 10 through the line 11 to a RAM 13 for accommodating a program, and finally, the writing completion of the program is detected through the RAM 13 by an address control part 16. The control part 16 respectively sends a control signal to a bus changing-over part 14 and a bus separating part 15, the CPU 12 is connected to an internal bus line 18 and the program is read and executed from the RAM 13. The data are transmitted and received through a RAM 19 between substrates 10 and 9. Thus, without the work such as the removing of an ROM, the program can be changed and the generation of the imperfect contact can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a program loading method for executing a program in a device formed by connecting a plurality of boards each equipped with a CPU.

Prior Art FIG. 2 shows the configuration of a conventional example. In Figure 2,
1 is a first board equipped with a central processing unit (for example, a microprocessor) that manages the entire device; 2 is a central processing unit (for example, a microprocessor) that implements specific functions;
3 is an external pass line for electrically connecting the substrates 1 and 2; 4 is a central processing section; is a read-only memory (ROM) in which the program is stored, 6
7 is an internal bus line for connecting the central processing unit 47 and ROλI5, and 7 is a dual port 1-RAM (DP, RAM) for transmitting and receiving data between the board 1 and the board 2.
, 8 is a power supply section.

Next, the operation of the above conventional example will be explained. When starting up the device, the first board 1 is connected from the power supply section 8 via the external path line 3.
And power is supplied to the second substrate 2. Second board 2
When power is supplied, the central processing unit 4 is reset, reads out a program written in a specific address in the ROM 5, and starts executing the program. Program execution is started on the first board 1 in the same procedure as on the second board 2, and the device is operated by transmitting and receiving data via the Dp and RAM.

Problems to be Solved by the Invention However, in the conventional method described above, the program of the second board 2 is loaded in the ROM 5 in an unrewritable state, so it is necessary to add or add to the functions specific to the second board 2. If there is a change, it is recommended to look into the ROM 5 from the second board 2,
ROM in which new programs that have been added or changed are written
must be mounted on the second substrate 2.

Therefore, it takes time and effort to remove and mount the ROM 5, and if this work is performed frequently, there is a problem in that the device malfunctions due to poor contact between the RON 16 and the second board 2.

The present invention solves these conventional problems,
The purpose of the present invention is to provide an excellent program loading method that eliminates mounting work and does not cause contact failure.

Means for Solving the Problems In order to achieve the above object, the present invention provides a
In place of OM5, a new program storage RAM, an internal/external bus switching section, an address control section, and a CPU bus separation section were provided, and the programs added and changed from the first board 1 were newly provided. It is designed so that it can be written to RAM.

According to the present invention, the program that has been changed from the first board is newly installed in the program storage RA on the second board.
Since it can be written in the hl, the program on the second board can be changed without removing the board, mounting, adding/removing ROM, or mounting work, and has the effect of preventing malfunctions due to the aforementioned contact failure.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, reference numeral 9 denotes a first board equipped with a central processing unit (for example, a microprocessor) for managing the entire device, and 10 denotes a first board equipped with a central processing unit (for example, a microprocessor) for realizing specific functions. A second substrate 11 operates under the control of the central processing section of the substrate 9;
12 is a central processing unit, 13 is a random access memory (RAM) for storing programs, and 14 is an R for storing programs.
An internal/external bus switching section that switches between connecting the AM 13 to an external path line or an internal path line, 15 a bus separation section that separates the central processing section 12 from the internal path line, and 16 a bus separating section from the first board 9; Program storage RAM1
17 is the central processing unit 12;
18 is an internal pass line, 19 is a pull port RAM (DP, RAM) for transmitting and receiving data between the first board 9 and the second board 10.
), 20 is a power supply unit for supplying power to the entire device.

Next, the operation of the above embodiment will be explained. When the device is started up, power is supplied from the power supply section 2o to the first substrate 9 and the second substrate 10 via the external bus line 11. At this time, the switch of the bus switching section 14 of the second board 10 is turned to the external path line 11 side, and the program storage RAM 13 is connected to the external path line 11. At the same time, bus separation section 1
The switch 5 is opened, and the central processing unit 12 is separated from the bus, and access to the inside of the second board 1Q is prohibited. After that, the first substrate 9 is connected to the external pass line 1
1 to the RAM 13 for storing the program via the second board 1.
Write program 0. Finally, in order to notify the address control unit 16 that the program has finished writing, a program is stored! 'tAλ (accesses 13 specific addresses (for example, addresses that are not used by the program to be executed).

The address control section 16 detects the end of program writing and sends the next control signal to the bus switching section 14 and the bus separation section 15. A signal for connecting the program storage RAM 13 to the internal path line 18 is sent to the bus switching section 14, and a signal for connecting the central processing section 12 to the internal path line 18 is sent to the bus separating section 15. The bus switching unit 14 selects the program storage RAM 1 based on the above-mentioned signal.
3 is connected to the internal bus line 18, the bus separation unit 15 connects the central processing unit 12 to the internal pass line 18, and issues a reset signal to the central processing unit 12 using the reset signal line 17. At this stage, the central processing unit 12 is connected to the internal path line 18 and is further reset and initialized, so the program is read out from the program storage RAM 13 and executed. When the second board 1o is started, data is sent and received to and from the first board 9 via the DP and RAM 19.

According to the above embodiment, since the program is stored from the first board 9 to the program storage RAM 13 of the second board 10, it is not necessary to remove the program when changing the program as in the case of ROM, and the program storage RAM 13
This has the advantage that the central processing unit 12 can be easily operated with only the simple operation of accessing the specific address No. 3.

Effects of the Invention As is clear from the above embodiments, the present invention is such that the second board is provided with a program storage RAM, a bus switching section, a bus separation section, and an address control section. Since all programs installed on the second board can be easily changed from the first board, the program on the second board can be changed without removing the board, mounting, removing the ROM, and mounting work, and malfunctions due to the aforementioned contact failures will not occur. It has this effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an apparatus that implements a program loading method according to an embodiment of the present invention, and FIG. 2 is a block diagram of an apparatus that implements a conventional program loading method. 9°°°First substrate, 10...Second substrate, 11...
- External pass line, 12...Central processing unit, 13...
Grogram storage RAM, 14, bus switching section, 16...
- Bus separation section, 16 Address control section, 17... Reset signal line, 18... Internal bus line, 19... Dual port RAM, 20... Power supply section. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (1)

[Claims] A first board equipped with a central processing unit that manages the entire device and a second board equipped with a central processing unit that implements some of the functions of the device are connected via an external bus. 2
A program storage RAM, an address control unit, a bus switching unit, and a bus isolation unit are provided on the second board, and when the power is turned on, the central processing unit of the second board is separated from the internal bus, and the program storage RAM is connected to the external bus. The program is written from the first board to the program storage RAM, and after the writing is completed, the central processing unit of the second board and the program storage RAM are connected to the program storage RAM by a command from the central processing unit of the first board. A program loading method characterized by connecting RAM to an internal bus and executing a program.