JPS6361847B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention aims to provide a digital processing relay, and more particularly, a digital processing relay in which measures are taken to improve reliability against data abnormalities and arithmetic processing errors caused by accidental noise. In general, digital processing relays are based on the assumption that the calculation principle is a "vector", similar to that of conventional analog relays. The amount handled for this purpose is a discrete digital amount, and this digital amount is a value obtained by sampling an analog amount at a constant period and digitizing it using an analog/digital converter. This analog quantity is generally derived from a sine wave generator, so the voltage and current quantity are sine waves, and the digital processing relay that uses digital quantities is also constructed based on the above-mentioned "vector". Become. Measures to improve the reliability of this type of digital relay that have been proposed in the past include testing the validity of the data at the time it is obtained, testing the validity of the quantity during calculation, or This is generally done by incorporating means such as performing multiple consecutive checks at the output stage. Among conventional reliability improvement measures, the following have been proposed to test the validity of data. I _A (t) + I _B (t) + I _C (t) - 3I ₀ (t)≦ε(1) This is the digital quantification of each phase current, A, B, C, and zero-sequence current at time t. I _A (t), I _B (t), I _C
(t), 3I ₀ (t), and if the formula (1) is not satisfied, it is determined that there is a data abnormality in at least one of the sets according to the symmetric coordinate method. This is an ingenious method that allows confirmation to be obtained with a simple method for each sampling. Furthermore, the methods adopted during the calculation are as follows:
There are the following. {I _A (t)} ² + {I _A (t-3h)} ² > = <I ² _T (2) This shows the A-phase overcurrent relay, and the calculation on the left side is the tap setting value I ² If it is greater than or equal to _T , the relay will send out an operating output. Here, I _A (t-3h) indicates data three samplings ago from I _A (t). Here, h is selected so that the sampling time width is usually 30 degrees in electrical angle, so equation (2) is nothing but the sum of (sin) ² and (-cos) ² . Therefore, when the system is in a normal state, Equation (2)
The quantity calculated on the left side of will represent a constant quantity. In this case, for example, 1
Assuming that a sample of data becomes abnormal, it becomes clear over time whether the result is a result of calculation using normal data or a result of calculation using abnormal data after the transient phenomenon ends. It is a method. Measures to improve reliability on the output side include the fact that 30° sampling is currently the mainstream, and the sum of squares is performed using quantities that differ by 90° in electrical angle (for example, as shown in equation (2)). For this reason, the output results of operation and non-operation are checked three times consecutively. All of these are noises caused by accidental phenomena, and it is assumed that only one sample is affected and the data becomes abnormal, but this is because the sampling frequency is 720Hz even though the sampling frequency is 60Hz. This is because there is a time difference of 1.39 ms, and the probability that two sampling values will be abnormal at the same time is considered to be extremely small. If these reliability improvement measures are adopted for digital processing relays, it will be necessary to check each of the input section, arithmetic section, and output section, making the software more complex and requiring a great deal of program creation and debugging. It becomes necessary to expend effort. Furthermore, a completely different method of thinking that is often used to improve reliability is the method of preparing two sets of digital processing devices and using the logical product of the outputs of the judgment results of these two digital processing devices. It is. Moreover, it is preferable to have one processing unit perform calculations using odd-numbered sampling data, and the other processing unit to perform calculations using even-numbered sampling data. . This method is also extremely useful in terms of preventing unnecessary operations. Now, FIG. 1 is a diagram for explaining the output processing of the digital processing relay, and is shown in the case of 30° sampling. Further, the round number (subscripts S ₁ to S ₁₉ ) indicates the sampled number. The Roman numerals ~ are group numbers for explaining the effects of conventional output processing. Here, the relays that are satisfied by the calculation formula of equation (2) are, for example, the sampling numbers 1 and 4, 4 and 7 in FIG. ...Generally, the 3rd and 6th groups, 6 and 9, which are calculated by n+1 and n+4......Generally, n
It can be broken down into a second group calculated by +2 and n+5. The idea is to have multiple digital processing devices, for example three, so that the first one processes the calculations of the first group, the second one processes the calculations of the third group, and the logic of the output of each processing device is If the output is output as a product or by adopting the majority voting method, it will be possible to prevent errors in certain sampling data due to noise caused by an accidental phenomenon, and even if this data is used to produce a calculation result that is in the wrong direction. By taking the above-mentioned processing, it is also possible to completely prevent this type of unnecessary operation. On the other hand, since a single unit has enough leeway in terms of processing amount and processing capacity, in terms of economy and efficiency of processing equipment, it is used with a large loss, and at the same time it is in a non-operating configuration. . This method can be considered to be a hardware-based fail-safe method, but in order to compensate for its disadvantages of economy and usage efficiency, software-based fail-safe methods have been adopted. So, this is the sampling data mentioned above
and n+3, the logical product of the outputs obtained by the groups n+1 and n+4, and the groups n+2 and n+5, and is intended to be output when the operation signal continues at least three times. In other words, it is output only when groups , , , , , , , , , , , , , , , , , , , , , , , , 1,,11,,,11,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,1,, From these explanations, it can be seen that in general, hardware-based fail-safe methods are
Regarding the hardware of the machine, the sampling period is relatively reduced (in the explanation of this figure 1, the electrical angle
(equivalent to 90° sampling).
In software failsafes, the sampling period tends to increase compared to the former. Considering the case where a digital processing relay outputs a malfunction due to noise caused by an accidental phenomenon, there is a limit to increasing the sampling period even if a hardware fail-safe is adopted. This is because, in terms of preventing malfunction signals, even if three digital processing relays with a sampling period of 30 degrees are used to perform calculations using the same data, fail-safe will no longer be established as all three will produce false outputs. But it's clear. The hardware fail-safe principle is that while the first piece of hardware is acquiring data, the second piece of hardware is doing a different job using data from a different time, and During the time when the second hardware is acquiring data, the first hardware is doing a different job using data from a different time, so this method cannot be used unless the usage efficiency is low. be. In order to increase the efficiency, there is a way to increase the sampling frequency, but this increases the burden on the analog-to-digital converter. For example 60
On a Hz basis, the sampling frequency shown in equation (2) is 720Hz, but to give an example, in order to be equivalent to this, for those related to groups 1 to 1 in Figure 1, the sampling frequency should be 720Hz x 3 = 2160Hz. (3) It would be a good thing. In order to make the processing unit efficiency the same as when there is only one piece of hardware, when three pieces of hardware are used, the load on the analog-to-digital converter will be tripled. Furthermore, if you give one piece of hardware to the first group and give it the data corresponding to the odd number, and give another piece of hardware to the second group and give it the data of the even number, then you can perform calculations (this method has already been explained). As mentioned above), the efficiency of the hardware is improved compared to the above, but the efficiency is still halved compared to the case of only one hardware. As mentioned above, a reliability improvement method that relies on software-based fail-safes unnecessarily complicates the software, and a reliability improvement method that relies on hardware-based fail-safes requires an unnecessary amount of space. becomes larger and usage efficiency decreases. It is with this in mind that the present invention aims to provide a simple and reliable digital processing relay. FIG. 2 is a block diagram illustrating an example of implementing software fail-safe using a hardware fail-safe concept. In FIG. 2a, 10 and 20 are first and second algorithm processing circuits, 40 is a logic circuit, and 50 is an output terminal, the gist of which is as follows. The algorithm processing circuit 10 is, for example, suitable for performing calculations using odd-numbered sampling data among the sampling numbers shown in FIG. This is suitable for calculation using sampling data. Considering the algorithm processing circuits 10 and 20 in this way, the hardware described in FIG.
This means that instead of installing two different sampling numbers and performing calculations using odd or even sampling numbers, it is now possible to perform the calculations using software. FIG. 3a shows a block diagram of a specific example of the algorithm processing circuit. In the figure, 1 and 2 are memory circuits, 3 and 4 are multiplication circuits, and 5
100 indicates a subtraction circuit, and input terminal 101 indicates an output terminal. Here, to simplify the explanation, we will use a sampling period of 720Hz, and the algorithm will be described using a scalar relay as an example. This operation is as follows. When data I(t) is received at the input terminal 100 (I(t) = Isin wt), I(t-2h) and I(t-4h) are stored in the storage circuits 1 and 2, respectively. shall be taken as a thing. Each of these data is input to I in multiplication circuits 3 and 4, respectively.
(t)・I(t-4h) and {I(t-2h)},
The outputs of these multiplication circuits 3 and 4 are sent to the subtraction circuit 5 as {I
(t-2h)} ² -I(t)·I(t-4h) is calculated and 3/4I ² is output to the output terminal 101. That is, in the case of 30° sampling, this algorithm uses data at 60° intervals instead of the conventional calculation method of (sin) ² + (-cos) ² , which uses data at 90° intervals, and calculates {I( t-2h)} ² -I(t)×I(t-4h)=3
/4...(4) is calculated to derive a predetermined DC amount from discrete instantaneous values that vary over time. Figure 3b is a further development of Figure 3a, in which compared to the conventional three consecutive verifications,
Sampling numbers (1, 4, 7) shown in Figure 1,
(2, 5, 8), (3, 6, 9), (4, 7, 10)...
Using ......, the calculation results [1, 4, 7], [2,
5, 8], [3, 6, 9] and [2, 5, 8],
This is an algorithm that can perform three consecutive checks: [3, 6, 9], [4, 7, 10]... 11 in the diagram
1 and 112 are storage circuits, 3 and 4 are multiplication circuits, 5 is a subtraction circuit, 100 is an input terminal, and 101 is an output terminal. This operation is as follows. When data I(t) is received at input terminal 100, storage circuits 111 and 112 receive I(t-
3h) and I(t-6h) are stored. Each of these data is inputted by multiplier circuits 3 and 4, respectively.
(t)・I(t-6h) and {I(t-3h)} ² ,
The outputs of these multiplication circuits 3 and 4 are sent to the subtraction circuit 5 as {I
−(t−3h)} ² −I(t)・I(t−6h),
^I2 will be output to the output terminal 101. That is, there is a feature that the data used for the calculation is not used redundantly in any of the three calculation results. In other words, when referring to two consecutive verifications and three consecutive verifications in Figure 3 a and b, this is an attempt to approach the hardware fail-safe concept using a software fail-safe method. It is. Returning now to FIG. 2a, the above-mentioned critical features will now be illustrated by a specific embodiment of the invention. The algorithm processing circuits 10 and 20 are shown in FIG.
Using the algorithm described in , the algorithm processing circuit 10 is caused to perform calculations using the odd numbered sampling data shown in FIG. 1, and the algorithm processing circuit 20 is caused to perform calculations using the even numbered sampling data shown in FIG. It becomes possible to perform calculations using Therefore, even if one of the odd-numbered data causes a data abnormality, the output of the algorithm processing circuit 20, which operates using the even-numbered data, is still usable. Logic circuit 40 performs this. Figure 2b shows another specific example, and Figure 2a shows another specific example.
was a calculation method that used odd and even sampling numbers, whereas here the same sampling numbers are used at the same time, but the algorithm itself is different so that the calculation results will be different for abnormal data. This is what I did. In the figure, 10 and 20 are first and second algorithm processing circuits, respectively, 40 is a logic circuit, and 50 is an output terminal. The operation of this is as follows. In the first algorithm processing circuit 10, for example, {I(t-2h)} ² -{I(t-h)} ² +{I(t)}
² =
I ² /2 (5) is executed, and the second algorithm processing circuit 20 calculates, for example, {I(t-h)} ² -I(t)・I(t-2h)=I ² /4(
6) is executed, and the effects of these things become more apparent when abnormal data is given.

【table】

[Table] This table 1 shows that when the input amplitude value is 1,
When formulas (5) and (6) are used, the abnormal data (90° above)
The following three cases are considered: when is positive and becomes extremely large (+10), when is negative and becomes extremely large (-10), and when it becomes zero. For example, in the case of abnormal data +10, the difference between the two is extremely large as shown in the table above, so it is easily determined that the data is abnormal. Here, it is assumed that all data before 0° is zero, and data introduction starts from 0°. Similarly, abnormal data of -10 and 0 can be easily identified. In this case, the logic circuit 40 calculates equation (5) - 2 x equation (6) = 0 (7), and one judgment condition can be that equation (7) is no longer zero. . Regarding Fig. 2c, we are trying to adopt the majority voting principle with a software fail-safe.The conventional method uses multiple consecutive verifications, but this method uses discrete digital data. , because we are getting a constant DC flow that is not related to the flow of time, the result of one judgment is that it is the result of calculations that accepted correct data, but it should have originally become inoperable due to abnormal data. Since it is difficult to identify whether a device is producing a malfunctioning output or not, verification was performed multiple times in succession to distinguish between them over time. In the figure, 10, 20, and 30 are first, second, and third algorithm processing circuits, and 40 is a logic circuit 50, which is an output terminal. The first algorithm processing circuit 10 and the second algorithm processing circuit 20 are shown in equations (5) and (6), respectively, and in the third algorithm processing circuit 30, for example, {I(t)-I (t-2h)} ² + {I(t-h)} ² = I ²
(8).

【table】

[Table] Table 2 is a tabulation of formula (8) according to Table 1 above. In other words, since three different algorithm processing circuits are used, if these three algorithm processing circuits all come together and output an operation signal, there is no need for multiple consecutive verifications, and even if there is abnormal data, , at least two or more mismatches, eliminating the possibility of unnecessary operations. Furthermore, if different algorithms are adopted as in the present invention, there will be discrepancies between these multiple algorithms even in the so-called transient phenomenon region caused by sudden changes in the system input. There will no longer be a need to avoid this period using unstable methods such as multiple consecutive verifications. That is, if the input enters the stable region, the calculation results of the plural algorithms will automatically match. For this reason, it is preferable that the number of data required to calculate correct calculations be small for a predetermined sampling period, in order to expect high-speed operation. The algorithm exemplified in this invention is 720Hz for the algorithm shown in equation (2).
(60Hz base) In the case of sampling frequency, it is 30 degrees faster in electrical angle. FIG. 4 is a block diagram showing specific examples of the software and fail-safe systems of the present invention. In FIG. 4a, reference numeral 1 indicates an outline section 21, 22 of a digital processing device, algorithm processing circuits, 3 comparison circuits 4, 5 storage circuits, 61, 62 comparison circuits, 7 a tap value comparison circuit, 81, 82. 9 is a judgment circuit, and 9 is a time circuit. 100 to 102 are output terminals. The operation of this block diagram is as follows. Here, the algorithm processing circuits 21 and 22 are the same, and for example, the above-mentioned {I(t-2h)} ² -I
The algorithm is expressed as (t)·I(t-4h)=3/4I ^2. Of course, the hardware is also one, and it is shown separately for convenience of explanation. The numbers attached to the waveforms in the outline section 1 indicate sampling numbers. For example, the algorithm processing circuit 21
is calculated using data of odd sampling numbers, and the algorithm processing circuit 22 is calculated using data of even sampling numbers. The comparison circuit 3 obtains the difference between the amount of calculation using, for example, (3, 5, 7) in the algorithm processing circuit 21 and the amount of calculation using (2, 4, 6) in the algorithm processing circuit 22, and calculates this difference. If it is zero, it is output to the Y side and compared with the tap value I ² _T in the tap value comparison circuit 7. If it is equal to or larger than this, the time-series signal is output to the time-series signal in the time-limiting circuit 9. The comparator circuit 3 converts the signal into a signal and outputs it from the output terminal 100, and when the difference amount does not become zero, output is output to the N side. At this time, data (1,
3, 5) and (-1, 2, 4) are stored, and the comparison circuit 61 stores the output data (3, 5, 7) from the comparison circuit 3 and the output data from the storage circuit 4. Check whether the difference between the calculation amounts using (1, 3, 5) is zero, and if it is zero, then
If it is not zero, it is output to the N side. Similarly, in the comparison circuit 62, the data (2, 4,
Check whether the difference between the calculation amounts using 6) and data (-1, 2, 4) is zero, and if it is zero, output it to the Y side, and if it is not zero, output it to the N side. Output. The judgment circuit 81 knows that the data on the odd number side (in this case, data No. 7) is correct, or that the calculation result of the data on the odd number side (3, 5, 7) is correct, and outputs this to the output terminal 101. . On the other hand, the determination circuit 82 outputs even-numbered data (in this case, data 6
number) is correct, or the even number side data (2, 4,
Knowing that the calculation result in step 6) is correct, the output is sent to the output terminal 102. Therefore, the output terminals 101 and 102 are connected to the comparison circuit 3.
If connected as shown in the figure (dotted line), it is possible to output the correct calculation amount to the Y side and send the correct processing result to the tap value comparison circuit 7. That is, even if a mismatch occurs, if there is a calculation error, it is possible to utilize the correct calculation amount. In this case, there is a possibility that the output from the tap value comparison circuit 7 for one sample will be lost, so if the time limit circuit 9 sends out the output for two samples, the signal will be Even if abnormal data is mixed in or a calculation error occurs during transmission, there will be no instantaneous recovery. This method is desirable as a relay because the output in the transient region is theoretically suppressed even in the event of a sudden change in input, ie, an accident occurs in the system. In FIG. 4b, 1 is a general section of the digital processing device, 21, 22, and 23 are algorithm processing circuits, 3 is a comparison circuit, 4, 5, and 6 are storage circuits, and 61
~63 is a comparison circuit, 7 is a tap value comparison circuit, 8
1, 82, 83 are judgment circuits, 9 is a time limit circuit, and 10
0, 101, 102, and 103 are output terminals. The operation of this block diagram is as follows. Here, algorithm processing circuits 21, 22,
23 is the same algorithm as shown, for example, in FIG. 3b, and of course, the hardware is also one, so it is shown separately for convenience of explanation. The numbers attached to the waveforms in the outline section 1 indicate sampling numbers. Therefore, the algorithm processing circuit 21 processes the data of the first group (sampling numbers 1, 4,
7), the algorithm processing circuit 22 calculates the data of the first group (sampling numbers 2, 5, 8), and the algorithm processing circuit 23 uses the data of the third group (sampling numbers 3, 6, 9). The comparison circuit 3 compares the calculation amounts calculated by these three algorithm processing circuits 21 to 23, and if it determines that at least two amounts are equal, outputs it to the Y side and sets the tap value. The comparison circuit 7 compares the tap value with the tap value I ² _T , and if it is equal to or greater than this, the time-series signal is converted into a continuous signal in the time limit circuit 9 and output to the output terminal 1.
It is output from 00. Comparison circuit 3 indicates that two or more quantities are not equal, or
If it is confirmed that the amounts are uneven, an output is output to the N side. At this time, the sampling data (-3, 1, 4), (-2, 2,
5) and (-1, 3, 6) are stored, and the comparison circuits 61 to 63 store the sampling data (-3, 1, 4) and (1, 4, 7), respectively. and (-2, 2, 5) and (2, 5,
8) Check whether the difference between the calculation amounts using (-1, 3, 6) and (3, 6, 9) is zero,
If it is zero, it is output to the Y side, and if it is not zero, it is output to the N side. The determination circuit 81 outputs an output to the output terminal 101 when the result of the arithmetic processing using at least the data of the first group is correct, the determination circuit 82 performs the processing using at least the data of the first group, and the determination circuit 83 performs the processing using at least the data of the third group. When the results are correct, outputs are output to output terminals 102 and 103. Therefore, by connecting the output terminals 101 to 103 to the comparison circuit 3 as shown (dotted lines), it is possible to output the correct amount of calculation to the Y side and send the correct processing result to the tap value comparison circuit 7. . With this configuration, data 9, 8,
It becomes possible to know whether 7 was abnormal or whether there was a calculation error. Moreover, if the data is correct and there is an error in the calculation, it becomes possible to proactively use the correct calculation result. In this case, the time limit circuit 9 only needs to have a return time limit for two samples. With this configuration, no output is output to the output terminal 100 while an input in the transient region is present, and a desirable condition for a relay is established. In FIG. 4c, 1 is a general section of the digital processing device, 21 and 22 are algorithm processing circuits, and 3
1 is a comparison circuit, 4 and 5 are storage circuits, 61 and 62 are comparison circuits, 7 is a tap value comparison circuit, 81 and 82 are determination circuits, and 9 is a time limit circuit. 100 to 102 are output terminals. The operation of this block diagram is as follows. Here, although the algorithm processing circuits 21 and 22 each use different algorithms and only one piece of hardware is used, the algorithms are shown separately for convenience of explanation. The numbers shown on the waveforms in the outline section 1 indicate sampling numbers. Here, the algorithm processing circuits 21 and 22 are, for example, those shown by equations (5) and (6), and perform calculations using data of sampling numbers (3, 4, 5), respectively. The comparison circuit 3 calculates the difference in the amount of calculation between the calculation results of both algorithm processing circuits 21 and 22.
For example, if the difference obtained by formula (7) is zero, it is output to the Y side and the tap value comparison circuit 7 outputs the tap value I ² _T.
If it is equal to or larger than this, the time-series signal is converted into a continuous signal by the timer circuit 9 and output from the output terminal 100. If the difference does not become zero in comparison circuit 3, N
output to the side. At this time, the storage circuits 4 and 5 respectively store the amount of calculation using data (2, 3, 4), and the comparison circuits 61 and 62 store data (3, 4, 5) and data (2, 3), respectively. , 4), and if it is zero, it is output to the Y side, and if it is not zero, it is output to the N side. When the determination circuit 81 determines that the calculation result of the algorithm processing circuit 21 is correct, the result is transmitted to the output terminal 101. When the determination circuit 82 determines that the calculation result of the algorithm processing circuit 22 is correct, the result is transmitted to the output terminal 102. Therefore, the output terminals 101 to 102 are connected to the comparison circuit 3.
3 as shown (dotted line), it is possible to output the correct calculation amount to the Y side and send it to the tap value comparison circuit 7. In other words, even if a mismatch occurs, if there is a calculation error, it is possible to use the correct data, and it is possible to prevent the output terminal 102 from automatically outputting in response to data abnormality or transient input. It becomes possible by When assuming abnormal data for one sample data, there is a possibility that the output from the tap value comparison circuit 7 will be lost. Even if abnormal data is mixed in or a calculation error occurs during transmission, a desirable relay that does not recover instantaneously can be created. In FIG. 4d, 1 is a general section of the digital processing device, 21, 22, and 23 are algorithm processing circuits, 3 is a comparison circuit, 4, 5, and 6 are storage circuits, 7 is a tap value comparison circuit, and 61 to 63 are Comparison circuit, 8
1, 82, 83 are judgment circuits, 9 is a time limit circuit, and 10
0, 101, 102, and 103 are output terminals. The operation of this block diagram is as follows. Here, algorithm processing circuits 21, 22, 2
3 are different algorithms, for example, each is calculated using the algorithms shown in equations (5), (6), and (8), and requires only one hardware. The numbers attached to the waveforms in outline section 1 indicate sampling numbers. The calculation amount of the calculation results of the algorithm processing circuits 21, 22, 23 is sent to the comparison circuit 3, where:
Comparing these three calculation amounts, we found that at least 2
If it turns out that the amount is equal or greater, it is output to the Y side, and is compared with the tap value I ² _T in the tap value comparison circuit 7, and if it is equal to or larger than this, the timer circuit 9 sets the time. A sequential signal is converted into a continuous signal and output from the output terminal 100. Comparison circuit 3 indicates that two or more quantities are not equal, or
If it is confirmed that the amounts are uneven, an output is output to the N side. At this time, the storage circuits 4, 5, and 6 respectively store the calculation amount calculated using the sampling data (2, 3, 4), and the comparison circuits 61 to 63 store the calculation amount calculated using the sampling data (3, 4, 5), respectively. It is checked whether the difference between the amount of calculation using The judgment circuit 81 knows that at least the algorithm processing circuit 21 has made a calculation error, and the judgment circuit 82
In 83, it is known that an arithmetic error has occurred at least in the algorithm processing circuit 22, and in 83, it is known that at least an arithmetic error has occurred in the algorithm processing circuit 23. The result is transmitted to the comparator circuit 3, and it becomes possible to actively use the correct calculation result. When assuming a data abnormality for one sample, there is a possibility that the output from the tap value comparison circuit 7 will be lost. This has resulted in the emergence of a desirable relay that does not instantly return even when a signal is being sent. As described in detail above, this invention is a digital processing relay that uses an arithmetic processing method that corresponds to data of different odd and even sampling numbers in the same algorithm processing circuit, and checks whether the two arithmetic results match, and if there is a mismatch. In addition, we check whether there is a match or mismatch between the results of arithmetic processing from the past data of the odd and even sampling numbers, and we actively use the data that matches. Since output loss in the event of an abnormality is prevented, it is possible to take measures before data abnormalities or unnecessary operations occur due to calculation errors. In the same algorithm processing circuit, a digital processing relay using an arithmetic processing method corresponding to the data of the 1st to 3rd groups checks whether the calculation results of the three parties match or disagree, and if there is a discrepancy, it belongs to the 1st to 1st groups, respectively. We will check whether there is a match or mismatch between the result of the calculation process from the past data of the sampling number, and we will actively use the data that matches.We will also install a timer circuit to prevent output loss in the event of data abnormality. Since this is prevented, it is possible to take measures before unnecessary operations occur due to data abnormalities and calculation errors. Similarly, data with the same sampling number is used, or a digital processing relay using two different arithmetic processing methods is used to check whether the two arithmetic operations match or do not match, and if there is a mismatch, the data is processed by the respective algorithms. Furthermore, we check whether there is a match or mismatch between the results and actively use the matched data.We also installed a timer circuit to prevent output loss in the event of data abnormality. This allows processing to be performed before unnecessary operations due to calculation errors occur. Similarly, using data with the same sampling number, digital processing relays using three different arithmetic processing methods are used to check whether the calculations of the three parties agree or disagree, and if there is a mismatch, the arithmetic processing is performed by each algorithm. There is further agreement between the results
By detecting discrepancies, we actively use the matching data, and by installing a timer circuit to prevent output loss in the event of a data error, processing can be performed before unnecessary operations due to data anomalies or calculation errors occur. is now possible.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining the output processing of the digital processing relay, Figure 2 is a diagram for explaining the combination of arithmetic processing methods, and Figure 3 is a diagram for explaining a specific example of the algorithm processing circuit in Figure 2. FIG. 4 is a block diagram showing a specific embodiment of the present invention. In the figure, 21 to 23 are algorithm processing circuits, 3 is a comparison circuit, 4 to 6 are storage circuits, and 61 to 6 are
3 is a comparison circuit, 7 is a tap value comparison circuit 81 to 83
9 is a judgment circuit, and 9 is a timer circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a digital processing relay that converts the amount of electricity obtained from the power system into a digital amount at a predetermined sampling period and processes this with a digital processing device, data having an odd sampling number is used. a first algorithm processing circuit that performs arithmetic processing and calculates a value according to the amount of electricity;
a second algorithm processing circuit that performs arithmetic processing on data having even sampling numbers and calculates a value corresponding to the electrical quantity; a first algorithm processing circuit that compares the calculation results of the first and second algorithm processing circuits;
a comparison circuit; a tap value comparison circuit that inputs the calculation result of the first or second algorithm processing circuit and compares it with a preset tap value if the comparison condition is satisfied in the first comparison circuit; a time limit circuit that generates an operational output when the comparison condition is satisfied in the tap value comparison circuit; a first storage circuit that stores the calculation result before the first algorithm processing circuit; and a first storage circuit before the second algorithm processing circuit. a second storage circuit that stores the calculation results of the first and second algorithm processing circuits and the first and second storage circuits when the comparison condition is not satisfied in the first comparison circuit; Second and third comparison circuits each compare the stored previous calculation results, and the comparison results of these second and third comparison circuits determine whether the calculation results of the first and second algorithm processing circuits are good or bad. A digital device comprising a judgment circuit for making a judgment, and a calculation result of the first or second algorithm processing circuit that is determined to be good by the judgment of the judgment circuit is sent to the tap value comparison circuit. processing relay. 2. In a digital processing relay that converts the amount of electricity obtained from the power system into a digital amount at a predetermined sampling period and processes this with a digital processing device, the sampling data of the first to third groups of sampling numbers that are in different combinations A first to third algorithm processing circuit that performs arithmetic processing using each of the above and calculates a value corresponding to the electric quantity, a first comparison circuit that compares the calculation results of these third to third algorithm processing circuits, and If the comparison condition is satisfied in the first comparison circuit, a tap value comparison circuit inputs the calculation result of any one of the first to third algorithm processing circuits and compares it with a preset tap value; a time limit circuit that generates an operating output when a comparison condition is satisfied in the comparison circuit;
first to third storage circuits that respectively store the calculation results before the first to third algorithm processing circuits; and when the comparison conditions are not satisfied in the first comparison circuit, the first to third algorithms second to fourth comparison circuits that respectively compare the calculation results of the processing circuit and the previous calculation results stored in the first to third storage circuits, and the comparison results of these second to fourth comparison circuits , comprising a determination circuit that determines whether or not the calculation results of the first to third algorithm processing circuits are acceptable; A digital processing relay characterized in that a calculation result is sent to the tap value comparison circuit. 3. In digital processing relays, which convert the amount of electricity obtained from the power system into digital amounts at a predetermined sampling period, and process this with a digital processing device, each uses sampling data at the same time and uses different algorithms. A first and second algorithm processing circuit that performs arithmetic processing and calculates a value corresponding to the electric quantity, a first comparison circuit that compares the calculation results of these first and second algorithm processing circuits, and this first If the comparison condition is satisfied in the comparison circuit of
a tap value comparison circuit which inputs the calculation result of the algorithm processing circuit and compares it with a preset tap value; a time limit circuit which generates an operation output if the comparison condition is satisfied in this tap value comparison circuit; A comparison condition is satisfied in a first storage circuit that stores the calculation result before the algorithm processing circuit, a second storage circuit that stores the calculation result before the second algorithm processing circuit, and the first comparison circuit. second and third comparison circuits that compare the calculation results of the first and second algorithm processing circuits with the previous calculation results stored in the first and second storage circuits, respectively; a determination circuit for determining the acceptability of the calculation results of the first and second algorithm processing circuits based on the comparison results of the second and third comparison circuits; Alternatively, a digital processing relay characterized in that the calculation result of the second algorithm processing circuit is sent to the tap value comparison circuit. 4 Digital processing relays that convert the amount of electricity obtained from the power system into digital amounts at a predetermined sampling period and process this with a digital processing device, each using sampling data at the same time and using different algorithms. The first step performs arithmetic processing and calculates a value corresponding to the above-mentioned amount of electricity.
- a third algorithm processing circuit; a first comparison circuit that compares the calculation results of the first to third algorithm processing circuits; if the comparison conditions are satisfied in the first comparison circuit, the first to third algorithm processing circuits a tap value comparison circuit which inputs the calculation result of one of the algorithm processing circuits 3 and compares it with a preset tap value;
a timer circuit that generates an operational output if the comparison condition is satisfied in the tap value comparison circuit; first to third storage circuits that store the calculation results of the first to third algorithm processing circuits, respectively; When the comparison condition is not satisfied in the first comparison circuit, the calculation results of the first to third algorithm processing circuits and the first
- second to fourth comparison circuits that respectively compare the previous calculation results stored in the third storage circuit;
~ According to the comparison result of the fourth comparison circuit, the above-mentioned first ~
A determination circuit is provided for determining the quality of the calculation result of the third algorithm processing circuit, and the calculation result of the first, second, or third algorithm processing circuit that is determined to be good based on the determination result of the determination circuit is A digital processing relay characterized in that the data is sent to a tap value comparison circuit.