JPS6361786B2 - - Google Patents
Info
- Publication number
- JPS6361786B2 JPS6361786B2 JP15915182A JP15915182A JPS6361786B2 JP S6361786 B2 JPS6361786 B2 JP S6361786B2 JP 15915182 A JP15915182 A JP 15915182A JP 15915182 A JP15915182 A JP 15915182A JP S6361786 B2 JPS6361786 B2 JP S6361786B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- semiconductor device
- glass
- mesa groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000011521 glass Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
従来よりサイリスタ等において、高い信頼性と
すぐれた量産性を得る目的で、順、逆方向の印加
電圧を阻止するｐ−ｎ接合の露出部分をガラス膜
で被覆する、いわゆるガラスパツシベーシヨン法
が多く適用されてきた。DETAILED DESCRIPTION OF THE INVENTION Conventionally, in thyristors and the like, for the purpose of obtaining high reliability and excellent mass production, the exposed part of the p-n junction that blocks applied voltage in the forward and reverse directions is covered with a glass film. The so-called glass pinning method has been widely applied.
第１図に従来のガラスパツシベーシヨン形サイ
リスタの製造プロセスの例を示す。 FIG. 1 shows an example of the manufacturing process of a conventional glass casing type thyristor.
第１図ａの如くｎ形シリコン基板１の両主面よ
りGaの拡散を行なつてｐ形領域２及び３を形成
し、しかる後、ｐ形領域３の一部に選択的にｎ形
エミツタ領域４を形成した後、第１図ｂに示す如
く、基板の両主面より選択的に基板のエツチング
を行なつて、ｐ−ｎ接合５又は６より深いメサ溝
７及び８を形成し、このメサ溝の表面に粉末状の
ガラスを被着させた後、所定の温度に加熱すれ
ば、第１図ｃに示す如く接合５，６の露出部分が
ガラス膜１０で覆われたサイリスタの構造が得ら
れる。以上のプロセス中、メサ溝の形成法やガラ
ス膜の形成法に関しては周知である。以上の後、
第１図ｄの如く所定の場所に電極１１，１２，１
３を形成した後、Ａ−A′の線で切断すれば、サ
イリスタチツプが得られる。 As shown in FIG. 1a, p-type regions 2 and 3 are formed by diffusing Ga from both main surfaces of n-type silicon substrate 1, and then n-type emitters are selectively formed in a part of p-type region 3. After forming the region 4, as shown in FIG. 1B, the substrate is etched selectively from both main surfaces of the substrate to form mesa grooves 7 and 8 deeper than the p-n junction 5 or 6. After coating powdered glass on the surface of this mesa groove and heating it to a predetermined temperature, a thyristor structure in which the exposed portions of the junctions 5 and 6 are covered with a glass film 10 as shown in FIG. is obtained. In the above process, the method of forming the mesa groove and the method of forming the glass film are well known. After the above,
Electrodes 11, 12, 1 are placed at predetermined locations as shown in Figure 1d.
3 and then cut along the line A-A' to obtain a thyristor chip.
しかるに、以上の構造では、メサ溝７及び８が
それぞれ対向する面にあるため、メサ溝部分のｎ
領域１の残り巾Ｄが狭くなり、ウエハが非常に割
れやすく、歩留りの著しい低下を来たすという欠
点がある。また、これを防ぐためにｎ領域１の層
を厚くするとサイリスタの電気的特性、例えばオ
ン電圧やターンオフ特性を劣化させるという問題
があつた。 However, in the above structure, since mesa grooves 7 and 8 are located on opposing surfaces, n of the mesa groove portion
There is a drawback that the remaining width D of the region 1 is narrow, the wafer is very easy to break, and the yield is significantly reduced. Furthermore, if the layer of n-region 1 is made thicker in order to prevent this, there is a problem in that the electrical characteristics of the thyristor, such as on-voltage and turn-off characteristics, deteriorate.
以上の欠点を補うために考案されたのが、第２
図に示す構造である。第２図ａは第１図ａの構造
を作るに先立ち、両主面の互いに対向する部分に
選択的にｐ形不純物を拡散して、両主面から形成
されたｐ形領域を貫通させて分離領域９（第２図
ａ）を形成することにより得られる。しかる後、
第２図ｂの如く選択的にメサ溝８を形成した後、
従来と同様の方法によつてガラス膜、電極を形成
し、切断すればサイリスタのチツプが得られる。 The second product was devised to compensate for the above drawbacks.
This is the structure shown in the figure. FIG. 2a shows that prior to creating the structure of FIG. 1a, p-type impurities are selectively diffused into opposing portions of both main surfaces to penetrate the p-type regions formed from both main surfaces. This is obtained by forming a separation region 9 (FIG. 2a). After that,
After selectively forming mesa grooves 8 as shown in FIG. 2b,
Thyristor chips can be obtained by forming a glass film and electrodes using the same conventional methods and cutting them.
この構造によれば、メサ溝は基板の片面にしか
なく、従つてウエハの割れによる歩留り低下は防
げる。 According to this structure, the mesa groove is present only on one side of the substrate, and therefore, a decrease in yield due to cracking of the wafer can be prevented.
ところが、第２図の構造において、次のような
問題点がある。すなわち、以上の如き目的に使用
されるガラスはその膨張係数がシリコン基板に近
いものが用いられるが、ガラスの膨張係数をシリ
コンの値に近づけるとガラスの軟化温度が高く、
かつガラス膜の電気的安定性が悪くなるという特
徴があり、一般にガラスの膨張係数はシリコンよ
り大きくなる。そのため、第２図の構造によれば
ガラス粉末を被着し、加熱してガラス膜を形成す
ると、ガラスのある面を内側にしてシリコン基板
が反る。 However, the structure shown in FIG. 2 has the following problems. In other words, the glass used for the above purpose has an expansion coefficient close to that of the silicon substrate, but when the expansion coefficient of the glass approaches the value of silicon, the softening temperature of the glass becomes high;
Another characteristic is that the electrical stability of the glass film deteriorates, and the expansion coefficient of glass is generally larger than that of silicon. Therefore, according to the structure shown in FIG. 2, when glass powder is deposited and heated to form a glass film, the silicon substrate is warped with the glass side facing inside.
本発明は以上の欠点に鑑みてなされたもので、
シリコン基板の反りなく、第２図の形を得るため
の改良された構造を与えるものである。 The present invention has been made in view of the above drawbacks.
This provides an improved structure for obtaining the shape shown in FIG. 2 without warping the silicon substrate.
ｐ形不純物であるボロンはその原子径がシリコ
ンに比べ小さく、ボロンをシリコン基板の片面に
高濃度に拡散すると、拡散された面を内側にして
基板が反るという特徴があり、本発明はこれを利
用したものである。 Boron, which is a p-type impurity, has a smaller atomic diameter than silicon, and when boron is diffused at a high concentration on one side of a silicon substrate, the substrate warps with the diffused side facing inside. This is what was used.
第３図に本発明による構造の製造方法を示す。
第２図と同様にして、ｎ基板１にｐ形分離領域
９、ｐ形領域２，３を形成した後、後工程にてメ
サ溝を形成すべき面に対向する面にボロンを高濃
度に拡散してp+領域１４を形成する。しかる後、
第２図と同様の方法において、ｎ領域４及びメサ
溝８、電極を形成すれば、第３図の如きサイリス
タの構造が得られる。この場合、メサ溝を対向す
る面にボロンの高濃度拡散層があるため、ガラス
による反りとボロンによる反りが相殺して、ウエ
ハ全体の反りは大きく軽減される。以上の効果は
ボロンの表面濃度が1018／cm3以上ある場合、特に
有効である。 FIG. 3 shows a method of manufacturing a structure according to the invention.
After forming the p-type isolation region 9 and the p-type regions 2 and 3 on the n-type substrate 1 in the same manner as shown in FIG. Diffusion to form p + region 14. After that,
By forming the n-region 4, mesa groove 8, and electrodes in the same manner as in FIG. 2, a thyristor structure as shown in FIG. 3 can be obtained. In this case, since there is a highly concentrated boron diffusion layer on the surface facing the mesa groove, the warpage due to the glass and the warpage due to the boron cancel each other out, and the warpage of the entire wafer is greatly reduced. The above effects are particularly effective when the surface concentration of boron is 10 18 /cm 3 or more.
以上の如く、本発明によれば、シリコン基板の
片側にのみメサ溝が形成され、このメサ溝にガラ
ス被膜が形成されたサイリスタにおいて、シリコ
ン基板を厚くすることなく、ウエハの反りを軽減
することができるという優れた効果を有する。 As described above, according to the present invention, in a thyristor in which a mesa groove is formed only on one side of a silicon substrate and a glass coating is formed on the mesa groove, warpage of the wafer can be reduced without increasing the thickness of the silicon substrate. It has the excellent effect of being able to
第１図及び第２図は従来のサイリスタの製造方
法を示す工程別断面図、第３図は本発明の一実施
例を示す断面図である。
１はｎ形シリコン基板、２及び３はｐ形領域、
４はｎ形領域、７はメサ溝、９は分離領域、１０
はガラス膜、１１，１２，１３は電極、１４は
p+ボロン拡散層である。
1 and 2 are cross-sectional views showing each step of a conventional thyristor manufacturing method, and FIG. 3 is a cross-sectional view showing an embodiment of the present invention. 1 is an n-type silicon substrate, 2 and 3 are p-type regions,
4 is an n-type region, 7 is a mesa groove, 9 is an isolation region, 10
is a glass film, 11, 12, 13 are electrodes, and 14 is a glass film.
It is a p + boron diffusion layer.
Claims (1)
選択的に形成された分離領域、両主面より所定の
深さで形成された第１及び第２のｐ形領域、該分
離領域によつて囲まれた領域内の該第２のｐ形領
域の一部に形成された第２のｎ形領域、該第２の
ｎ形領域をとり囲み、該第２のｐ形領域とｎ形基
板とによつて形成されるｐ−ｎ接合に達する深さ
で形成されたメサ溝、該メサ溝の表面に被着され
たガラス膜よりなる半導体装置において、該第１
のｐ形領域の表面にボロン拡散によつて形成され
たp+領域があることを特徴とする半導体装置。 ２ p+形領域のボロンの表面濃度は1018atom／
cm3以上であることを特徴とする特許請求の範囲第
１項記載の半導体装置。[Claims] 1. A separation region selectively formed to penetrate both main surfaces of an n-type silicon substrate, and first and second p-type regions formed at a predetermined depth from both main surfaces. , a second n-type region formed in a part of the second p-type region in a region surrounded by the isolation region; A semiconductor device comprising a mesa groove formed at a depth reaching a p-n junction formed by a shaped region and an n-type substrate, and a glass film deposited on a surface of the mesa groove.
A semiconductor device characterized in that there is a p + region formed by boron diffusion on the surface of the p-type region. The surface concentration of boron in the 2 p + type region is 10 18 atoms/
2. The semiconductor device according to claim 1, wherein the semiconductor device has a diameter of cm 3 or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15915182A JPS5947765A (en) | 1982-09-10 | 1982-09-10 | Semicondutor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15915182A JPS5947765A (en) | 1982-09-10 | 1982-09-10 | Semicondutor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5947765A JPS5947765A (en) | 1984-03-17 |
| JPS6361786B2 true JPS6361786B2 (en) | 1988-11-30 |
Family
ID=15687372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15915182A Granted JPS5947765A (en) | 1982-09-10 | 1982-09-10 | Semicondutor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5947765A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08102342A (en) * | 1994-09-30 | 1996-04-16 | Japan Aviation Electron Ind Ltd | Connecting structure of circuit board with flexible cable |
-
1982
- 1982-09-10 JP JP15915182A patent/JPS5947765A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08102342A (en) * | 1994-09-30 | 1996-04-16 | Japan Aviation Electron Ind Ltd | Connecting structure of circuit board with flexible cable |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5947765A (en) | 1984-03-17 |
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