JPS636169B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge redistribution type analog-to-digital converter that allows translation of a transfer function with respect to an analog input voltage.

A commonly used n-bit charge redistribution type analog-to-digital converter is shown in FIG. In particular, FIG. 1 shows the unit capacitance, capacitor array, selection switch array, other selection switches, and voltage comparators of the analog-to-digital converter. The unit capacity, capacity array, selection switch array, and other selection switch parts are hereinafter referred to as the DA section.

In FIG. 1, 1 is the unit capacity. 2 is a capacitor array with unit capacitance 1 times 1, 2 times, 4 times,...
…2 Multiple capacitances 2 ₁ , 2 ₂ , 2 ₃ with ^n-1 times the weight
...consists of 2n. One ends of these capacitors 2 ₁ to 2n are commonly coupled to one end of the unit capacitor 1 and connected to the "-" input terminal of the voltage comparator 4 . 3 is a selection switch array, analog switch SW ₁ ,
SW ₂ , SW ₃ ... Consists of SWn. analog switch
The movable terminals a of SW ₁ to SWn are individually coupled to the other ends of the capacitors 2 ₁ to 2n of the capacitor array 2. Further, the first fixed terminal b is connected to the movable terminal a of the analog switch SW _B together with the other end of the unit capacitor 1. Furthermore, the second fixed terminal c is coupled to the reference voltage V _R1 of the analog-to-digital converter. The analog switch SW _B has a first fixed terminal b coupled to the analog input voltage Vin. On the other hand, the second fixed terminal c is coupled to ground (GND). V _R2 is the reference voltage of voltage comparator 4 and is coupled to the "+" input terminal of voltage comparator 4. The output terminal of this voltage comparator 4 is OUT
In addition to being taken out as an analog switch
The output terminal and the "-" input terminal are connected via SW _A.

The operation of such an analog-to-digital converter will be explained. First, as the first step of operation,
The analog switch SW _A is closed, and the analog switches SW _B , SW ₁ , SW _{2 , .} . . SWn are brought into the state shown in the figure (the movable terminal a is connected to the first fixed terminal b). As a result, the analog input voltage Vin is taken in. Next, release analog switch SW _A , and connect movable terminal a of analog switch SW _B to the second
Connect to fixed terminal c. In this state, P
The voltage V _P0 at the point (the part where one end of capacitors 1, _{2 1} , 2 ₂ ... 2n are commonly coupled) is as shown in Figure 2 (in Figure 2, Vc indicates the voltage across the capacitors). Then, V _P0 = V _R2 −Vin.

Next, as the second step, switch the analog switch.
Comparisons are made by sequentially moving SWn to _SW1 as shown in Figure 3. First, the analog switch
Move the movable terminal a of SWn toward the second fixed terminal b. The voltage V _P1 at point P at this time is V _P1 =V _P0 +1/2V _R1 =V _R2 -Vin+1/2V _R1 , and when compared in this state, (1) (MSB)V _P1 -V _R2 =- If Vin+1/2V _R1 >0 or <0>0, the MSB is set to “0”, and V _P1 = V _P0 = V _R2 −Vin... (In analog switch SWn, movable terminal a is connected to first fixed terminal B. (Return to side) <0, MSB is set to "1", V _P1 = V _P0 + 1/2 V _R1 ... (In analog switch SWn, movable terminal a is held on the second fixed terminal b side) Thus, the comparison of the MSB (nth bit) is now performed.

Next, by moving the movable terminal a of the analog switch SW _o-1 to the second fixed terminal b side, the voltage V _P2 at point P becomes V _P2 = V _P1 + 1/4 V _R1 , and the same goes up to LSB. Perform the comparison and finish the conversion.

(2) V _P2 −V _R2 =V _P1 +1/4V _R1 −V _R2 >0 or <0 (3) V _P3 −V _R2 =V _P2 +1/8V _R1 −V _R2 >0 or <0 (n-1 ) V _Po-1 −V _R2 =V _Po-2 +1/2 ^n-1 V _R1 −V _R2 >0 or <0 (n) (LSB) V _Po −V _R2 =V _Po-1
+1/2 ⁿ V _R1 −V _R2 >0 or <0...(1) Conversion is performed as described above, but equation (1) is a general equation for this charge redistribution type analog-to-digital converter, As is clear from this equation, this analog-to-digital converter performs comparison in 1/2 ⁿ V _R1 (1LSB) steps.

Further, the conversion result shows a transfer function as shown in FIG. 4 and a quantization error distribution with respect to the analog input level. As is clear from this figure, the quantization error distribution is fixed and biased by -1/2 LSB.

However, this must be taken into consideration when using this analog-to-digital converter, and also causes a limitation in the range of use of this analog-to-digital converter.

This invention was made in view of the above points, and by enabling parallel movement of the transfer function with respect to the analog input voltage, it is possible to give a degree of freedom to the quantization error distribution with respect to the analog input voltage,
Moreover, by using the DA section and the voltage comparator for both the operation of creating the reference voltage of the voltage comparator and the comparison operation, it can be realized without increasing the chip size. - The purpose is to provide digital converters.

DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of the present invention, a 4-bit analog-to-digital converter will be described below with reference to the drawings. Moreover, first, as a first example, a case will be described in which the quantization error distribution is set to ±1/2 LSB with respect to the analog input level, as shown in FIG.

FIG. 6 shows a 4-bit analog-to-digital converter according to the first embodiment of the present invention, particularly its DA section,
FIG. 2 is a circuit diagram showing a voltage comparator. In this figure, 11 is a unit capacity. Further, 12 is a capacitor array, which has four capacitors 12 1 , 12 2 , 12 ₃ , which have weights of ₁ , ₂ , 4, and 8 times the unit capacitor 11.
Consists of 12 ₄ . One end of each of these capacitors 12 ₁ to 12 ₄ is commonly coupled with one end of the unit capacitor 11 . SW ₁₁ is an analog switch serving as a first selection switch means, the first fixed terminal b of which is coupled to the analog input voltage Vin, and the second fixed terminal c coupled to ground (GND). Reference numeral 13 denotes a selection switch array consisting of four analog switches (selection switch means) SW ₀₁ to _{SW 04} . The analog switches SW ₀₁ , SW ₀₂ , SW ₀₃ , and SW ₀₄ have movable terminals a connected to the four capacitors 12 ₁ , 1 of the capacitor array 12 .
2 ₂ , 12 ₃ , and 12 ₄ are individually coupled to the other ends.
Moreover, the first fixed terminal b is connected to the analog switch.
The second fixed terminal c is coupled to the movable terminal a of SW ₁₁ and the reference voltage (first reference voltage) V _R1 of the analog-to-digital converter. A series circuit of resistors R ₁ and R ₂ is coupled between this reference voltage V _R1 and ground.
The values of resistors R ₁ and R ₂ are equal. This makes the resistance R ₁
1/2 V _R1 is taken out as the second reference voltage at the voltage dividing point X of and R ₂ . SW ₁₂ is an analog switch serving as a second selection switch means, and a movable terminal a is connected to the other end of the unit capacitor 11. Further, the analog switch SW ₁₂ has a first fixed terminal b coupled to the movable terminal a of the analog switch SW ₁₁ , and a second fixed terminal c coupled to the voltage dividing point X. 14 is a voltage comparator, and the "-" input terminal (first
An analog switch SW ₁₃ as a third selection switch means is coupled between the signal input section (signal input section) and the output terminal (signal output section). SW ₁₄ is an analog switch serving as a fourth selection switch means, and a movable terminal a is connected to a point P where one ends of the capacitors 11, 12 ₁ to 12 ₄ are commonly connected. Further, the first fixed terminal b is connected to the "-" input terminal of the voltage comparator 14,
The second fixed terminal c is coupled to the first common coupling portion _Y1 . SW ₁₅ is an analog switch serving as fifth selection switch means, and its movable terminal a is coupled to the output terminal of the voltage comparator 14. Further, the first fixed terminal b is coupled to a digital signal output section (not shown) and also to the timing circuit 15, and the second fixed terminal c is coupled to the second common coupling section _Y2 . SW ₁₆ is an analog switch as a sixth selection switch means, the second fixed terminal c is coupled to the first common coupling portion _Y1 , and the first fixed terminal b is coupled to the second common coupling portion _Y2 . is combined with
A voltage holding capacitor C' is connected between the movable terminal a of the analog switch SW ₁₆ and the ground.
SW ₁₇ is an analog switch as a seventh selection switch means, and a movable terminal a is connected to the voltage comparator 14.
It is coupled to the "+" input terminal (second signal input section) of the "+" input terminal (second signal input section). Further, the second fixed terminal c is connected to the first common coupling portion _Y1 , and the first fixed terminal b is connected to the voltage dividing point X.
is combined with

FIG. 7 shows a time chart of such an analog-to-digital converter. In this FIG. 7, the "0" state is the analog switch SW ₀₁ to SW ₀₄ , SW ₁₁ , SW ₁₂ , SW ₁₄ to _{SW 17} in FIG.
, the movable terminal a is the first fixed terminal b
Analog switch SW ₁₈ is shown in the open state. Conversely, the "1" state indicates a state in which the movable terminal a is connected to the second fixed terminal c and a closed state. The analog switches SW ₀₁ to _{SW 04} and SW ₁₁ to SW ₁₇ are controlled by the output signal of the timing circuit 15. Also,
In FIG. 7, * indicates a delay time to prevent malfunction.

The operation of the analog-to-digital converter will be described below with reference to the time chart shown in FIG.
First, as a first step, turn on the analog switch.
Close SW ₁₈ and analog switch SW ₁₁ ,
Connect the movable terminal a of SW ₁₅ to the second fixed terminal c.
Connect to other analog switches SW ₀₁ ~
Movable terminal a of SW ₀₄ , SW ₁₂ , SW ₁₄ , SW ₁₆ , SW ₁₇
is connected to the first fixed terminal b. In this state, the voltage at point P is V _P =1/2V _R1 .

The second step is analog switch SW ₁₄ ,
Connect the movable terminal a of SW ₁₇ to the second fixed terminal c.
Move it to the side.

In the third step, in the state of the second step, the movable terminal a of the analog switch SW ₁₂ is brought to the side of the second fixed terminal c. At this time, V _P is: V _P =1/2V _R1 +1/16×1/2V _R1 =1/2V _R1 +1/3
2V _R1 = 1/2V _R1 + 1/2LSB, and this voltage is held in the capacitor C' through the voltage follower (voltage comparator 14).

In the fourth step, open analog switch SW ₁₃ and close all other analog switches.
It is assumed that the movable terminals a of SW ₀₁ to _{SW 04} , SW ₁₁ , SW ₁₂ , and SW ₁₄ to _{SW 17} are connected to the first fixed terminal b.

In the fifth step, analog switch SW ₁₃ is closed and the analog input voltage is acquired.

In the sixth step, open the analog switch SW ₁₃ and connect the movable terminal a of the analog switch SW ₁₁ to the second
Move it to fixed terminal c. At the same time, the movable terminals a of analog switches SW ₁₆ and SW ₁₇ are connected to the second fixed terminal c.
Move it to the side. At this time, the voltage V _P0 at point P becomes V _P0 = 1/2V _R1 −Vin, and the voltage at point Q (“+” of voltage comparator 14
The voltage V _Q at the input terminal) changes to V _Q = 1/2 V _R1 + 1/2 LSB, which becomes the reference voltage of the voltage comparator 14 from the seventh step onwards.

As the seventh step, analog switch SW ₀₄
Move the movable terminal a toward the second fixed terminal c. The voltage V _P1 at point P at this time is V _P1 =V _P0 +1/2V _R1 =1/2V _R1 -Vin+1/2V _R1 , and when compared in this state, (1)(MSB)V _P1 -V _Q = 1/2V _R1 -Vin+1/2V _R1 - (1/2V _R1 +1/2LSB) = -Vin+ (1/2V _R1 -1/2LSB) >0 or <0...(2) If >0, the MSB is “ 0" is set, V _P1 = V _P0 = 1/2 V _R1 - Vin... (The movable terminal a of analog switch SW ₀₄ returns to the first fixed terminal b side.) If <0, the MSB is set to "1". V _P1 = V _P0 + 1/2 V _R1 ... (Analog switch SW ₀₄ maintains the state in which the movable terminal a is connected to the second fixed terminal c side), and the following is the same as the explanation in Fig. 1. (2)V _P2 −V _Q =V _P1 +1/4V _R1 −(1/2V _R1 +1/2LSB
) =V _P1 -1/2V _R1 + (1/4V _R1 -1/2LSB) >0 or <0 ...(3) (3)V _P3 -V _Q =V _P2 +1/8V _R1 - (1/2V _R1 +1/2LSB
) =V _P2 -1/2V _R1 + (1/8V _R1 -1/2LSB) >0 or <0 ...(4) (4)V _P4 -V _Q =V _P3 +1/16V _R1 - (1/2V _R1 +1/2LSB
) =V _P3 -1/2V _R1 + (1/16V _R1 -1/2LSB) >0 or <0...(5). As is clear from these equations (2) to (5),
Comparisons are always made using voltages that have dropped by 1/2 LSB.

As explained above, according to the first embodiment,
As shown in FIG. 5, the quantization error distribution for the analog input level can be made ±1/2 LSB by parallel movement of the transfer function. Further, since the DA section and the voltage comparator 14 are used for both the operation of creating the reference voltage of the voltage comparator 14 and the comparison operation, this can be realized without increasing the chip size. Moreover, it can be realized very easily using conventional techniques.

In the first embodiment, the voltage at the voltage dividing point _X in FIG. 4 is set to _V However, by changing this voltage _VX , it becomes possible to realize a quantization error distribution with even more freedom.

In the first embodiment, it has been explained that the quantization error distribution is moved in the (+) direction, but by changing the timing, it is also possible to move it in the (-) direction. As a second example, a case will be described in which the center of the quantization error distribution with respect to the analog input level is -1 LSB, as shown in FIG.

The circuit diagram is the same as the first embodiment above, and the sixth embodiment
As shown in the figure. The operation will be explained below using FIG.

As a first step, analog switch SW ₁₃
, and connect the movable terminals a of the analog switches SW ₁₁ and SW ₁₅ to the second fixed terminal c, and further connect all the movable terminals a of the analog switches SW ₁₂ and SW ₀₁ to _{SW 04} to the second fixed terminal c. Connect to c side. Other analog switches SW ₁₄ , SW ₁₆ ,
It is assumed that SW ₁₇ has a movable terminal a connected to a first fixed terminal b. In this state, the voltage V _P at point P is
V _P = 1/2 V _R1 .

The second step is analog switch SW ₁₄ ,
Connect the movable terminal a of SW ₁₇ to the second fixed terminal c.
to the side.

In the third step, in the state of the second step, the movable terminal a of the analog switch SW ₁₂ is fixed to the first fixed terminal b side. This V _P is V _P = 1/2V _R1 -1/16×1/2V _R1 = 1/2V _R1 -1/3
2V _R1 =1/2V _R1 -1/2LSB, and this voltage is held in the capacitor C' through the voltage follower (voltage comparator 14).

In the fourth step, open analog switch SW ₁₃ and close all other analog switches.
The movable terminals a of SW ₀₁ to _{SW 04} , SW ₁₁ , SW ₁₂ , and SW ₁₄ to _{SW 17} are connected to the first fixed terminal b.

As described above, from the first step to the fourth step,
A reference voltage for voltage comparator 14 is created.

From the fifth step onwards, the comparison is completed by the same operations as in the first embodiment.

Expressing this comparison operation mathematically, (1) (MSB) V _P1 −V _Q = 1/2V _R1 −Vin+1/2V _R1 −(1/2V _R1
- 1/2LSB) = -Vin+(1/2V _R1 +1/2LSB) >0 or <0 ...(6) (2)V _P2 -V _Q =V _P1 -1/2V _R1 + (1/4V _R1 +1/ 2LSB
) ＞0 or <0 …(7) (3)V _P3 −V _Q =V _P1 −1/2V _R1 +(1/8V _R1 +1/2LSB
) >0 or <0...(8) (4)(LSB)V _P4 -V _Q =V _P3 -1/2V _R1 + (1/16V _R1 +1/2LSB) >0 or <0...(9) Comparisons are always made using voltages that have increased by 1/2LSB.

From the above, it is clear that the second embodiment has the quantization error distribution shown in FIG.

In the above-described embodiment, the transfer function is moved at the level of 1/2LSB, but by changing the timing circuit 15, it is also possible to move the transfer function by the offset of the input analog voltage. This will be explained using the transfer function shown in FIG.

In an analog-to-digital converter with a transfer function of a shown in Fig. 9, 3LSB as shown in the figure
If an analog input voltage having an input offset of Next, in this analog-to-digital converter, by shifting the transfer function by the input offset using the method explained in the second embodiment, the transfer function becomes b.
It becomes as shown in . As a result, the full scale is shifted by the input offset, and in the range of analog input voltage Vin-min to Vin-max,
It has the full functionality of a 3-bit analog-to-digital converter.

As detailed above, according to the analog-to-digital converter of the present invention, it is possible to move the average of the transfer function with respect to the analog input voltage, so it is possible to give a degree of freedom to the quantization error distribution with respect to the analog input voltage. , it is possible to eliminate considerations and usage restrictions when using an analog-to-digital converter. Furthermore, since the DA section and the voltage comparator are used for both the operation of creating the reference voltage of the voltage comparator and the comparison operation, this can be realized without increasing the chip size. Moreover, the analog-to-digital converter of the present invention can be realized very easily using conventional technology.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a commonly used n-bit charge redistribution type analog-to-digital converter, Figures 2 and 3 are diagrams for explaining the operation of the analog-to-digital converter, and Figure 4. are diagrams showing the transfer function and quantization error distribution of the analog-to-digital converter, and FIGS. 5 to 7 are diagrams for explaining the first embodiment of the analog-to-digital converter according to the present invention. FIG. 5 is a diagram showing the transfer function and quantization error distribution, FIG. 6 is a circuit diagram, FIG. 7 is a time chart, and FIG. 8 is a diagram showing the transfer function and quantization error distribution of the second embodiment of the present invention. 9 are diagrams showing transfer functions when the second embodiment is provided with an offset function. 11...Unit capacity, 12...Capacity array, 12 ₁ ~
12 ₄ ...Capacity, 13...Selection switch array, 14
…Voltage comparator, SW ₀₁ to _{SW 04} , SW ₁₁ to _{SW 17} … Analog switch, R ₁ , R ₂ … Resistor, C′ … Voltage holding capacitor.

Claims (1)

[Claims] 1. Unit capacity, 1 times, 2 times, 4 times this unit capacity.
A capacitor array consisting of a plurality of capacitors having a weight of 2 ^n-1 times, and one end of each of these capacitors is commonly coupled with one end of the unit capacitor, and an analog input voltage at a predetermined sampling time. or a first selection switch means for selectively outputting the ground voltage; and the other ends of the plurality of capacitors of the capacitor array are individually coupled to connect the other ends of the capacitors to the output of the first selection switch means or a selection switch array comprising a plurality of selection switch means selectively connected to a first reference voltage; and an output of the first selection switch means or a second reference voltage selectively connected to the other end of the unit capacitor; a voltage comparator having first and second signal inputs; and a third selection switch for selectively coupling the signal output of the voltage comparator to the first signal input. switch means; fourth selection switch means for selectively connecting the voltage at one end of the capacitor to a first signal input or a first common coupling of the voltage comparator; A voltage holding capacitor that holds the voltage divided by the capacitor voltage divider circuit composed of the reference voltage No. 2 and the capacitance, and the signal output section of the voltage comparator to the digital signal output section or the second common coupling section. fifth selection switch means for selectively coupling the holding voltage of the voltage holding capacitor to the first common coupling part or the second common coupling part;
a seventh selection switch means for selectively coupling a second signal input of said voltage comparator to said first common coupling or said second reference voltage; and said digital signal output. an analog-to-digital converter comprising: a timing circuit for sequentially operating the selection switch array according to a digital signal of the section; and a timing circuit for selectively operating each of the selection switch means at a predetermined timing. 2. The analog-to-digital converter according to claim 1, wherein the second reference voltage is 1/2 of the first reference voltage.