JPS6361510A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To suppress the error accompanied with analog-digital conversion by quantizing one sampled value of an input analog quantity plural times and obtaining an average value to obtain a digital conversion output. CONSTITUTION:Application of the second sampling pulse is started synchronously with sampling by the first sampling pulse. Consequently, the second semiconductor gate 251 is turned on plural times to charge the second hold capacitor 255 in the holding period of the first hold capacitor 245. That is, one sampled voltage value held in the first hold capacitor 245 is sampled plural times. An arithmetic average in this period is obtained on a basis of plural sampled results of one sampled voltage value in the first sampling circuit part 240 to generate a digital output signal encoded by analog-digital conversion.

Description

[Detailed Description of the Invention] [1 Already Required] An analog-to-digital converter that quantizes one sample value of an input analog quantity multiple times, calculates the average value, and converts it into a digital conversion output signal. By doing so, errors associated with analog-to-digital conversion can be suppressed.

[Industrial application field]

The present invention relates to an analog-to-digital converter, and more particularly to an analog-to-digital converter using a sampling method.

[Conventional technology]

An analog-to-digital converter using such a sampling method has a block configuration as shown in FIG.

Here, the analog signal, which is a sine wave as shown in FIG. 5(A), is sampled by a sample and hold circuit. That is, when sampling is performed according to a certain period, a continuous sampling output signal is obtained that represents a constant analog quantity over a certain period of time, as shown in FIG. 5(B).

In this way, two individual sampling values are converted into digital quantities by the analog-to-digital conversion circuit (A/D converter) at the next stage in accordance with the sampling output signal of the sample-and-hold circuit. In other words, one analog-to-digital conversion is performed for one sampling hold.

[Problem that the invention seeks to solve]

By the way, in the conventional analog-to-digital converter described above, a constant analog quantity is held over a certain period of time by, for example, a capacitor forming a sample and hold circuit, as shown in FIG. 5(B).

However, strictly speaking, the retained analog amount (voltage value) fluctuates as the retention time over a certain period of time passes. The retained analog amount is also affected by external noise.

Therefore, during the operation of converting into a digital code in the analog-to-digital conversion circuit, there is a problem in that an error occurs in the analog-to-digital conversion due to fluctuations in the retained analog amount.

The present invention was created in view of these points, and an object of the present invention is to provide an analog-to-digital converter with fewer conversion errors.

[Means for solving problems]

FIG. 1 is a principle block diagram of an analog-to-digital converter according to the present invention.

In the figure, a sampling means 115 receives a converted signal 111 representing an analog quantity, extracts it based on a predetermined period, and outputs a sampled signal 113 representing a sample value of the analog quantity.

The quantization means 119 receives the sampled signal 113, quantizes each of the sampled values a plurality of times, and outputs a quantized signal 117 representing the result obtained by the quantization.

The averaging means 121 obtains a digital amount of an average value based on a plurality of quantization results for one sample value represented by the quantization signal 117.

Therefore, the overall configuration is such that the result of the average value is used as a digital conversion output signal.

[For production]

One of the analog quantity sample values of the sampling signal 113 obtained from the sampling means 115 is quantized multiple times by the quantization means 119 .

Based on the plurality of quantization results for this one sample value, the averaging means 121 obtains a digital quantity representing the average value.

In the present invention, one sample value of an input analog quantity is quantized multiple times, and the average value is used to obtain a digital conversion output signal, thereby suppressing errors associated with analog-to-digital conversion. be able to.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an analog-to-digital converter according to an embodiment of the present invention.

(2) Connection between JFil and LLE At this point, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The signal to be converted 111 corresponds to an analog signal to be converted that is applied to the input terminal 231.

The sampled signal 113 corresponds to the output signal from the first sampling circuit section 240.

The sampling means 115 corresponds to the first sampling circuit section 240.

The quantized signal 117 corresponds to a digitally encoded signal within the digital encoding circuit section 260.

The quantization means 119 corresponds to the digital encoding circuit section 260 that receives the output signal of the second sampling circuit section 250 and digitally encodes it.

The averaging means 121 corresponds to the digital encoding circuit section 260.

The predetermined period corresponds to the repetition period of the first sampling pulse.

Embodiments of the present invention will be described below assuming that there is a correspondence relationship as described above.

In FIG. 2, an analog signal to be converted (for example,
A sinusoidal voltage signal (as shown in FIG. 5A) is applied to the signal input terminal 231 of the analog-to-digital converter. The analog signal applied to the input terminal 231 is supplied to the input terminal of the first buffer 243 via the first semiconductor switch 241 of the first sampling circuit section 240.

The input terminal of this first buffer 243 is grounded via a first hold capacitor 245.

Further, the gate terminal of the first semiconductor switch 241 is connected to an input terminal 247 to which a first sampling pulse is applied.

The output signal of the first sampling circuit section 240 obtained from the output terminal of the buffer 243 is sent to the input terminal of the second buffer 253 via the second semiconductor gate 251 on the input side of the second sampling circuit section 250 at the next stage. supplied to Similarly, the input terminal of this buffer 253 is connected to the second
It is grounded via a hold capacitor 255. Furthermore, an input terminal 257 that applies another second sampling pulse is connected to the gate terminal of the first semiconductor switch 241.

The output signal of the second sampling circuit section 250 obtained from the output terminal of the buffer 253 is supplied to the input terminal of the digital encoding circuit section 260 at the next stage. Further, in order to perform this conversion operation, a second sampling pulse is applied from the input terminal 257.

FIG. 3 is a waveform diagram showing the operation of the embodiment of the present invention shown in FIG. 2. Reference will now be made to FIGS. 2 and 3.

An analog signal, which is a sinusoidal voltage signal as shown in FIG. 5(A), is applied to the input terminal 231.

When the first sampling pulse applied to the input terminal 247 occurs, the first semiconductor switch 241 is turned on and charges the first hold capacitor 245, and the voltage value of the input analog signal is extracted and applied to the hold capacitor 245. Retained.

Here, since the input impedance of the first buffer 243 is extremely large, the first hold capacitor 245 is not discharged when the first semiconductor switch 241 is off.

In this way, the sampling operation of the input analog signal according to the first sampling pulse is periodically repeated, and the output terminal of the first buffer 243 receives the third sampling pulse.
A sampled voltage is produced as shown in the figure.

The period of the second sampling pulse supplied to the second sampling circuit section 250 is much smaller than that of the first sampling pulse. For example, it is one quarter of the holding period of the first sampling pulse (see the arrow in FIG. 3).

In this way, the second sampling pulse having an extremely high repetition frequency is commonly applied to the second sampling circuit section 250 and the digital encoding circuit section 260.

Now, when sampling is performed using the first sampling pulse, application of the second sampling pulse is started in synchronization with this.

Therefore, over the holding period in the first hold capacitor 245, the second semiconductor gate 251 is turned on multiple times and the second hold capacitor 255 is charged. In other words, one sampling voltage value held in the first hold capacitor 245 is sampled multiple times.

In this way, the second
An analog signal corresponding to the voltage value held in the hold capacitor 255 is supplied from the output side of the second buffer 253 to the next stage digital encoding circuit section 260. Since the second sampling pulse is also commonly applied to this digital encoding circuit section 260, the second semiconductor gate 2
The voltages, which are analog quantities extracted in synchronization with the sampling by 51, are individually converted into digital codes each time. Then, based on the results of sampling multiple times for one sampling voltage value in the first sampling circuit section 240, an arithmetic average of the sampling results is obtained, and a digital output signal coded by analog-to-digital conversion is generated. do.

(2) Summary of the Example In this way, the input analog signal is sampled according to the first sampling pulse, and the second sampling is performed a plurality of times for each sampling voltage. Based on the plurality of sampling results in the second sampling, the digital encoding circuit unit 260 calculates an average value and digitally encodes the average value.

Since the held voltage at the first hold capacitor 245 of the first sampling circuit section 240 is sampled multiple times and averaged, the discharge of the first hold capacitor 245 and the first Errors due to the influence of external noise on the sampling circuit section 240 are eliminated.

Note that in the embodiment of the present invention described above, the operation of the digital encoding circuit section 260 is to digitally encode the held voltages in the second sampling individually and then calculate the average value. However, the individual analog voltages may be averaged and then converted to a digital code.

In addition, in "1. Correspondence between Examples and FIG. 1",
Although the correspondence between FIG. 1 and the present invention has been described, those skilled in the art will easily imagine that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, 1 of the input analog quantity
By quantizing each sample value multiple times and calculating the average value to obtain a digital conversion output, it is possible to suppress errors associated with analog-to-digital conversion, which is extremely practical. Useful.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of an analog-to-digital converter according to the present invention, FIG. 2 is a block diagram of the configuration of an analog-to-digital converter according to an embodiment of the present invention, and FIG. 3 is an implementation of the present invention shown in FIG. A signal waveform diagram for explaining the operation of an example analog-to-digital converter; FIG. 4 is a block diagram showing the configuration of a conventional analog-to-digital converter; FIGS. 5(A) and (B) are shown in FIG. FIG. 2 is a signal waveform diagram showing the operation of the conventional analog-to-digital converter shown in FIG. In the figure, 111 is a signal to be converted, 113 is a sampling signal, 115 is a sampling means, 117 is a quantization signal, 119 is a quantization means, 121 is an averaging means, 231 is a signal input terminal, 240.250 is a sampling Circuit section, 241.251
245 and 255 are hold capacitors, and 260 is a digital coding circuit section. 10,000 yen spit c-1・虱壬10・70 1st figure 5F slot (i number (A) (B) '(L 'i <%i as q force (,'>'6L
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Claims (1)

[Scope of Claims] Sampling means (115) that receives a converted signal (111) representing an analog quantity, extracts it based on a predetermined period, and outputs a sampled signal (113) representing a sample value of the analog quantity. and quantization means (11) that receives the sampled signal (113), quantizes each of the sampled values a plurality of times, and outputs a quantized signal (117) representing the result obtained by the quantization.
9); and averaging means (121) for calculating a digital amount of an average value based on a plurality of quantization results for one said mark represented by a quantized signal (117); An analog-to-digital conversion device characterized in that the result of the average value of 121) is used as a digital conversion output signal.