JPS6360955B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a digital video switcher, in which a plurality of digital MK (MIX KEYING)
By equipping the amplifier with a digital switch and digital delay circuit to delay the signal without deteriorating the characteristics, and by efficiently using a small number of MK amplifiers, an economical switcher with good characteristics can be obtained.

When using analog elements in a video switcher, when connecting multiple MK amplifiers in various configurations, lumped constant delay elements are switched and used to match the video phase, which reduces the deterioration of video signal characteristics. It was becoming a problem. Furthermore, even when using digital elements, preparing all the necessary numbers of multiple MK amplifiers in a system and using only the necessary ones from them has the drawback of being wasteful and expensive.

The present invention is intended to greatly improve the above-mentioned drawbacks, and will be explained below with reference to embodiments shown in the drawings.

FIG. 1 shows the relationship between a digital crosspoint circuit 1 with 11 inputs and 5 outputs and part 2 of the embodiment of the present invention, where 3 is a group of input terminals for PCM color video signals, and 4 is a crosspoint output terminal CP1. , 5
is the cross point output terminal CP2, 6 is the cross point output terminal CP3, 7 is the cross point output terminal CP4, 8 is the cross point output terminal CP5,
9 is an output terminal.

In this case, each PCM color video signal from terminal 3 passes through digital cross point circuit 1.
It is taken out to cross point output terminals 4 to 8 of CP1 to CP5. These five PCM color video signals undergo various effects in portion 2 and are taken out to the output terminal 9 line.

FIG. 2 is a diagram showing an embodiment of the part corresponding to 2 in FIG. 1, that is, a digital video switcher, in which 10 is a multiplexer MPX1 including a delay line, 11 is ADD1, NAM
1, the MK amplifier was configured to additively mix and non-additively mix the signals input to each, and output the signals to one of the selected output terminals, and 12 included a delay line. Multiplexer MPX2, 13 is ADD2,
This is an MK amplifier configured to perform additive mixing and non-additive mixing of the signals input to each NAM2, respectively, and output the signals to one of the selected output terminals.

In this case, multiplexers MPX1 and MPX
2 has a configuration of 5 inputs and 4 outputs, and each output terminal is equipped with a 5 to 1 multiplexer element (for example, TI's TTL-IC) so that any signal out of the 5 input signals can be selected and output. Eight-Input
Multipkxer SN74LS151). The delay line is a digital variable delay line placed before each multiplexer element, and tap-switches a group of shift registers connected in multiple stages and a group of output terminals of this shift register, and adjusts the amount of delay according to the video sample period. It is configured so that it can be varied as a unit (minimum delay amount = 0 is also possible). 14 is the input terminal of video CP1, 1
5 is an input terminal for the video CP2, 16 is an input terminal for the video CP3, 17 is an input terminal for the video CP4, 18 is an input terminal for the video CP5, and 19 is an output terminal for the video line. 20 is mix1 output terminal, 21 is mix
This is the second output terminal. 22 is the CTL1 terminal of the control input of MPX1, 23 is the CTL of the control input of MPX2
It has 2 terminals.

Figure 3 is an example of its functional diagram, and Figure 3 A is additive mixture.
CP using ADD1 and ADD2 and non-additive mixed NAM1
1, CP2, CP4, and CP5 are combined and output. The input of CP4 and CP5 is the delay line DL inside MPX1 and MPX2.
is connected.

Figure B uses ADD2, NAM1 and NAM2.
The circuit configuration that combines and outputs four images of CP3, CP4, CP2, and CP5 is shown, and similarly CP2 and CP5
The input is the delay line inside MPX1 or MPX2.
DL is connected.

As a supplement here, in order to simplify the explanation, it is assumed that the amount of video signal delay occurring in each of ADD1-ADD2-NAM1-NAM2 is equal to the amount of delay at the delay line DL, and ADD
This is necessary to match the phase of the video signal that has passed through the first-class MK amplifier with other video signals. Therefore, for example, in A, ADD from CP4
The delay line DL connected to the multiplexer MPX2 is configured such that the variable delay line in the multiplexer MPX2 is set to the delay amount in ADD1, and the multiplexer element is connected so that the video signal from CP4 is guided to the input terminal of ADD2. It shows that it is working. Similarly, it is shown that the variable delay line in the multiplexer functions so that the delay line from CP5 to NAM1 is equivalent to connecting two delay lines DL.

In this configuration, images of terminals 14 to 18
CP1 to CP5 are CTL1 of terminal 22 and CTL1 of terminal 23.
MPX1 and MPX2 are controlled by CTL2, and ADD1,2,
NAM1,2 has been reorganized, limited ADD1,
ADD2, NAM1, NAM2 are used effectively,
It behaves as if there were three ADD and NAM units. Also, in A, CP1, CP
2 screen becomes the background, and CP4 and CP5 are in the foreground.
The sun is shining. In B, the screens of CP3 and CP4 are in the background, and the screens of CP2 and CP5 are in the foreground.
In this way, according to the above embodiment, the addition mixing circuit
ADD1, ADD2 and non-adding mixed circuit NAM1,
NAM2 can be replaced and reorganized arbitrarily, and by doing so, video signals can be sequentially input to the addition mixing circuits ADD1 and ADD2 and the non-addition mixing circuits NAM1 and NAM2 with almost no restrictions (unlimited re-input). It is possible to develop the screen using new video signals one after another. Therefore, although the digital cross point 1 in FIG. 1 was conventionally replaced during the retrace time under the control of a microprocessor or the like, this is no longer necessary.

In other words, in the conventional system, it is ADD1.
Combine with NAM1 in the first mix section, ADD
The combination of 2 and NAM2 was used as the second mixer, and the video signal was fixed such that the output video from the first mixer was re-inputted to the second mixer. According to the invention, on the contrary, it is possible to realize a system in which the video signal is re-inputted from the second mixer to the first mixer, and from the operator's perspective, the mixer is arranged in multiple stages such as the first, second, third, and so on. This makes it possible to operate as if it were there.

As described above with reference to the embodiments, the present invention eliminates characteristic deterioration caused by lumped constant delay elements for unrestricted re-input of analog video switchers, and
By controlling MPX1 and MPX2 externally, an unlimited re-input function is achieved digitally.
can be used effectively.

[Brief explanation of drawings]

Figure 1 is a diagram showing the relationship between the digital crosspoint circuit and the digital video switcher.
The figure is a system diagram of a digital video switcher according to an embodiment of the present invention, and FIG. 3 is a functional diagram thereof. MPX1, MPX2...Multiplexer,
ADD1, ADD2...Additional mixture, NAM1,
NAM2...Non-additive mixture.

Claims (1)

[Claims] 1 A plurality of multiplexers each having a plurality of input terminals and a plurality of output terminals, and a delay circuit whose delay time is varied by a control signal from a control input terminal is connected between each of these input terminals and output terminals. and a plurality of adding mixing circuits and non-adding mixing circuits that are provided after each of these multiplexers and add or non-add predetermined outputs of the respective multiplexers, mix them, and output the resulting mixture to a predetermined output terminal. and means for supplying the outputs of these mixed keying amplifiers to several predetermined input terminals of the plurality of multiplexers, The video signal input to the input terminal is inputted to one of the mixing keying amplifiers through one of the multiplexers, and the video signals are additively mixed or non-additively mixed, and the additively mixed or non-additively mixed keying amplifier is mixed. The outputs of the keying amplifiers are input to predetermined input terminals of the plurality of multiplexers, and under the control of the multiplexers, the respective video signals input to the plurality of input terminals and the output of the mixed keying amplifier are respectively input to the plurality of multiplexers. The additive mixing circuit and non-additive mixing circuit of the mixed keying amplifier other than the mixed keying amplifier perform additive mixing and non-additive mixing, respectively.
A digital video switcher configured to output.