JPS6360936B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to FM stereo, and more particularly to an apparatus for reproducing FM stereo sound that reduces noise and distortion while maintaining the quality of the reproduced stereo sound.

It is known that when reproducing FM radio transmissions in mono mode, a relatively good quality sound reproduction is obtained with little background noise and relatively low distortion. However, it is also known that FM transmission of stereo signals causes much more noise and distortion.
That is, L-R sound is likely to cause multipath distortion. This occurs because when the FM signal is reflected by the side walls of buildings, hills, or even bridges, a second or third delayed signal reaches the receiver. be. When these delayed signals are superimposed on the main signal transmitted directly to the receiver, distortion occurs in the reproduced mixed signal.

A common way to generate FM stereo is to transmit the L+R signal (which is a combination of left and right stereo signals) as a frequency modulation on a radio frequency carrier, which is demodulated. and signals within the frequency band of 0 to 15KHz. It also contains the L-R signal component (this is the difference between the left stereo signal and the right stereo signal), which is centered on the 38KHz subcarrier and approximately 23KHz.
It is transmitted in a frequency band ranging from 53KHz to 53KHz. These two sets of signals are separated in the receiver and fed to a decoding matrix which mixes these signals and separates them into L and R outputs corresponding to the original left and right stereo signals, and the L and R outputs are Supplied to left and right speakers to generate stereo sound.

Although the L+R signal itself is of good quality, most of the random noise and multipath distortion is due to the L-R signal. Attempts have been made to somehow mask or remove the random noise and distortion in this L-R signal. It is recognized that most unwanted noise and distortion exists within the high frequency range of the L-R signal, and for this reason
One countermeasure was to eliminate the high frequency portion of the -R signal component, especially the portion where the signal strength is low and noise and distortion are noticeable. Such measures are covered by U.S. Patent No.
It is disclosed in No. 3943293. However, by erasing or removing the L-R information in this way, most of the stereo effect is lost, and the L+R signals are transmitted from both speakers, effectively creating a mono-like sound rather than a full stereo sound. I come to do it.

The combined effect of this is that when music is played loud, the sound shifts through the speakers for a stereo effect. However, when the volume of the music starts to decrease, the speaker moves from the speaker position to the center position. Similarly, if a single instrument is played loudly, it will sound like it is coming from the speaker position, but if the same instrument is playing more softly, it will move to a position between the speakers.

Another important point is that many previous approaches have overlooked the importance or role of so-called "ambient" sound in stereo recordings. The quality of a stereo recording is affected by the sound reflected at the recording location and then picked up by the recording microphone. Whether these sounds are directional or not, when added to the main musical sound they create a rich sound that more closely resembles a live performance. These reflected or delayed sounds are the "ambient" sounds mentioned above.

In view of the above points, it is an object of the present invention to maintain the directional information and the richness of the original stereo signal.
FM to minimize random noise and distortion
It is to play stereo sound.

The apparatus of the present invention provides an improved FM stereo output that includes an L+R signal corresponding to the sum of the L and R signals, and an LR signal corresponding to the difference between the L and R signals. The device comprises input means for generating an input signal consisting of an L+R signal component and an LR signal component. The output means also receives and mixes these signal components at a sufficiently high level, and includes a first output component more corresponding to the L signal and a second output component more corresponding to the R signal to provide directional information. or at least convert the L+R signal into an L−
Matrix means are included for receiving the R signal at a sufficiently higher level to generate a second output mode in which both the first and second output components correspond more closely to the L+R component.

further comprising detector means for detecting from said signal first signal portions in which there are more rapid changes in amplitude, and for detecting first signal portions of said first signal portions in said sufficiently high transmitting at a level to generate a first output mode; a second signal portion other than the first signal portion
A control means is also provided for reducing the LR signal component relative to the L+R signal component during the signal portion of the signal to generate a second output mode. Also included is time delay means adapted to receive the L+R signal component and for providing a delayed L+R signal input to the output means, thereby producing a delayed L+R output at the output means.

Preferably, the control means are adapted to reduce primarily the high frequency portion of the L-R signal components during said second signal portion. That is, the control means may include a low-pass filter that transmits the low frequency part of the LR components independently of the detector means. More specifically, the control means includes amplifier means for receiving the L-R signal components and transmitting the L-R signal components to the matrix means. The detector means is responsive to the rapid change in amplitude, and the amplifier means transmits the L-R signal components at a high level in response to the detector means detecting the rapid change in amplitude.

As a further feature, noise control means can be connected to the matrix in parallel with the amplifier means to transmit the L-R signal components to the matrix means. The noise control means includes selectively actuatable switch means for reducing the L-R signal component provided by the noise control means so as to reduce the noise due to the L-R signal component. I'm starting to let them do it.

In one form, the detector means responds primarily to sudden increases in amplitude of the signal. In another configuration, the detector means is responsive to both sudden increases and decreases in amplitude of the signal.

In a preferred form, the time delay means includes a first time delay device for producing a first delayed L+R signal input with a shorter delay and a second delayed L+R signal input with a longer delay. and a second time delay device. The control means is L+R
A time delay control means is also provided for controlling the amplitude of the delayed L+R signal input according to the relative signal strength of the LR signal component with respect to the signal component.

The time delay means is such that one time delay device is L
The time delay input is generated in the high frequency range of the +R signal component and the other time delay device is connected to the L+
The delayed input is generated in the low frequency portion of the R signal component. That is, a first time delay device generates a short time delay input at a high frequency, and a second time delay device generates a long time delay input at a low frequency.

Preferably, filter means are provided for receiving the input from the time delay means and reducing the intermediate frequency portion thereof relative to the low and high frequency portions of the time delay input and providing the modified input to the output means.

A first input value associated with the logarithm of the respective input value in response to first and second input values associated with the L+R signal component and the L−R signal component, respectively, for controlling the amplitude of the delay input. and a comparator including first and second means for generating a second output value. The first and second output values are subtracted from each other by third means, and the first and second output values are subtracted from each other by third means.
A third output value is produced that is related to the true value of the ratio of the input values. Further, fourth means are provided for applying this third output to the time delay control means to increase or decrease the amplitude of the delay input.

In a preferred form, control logic means are provided to selectively cause the output means to be responsive to the control means. The logic means includes signal strength indicator means responsive to a value associated with the input signal to determine a low signal strength condition such that the signal strength is less than a predetermined signal value. Multipath distortion indicating means is also provided for indicating a multipath distortion condition in which the multipath distortion is higher than a predetermined multipath distortion level in response to a variation in a value associated with the input signal. Additionally, logic means is provided for causing the output means to respond to either a low signal strength condition or a multipath distortion condition in response to the signal strength indicator and the multipath distortion indicator.

Preferably, the control logic means also includes a time logic circuit for initiating a predetermined test period during which the signal strength indicating means and the multipath distortion indicating means are activated. Preferably, the logic circuit means also includes muting means for muting the output of the device during the test period. Additionally, the logic circuit means is responsive to the station change instructing means of the device to initiate a test period if the station input to the device changes.

Additionally, in a preferred form, a mutating signal input means is provided for causing the time logic circuit to initiate a test period in response to a muting signal of the device, thereby operating the signal strength indicator and the multipath distortion indicator.

Trigger switch means is provided for initiating a test period in response to initial operation of the control means. The trigger switch means also causes the time logic circuit means, in response to de-energization of the control means, to generate a sound signal for a period of time after the control means is de-energized and before the L and R signals are transmitted directly from the output means. It is also possible to make the output disappear.

In the particular embodiment described below, the detector hand is L-
Capacitor means is provided for receiving a value related to the R signal component and transmitting a difference signal related to the rate of change of the LR signal component. Signal control means is provided for generating a control signal in response to the difference signal. Further, the L-R signal component is transmitted to the output means at a variable output level.
R variable transmission means are also provided. The transmission means is responsive to a control signal and transmits a high or low level L-R signal component depending on the differential output from the capacitor means.

Specifically, the detector means includes rectifying means for receiving the LR signal and generating a rectified LR signal value. Amplifier means are also provided for receiving this rectified value and generating a value related to the LR signal components. Further, means are provided for providing a circuit from the amplifier to the signal control means for transmitting to the signal control means a value related to the absolute value of the L-R signal components.

In another embodiment, a steering diode is inserted between the capacitor means and the L-R signal control means to make the L-R signal control means responsive to both increases and decreases in the amplitude of the differential signal. It's summery.

The method of the invention includes the steps of providing an input signal as described above and then detecting from this signal a first signal portion in which there is a more rapid change in amplitude. receiving and mixing both signal components during a first signal portion, each at a sufficiently high level, to generate a first output mode; and during a second signal portion, generating a second output mode. Contains stages. The more specific features of the method of the invention correspond to the operations performed by the apparatus described above and will therefore not be repeated here.

Other features of the invention will become apparent from the following description based on the accompanying drawings.

To clearly understand the novel features of the present invention, it is first necessary to understand how stereo recording is performed.
It would be prudent to outline some of the phenomena of stereo sound and stereo sound. Therefore, with reference to FIG. 1, a stereo recording method will be briefly described.

A very common method of making stereo recordings is to use two microphones 10 and 12 spaced apart from each other.
It is to prepare. Sound sources (i.e. musical instruments, human voices,
drums, etc.) are placed at various positions in front of the microphones 10 and 12, and in FIG. The sound source 18 includes two microphones 10
and 12, so that sound from the sound source 18 will be received by each microphone 10 and 12 simultaneously and with the same intensity. Therefore, when a signal corresponding to the sound from the sound source 18 is reproduced by the stereo speakers, the same sound will be reproduced from both speakers at the same time. Therefore, the sound from the sound source 18 is substantially monophonic and appears to come from the center of the two speaker positions.

However, if the sound originates from a source that is much closer to one microphone than the other, the sound will be recorded quite differently by each microphone. For example, the sound from the sound source 14 may be heard at an earlier time than the microphone 12.
Then, it reaches the microphone 10 with high intensity. When a recorded signal is played back in stereo by two speakers, first a loud sound is generated from one speaker (corresponding to the sound received by the microphone 10), and after a short time a smaller, similar sound is generated from the other speaker. (This corresponds to the sound received by microphone 12). This type of sound has more of the directional characteristics associated with stereo. The combination of these sounds, some of which appear to come from both speakers and others which appear to be separate sounds from each speaker, creates a combined stereo effect.

In addition, there are sounds called "ambient" sounds mentioned above. These are sounds that reflect off walls or other objects in the recording location and are picked up by the microphone. When these reflected sounds are played through the speakers, they add some echo or reflected sound effect so that they are heard as live music in a room or music hall. These ambient sounds generally contain little directional information of stereo signals. Rather, they are reproduced in the form of general echoes or background sounds that commonly exist in the vicinity of the sound source.

Furthermore, in order to properly appreciate the novel features of the present invention, it is necessary to explain how directional information is detected from sound. As an example, suppose a person hears a sound from a position in front of and to the left of the person. Since the sound source is closer to the person's left ear, the sound source will reach the left ear first and the right ear shortly after. The human auditory system is sensitive to this extremely short delay in the arrival of the same sound to the human ear, and the human brain converts this into directional information about the source of the sound. Note, however, that it is the initial sound wave (ie, the "rising edge" of the sound wave) that provides the directional information.

To further illustrate this, consider a person walking into a room where a constant humming sound is present. When the person opens the door to the room, this sound begins to be heard. Since this is a constant sound and there is no "rising edge", it does not contain directional information. The only way a person can determine the source of a sound is by moving to different locations and detecting differences in the amplitude of the sounds. When the person finally reaches the position where the amplitude is maximum, it can be estimated that the person is closest to the source of the sound.

However, if instead of a constant hum, it is a "beeping" sound that goes on and off, the person can quickly detect the "rising edge" of each beep, and this directional information It can be immediately converted into information representing the sound source.

Sound interruptions also contain directional information.
When a sound ends abruptly, the ear closer to the sound source detects the sound's disappearance sooner than the other ear. This information is converted into directional information in the human brain, helping to identify the location of the sound source.

With this in mind, let's take a look at the common way in which FM stereo signals are transmitted, received, and reproduced as audible sound.
For historical reasons in the development of FM broadcasting (the complexity of which is beyond the scope of this brief introduction), FM stereo signals are generally not transmitted as pure left stereo signals and pure right stereo signals. Rather, a first signal component is included that is an L+R signal component (a combination of left stereo signal and right stereo signal). This signal component is transmitted at a low frequency (ie, below 15 KHz). Also included is a second stereo component, which is the LR component (ie, the component to the left of the left stereo signal and the right stereo signal). This signal component is transmitted at a high frequency (ie, a frequency centered around a frequency of 38 KHz). The two signal components are received, converted to an audio signal, and appropriately mixed in a matrix (or in some cases demodulated directly by synchronous switching phase-locked to a 19KHz synchronization pilot signal). ), L signal (corresponds to left stereo signal) and R signal (corresponds to right stereo signal)
is obtained. This is done by first canceling the R part by mixing the L+R component and the L-R component, and then 2L
This is accomplished by transmitting this to one speaker. Next, L + R component and inverted L
-R component (ie, R-L component) to create a 2R signal and transmit it to the right speaker.

Now, let's examine the type of information contained within the L+R and LR components. The L+R component carries monophonic information, while the LR component carries spatial information. This spatial information can be further classified into two subcomponents. The first is localization information that identifies the sound coming from one speaker or the other speaker. The second, as mentioned above, is ambient information associated with the sound reflected from walls and other objects at the recording location and picked up by the microphone. Generally, L-
Most of the information in the R component (probably about 85%) is redundant ambient information because it also includes the L+R component. In view of this, the approach taken in the apparatus and method of the present invention recognizes this redundancy and uses only the information necessary to reproduce the directional information of the stereo effect from the L-R components. be. Generally L+
Regarding the information in the L-R signal that can be considered redundant for the R component, the present approach refrains from determining this information from the L-R component.
Instead, this information is reconstructed from the L+R components in a relatively noise and distortion free form.

With this in mind, please refer to FIG. 2, which is a block diagram of the main components of the present invention. FM stereo information is L+R component and L-R
These two components shall be transmitted as components.
two components are received by the FM tuner and this
Assume that the FM tuner converts these to audio signals and mixes them in an appropriate matrix to produce L and R signal outputs. These L
and R stereo outputs can be directly transmitted to left and right speakers to play stereo music. If FM stereo stations have fairly strong signals and reasonably low multipath distortion, it is possible to reproduce good quality stereo music from these signals. However, if the signal is weak or significant multipath distortion is present, the L-R components will be reproduced degraded in the reproduced L and R output signals. Therefore, by adding the apparatus shown in FIG. 2 to a common FM stereo receiver, improved L and R output signals can be obtained at the output of the receiver. However, it should also be understood that the present invention may be adapted to utilize initially received L+R and LR signal components.

The input matrix 30 shown in FIG. 2 receives L and R stereo signals obtained from a common FM stereo receiver. This input matrix 30 provides L and R signals through lines 32 and 34 to a logic drive output switching device 38 (described in more detail below). The decision time logic device 36 also checks the control voltage of the tuner (a).
the signal strength is above a certain minimum level, and
(b) Determine that the multipath distortion of the signal is below a predetermined level. If both of these conditions exist, the L and R signals are sent directly to the logic driven output switching device 38 without further processing, and the device 38 sends these signals directly to the left output 40 and The right output 42 is supplied. In other words, since the L and R signals are already of sufficiently good quality, they are simply sent to output terminals 40 and 42 without further processing. However, if the signal is too weak or has too much multipath distortion, the decision time logic device 36
detects this and activates the main operating component of the invention, which will be described below.

The input matrix 30 mixes the two L and R signals to provide an L+R signal at an output terminal 44 and an L+R signal at an output terminal 44.
It also functions to generate the LR component at the output terminal 46 by subtracting the and R component. This L+R component is provided through line 48 to input terminal 52 of output matrix 52.

The L+R signal is also provided to a first delay device 56 via line 54 from terminal 44. Device 56 delays this signal by a relatively short time increment (approximately 11 milliseconds in the particular embodiment shown) and provides the delayed signal to high pass filter 58.
Filter 58 passes only signal components higher than 3 KHz to summing point 59.

The L+R signal from terminal 44 is also applied to low pass filter 60 through line 54. The filter 60 is designed to pass only a portion of the signal lower than 3KHz. The output from filter 60 is sent to a second time delay device 62 which provides a relatively long delay (approximately 26 milliseconds in the particular embodiment shown). The delayed output from device 62 is approximately 480
The signal is supplied to a high-pass filter 64 that passes only signal components of Hz or higher. However, since the delayed output from device 62 is also provided to resistor 65 in parallel with filter 64, the low frequency portion of the delayed LR signal is applied to summing point 59 with a low amplitude. Therefore, the signal provided by high pass filter 64 is delayed by approximately 26 milliseconds and has a delay of approximately 480 milliseconds.
It has a frequency ranging from Hz to 3000Hz. This signal is supplied to summing point 59.

The mixed signal from summing point 59 is applied to an automatic gain control (AGC) amplifier 66. This amplifier 6
The function of 6 is to weaken or strengthen the output from summing point 59 depending on the magnitude of the ratio of the L-R component to the L+R component. Let us pause at this point to state the general purpose of the above components involved in the reproduction of the L and R signals to obtain quality music. Recall that in the previous discussion it was stated that most of the information in the LR channel is redundant for the L+R channel. It has been found that this redundant information can be very advantageously recovered in some respects by using the L+R signal, delaying the signal, and reintroducing this signal into the output matrix 52. However, it is necessary to control the amplitude of the delayed L+R signal so that the delayed L+R signal corresponds to the intensity of the LR component. For this reason, the delayed signal from summing point 59 is provided to AGC amplifier 66.

A comparator circuit 68 is used to control amplifier 66, which produces an output proportional to the ratio of the LR component to the L+R component. To accomplish this, comparator 68 has two inputs, L+R DC converter 70 and L-R
An output from a DC converter 72 is supplied. As the name suggests, converter 70 receives the L+R output component from terminal 44 and converts it to a DC signal that is applied to log/antilog comparator 68 . L
-R DC converter 72 receives the LR signal component from output terminal 46 of matrix 40 and supplies the corresponding DC component to comparator 68. This comparator 68 is (or may be) of conventional design, as will be discussed below. As previously mentioned, the output from comparator 68 determines the strength of the signal provided from summing point 59. If the LR component is relatively strong compared to the L+R component, amplifier 66 amplifies the output from summing point 59 with a higher gain. Comparator 6
The opposite is true if the specific output from 8 is high.

The output from amplifier 66 is provided to a low Q bandstop filter 74 of (or may be) of conventional design. This filter 74 serves to shape the output from amplifier 66 to more closely match the spectral shape of the LR components. That is, the filter 74 attenuates some of the sound in the intermediate frequency band, and the pattern of this attenuation is as shown in FIG.

Let us now proceed to a description of the most important features of the invention. The LR components from output terminal 46 are provided through a low pass filter 76 to a "rising edge detector" 78 and a selectively activated noise control device 79. The filter 76, the detector 78 and the noise low frequency device 79 are connected in parallel with each other.
The outputs of the two components 76 and 78 are applied to a summing point 80. Addition point 80 is low Q band rejection filter 74
It also receives output from

The low-pass filter 76 is configured to pass only the low frequency portion of the LR components (ie, the frequency portion below 450 Hz in this example) at a low level (ie, lowered by approximately 8 dB). It has been found that this low frequency portion of the LR components, which has been reduced in amplitude by about 8 db, contains almost no undesirable noise and is almost completely free of multipath distortion. It is therefore fed to the summing point 80 undisturbed (apart from amplitude reduction).

Rising edge detector 78 responds only to relatively rapid changes in the amplitude of the LR signal (ie, either a sudden increase or decrease in amplitude). When such a sudden change occurs, detector 78 conducts and provides that portion of the L-R signal at a high level to summing point 80. To keep the sound signal stable, detector 78 provides the signal at a sufficiently reduced level.

The output from summing point 80 is output matrix 52
is supplied to the input terminal 82 of. The input to terminal 82 and the L+R component input to terminal 50 are mixed and appear as signals at L and R terminals 40 and 42.

Some components shown in FIG. 2 will be explained in more detail. First, with reference to FIG. 4, the input matrix 30 is
However, since this input matrix 30 has a common design, only an overview will be given.
The left and right stereo signals are applied to unity gain buffers 90 and 92, respectively. The outputs from buffers 90 and 92 are supplied to an operational amplifier 94 through their respective resistors, and the output of amplifier 94 is L+R.
It is a signal component. Further, the outputs from the buffers 90 and 92 are sent to an operational amplifier 96 so as to subtract them from each other.
is also applied to create LR signal components.

FIG. 5 is a detailed circuit diagram of the output matrix 52. Since this is also a common design, it will be briefly explained. The two inputs from terminals 50 and 82 are summed together in amplifier 100 and amplifier 1
The output from 00 is amplified by amplifier 102 and transmitted to L output 103. The inputs from terminals 50 and 82 are also provided to amplifier 104, and the input from terminal 82 is subtracted from the input from terminal 50. The output from amplifier 104 is transmitted to amplifier 106
and appears at the R output terminal 107.

As mentioned above, the input to terminal 50 is a pure L
+R signal component. The input signal to input terminal 82 is from summing point 80, which is similar to summing point 5.
9, the LR low frequency signal from filter 76, the LR output from rising edge detector 78, and the output from noise control device 79. The manner in which the outputs from summing point 80 are mixed within matrix 52 is critical to the operation of the present invention and will be discussed in detail below in connection with the combined operation of the present invention.

The two DC converters 70 and 72 are of common design and will not be discussed further. As previously mentioned, these converters 70 and 72 receive the L+R and LR signals, respectively, and convert the DC signals to DC signals, which are then provided to the comparator 68.

A log/antilog comparator 68 is shown in FIG. The output from the L+R DC converter 70 is applied to an amplifier 108 whose output is equal to the logarithm of the input voltage. Similarly, the DC output from the L-R DC converter 72 is transmitted to the amplifier 110.
, and the output of amplifier 110 is the logarithm of the input voltage. These two logarithmic values are processed by the amplifier 112.
, and the output of amplifier 112 is supplied to anti-log amplifier 114. Amplifier 114 converts the logarithmic input to the antilogarithm value, which is the ratio of the two inputs to amplifiers 108 and 110. Therefore, the output from comparator 68 is a negative value, and its absolute value is equal to L− of the L+R signal component.
This is the ratio to the R signal component.

AGC amplifier 60 is shown in FIG. The output from comparator 68 is applied to input terminal 116;
Amplifier 118 is provided. The output of amplifier 118 is always a negative value. The output from amplifier 118 is applied to one terminal 120 of bridge 122 and to an inverting amplifier 124. The output of amplifier 124 is applied to terminal 126 on the opposite side of bridge 122. The output from summing point 59 is supplied to input terminal 128 and applied to two voltage dividing resistors 130 and 132. The voltage at the junction of resistors 130 and 132 is applied to an amplifier 134. Amplifier 11
As the output from 8 becomes more negative, bridge 122
, the voltage level at the junction of the two resistors 130 and 132 decreases,
The value of the signal applied to amplifier 134 is decreased.
Therefore, if the LR signal is weak, the signal applied to operational amplifier 134 will be weak.

FIG. 8 shows the rising edge detector 78. The LR signal components are applied to an amplifier 142 from an input terminal 140, and the output of the amplifier 142 is further amplified by an amplifier 144. The output of amplifier 144 is provided to diodes 146 and 148. As a result, a DC output is obtained from the diode 146, which is connected in series with a resistor 150,
It is applied to amplifier 156 through 152 and 154. Also, the first capacitor 158 is connected to the resistor 150.
and 152 and ground. The second capacitor 160 is connected to resistors 152 and 15
A third capacitor 162 is connected between the input of amplifier 156 and ground. These three capacitors 1
The effect of 58, 160 and 162 is to continuously attenuate small fluctuations in the signal. These components are arranged to appropriately "smooth" the signal through resistor 150 and to make the signal provided from resistor 152 more "smooth."
The time constant of capacitor 162 is such that the signal provided by resistor 154 is a substantially constant voltage.

Junction point between resistors 152 and 154 and amplifier 15
Two sets of diodes are connected in parallel between the input terminal No. 6 and the No. 6 input terminal. That is, the first diode 164
is adapted to apply a negative signal to amplifier 156 and block the positive signal. 3 diodes 166
The second set is adapted to pass positive signals but block negative signals. Arithmetic amplifier 1
If the negative signal from 44 becomes more negative (i.e., stronger) and the magnitude and rate of change in the signal is large enough, it will overcome the bias of diode 164 and pass the signal to amplifier 156. It becomes possible to apply. When the negative signal from the amplifier 144 approaches positive (that is, the absolute value becomes small), the amplifier 1 overcomes the bias of the three diodes 166.
In order to cause a voltage change at the input of 56, it must be a relatively large amplitude and width change.
That is, this circuit is designed to be more sensitive to an increase in the amplitude of the LR signal component, and to respond rather slowly to a sudden decrease in the amplitude of the LR signal component. As will be explained later, the reason for doing this is that even though a sudden increase in amplitude contains directional information in the same way as a sudden decrease, human auditory senses treat a sudden increase in amplitude as directional information. This is because they are more sensitive than others.

The output from the amplifier 156 is connected to a pair of voltage dividing resistors 1
68 and 170, and the junction of these resistors is connected to an operational amplifier 172, so that the output of amplifier 172 is related to the signal strength. The output of amplifier 156 is also supplied to the input of operational amplifier 172 through capacitor 174 . The function of capacitor 174 is to differentiate the signal output from amplifier 156 so that the rate of voltage change (whether rising or falling) is sufficiently steep. The output of amplifier 172 is provided to the base of transistor 176;
Make it conductive. This transistor 176 operates a current controlled amplifier 178. Amplifier 17
The input of 8 directly receives the L-R signal component from the operational amplifier 96. Therefore, if a stable signal of sufficient amplitude is present, transistor 176
has slight conduction, so amplifier 178 passes the L-R signal at a low level. However, if the rate and magnitude of change in the L-R signal is large enough, transistor 176 receives it through capacitor 174, and amplifier 178 passes the L-R signal component at a much higher level. It becomes like this. The output of amplifier 178 is amplifier 1
80, and its output is applied to the aforementioned summing point 180.
It is supplied to

In the circuit described above, transistor 176 becomes more conductive and amplifiers 178 and 180 provide the L-R signal at a higher level only when the amplitude of the signal increases rapidly. . The human ear is more sensitive to sudden increases in amplitude to discern directional information, but the human hearing sense is also less sensitive to sudden decreases in amplitude to ascertain direction. have. Accordingly, the rising edge detector 78 of FIG. 8 can be slightly modified to respond even to sudden decreases in amplitude, and such modifications are illustrated in FIG. 8A.

For ease of explanation, for components corresponding to some components in FIG. 8, "a" is added to the same number in FIG. 8A to indicate that they are modified components. It shows.

Amplifier 156a of FIG. 8A receives the same output as amplifier 156 of FIG. This output is 2
It passes through two voltage dividing resistors 168a and 170a and a capacitor 174a. In FIG. 8A, a pair of steering diodes D10 and D11 are added to the positive and negative input terminals of amplifier 172a, respectively. Furthermore, a pair of voltage dividing resistors R10 and R
11 is connected to the positive input terminal of amplifier 172a. Diode D11 is connected to the negative input terminal of amplifier 172a through resistor R12,
Furthermore, the emitter of the transistor 176a is connected to the resistor R1.
3 to the negative input terminal of the amplifier 172a.

With this configuration, when a sudden increase or decrease in the amplitude of the signal from amplifier 156a occurs, the output of amplifier 172a goes high, causing transistor 176a to conduct to a greater extent. Thus, with this configuration, the rising edge detector 78 will respond not only to sudden increases in the signal strength of the LR components, but also to sudden decreases in the LR signal strength.

The output from amplifier 180 is provided to summing point 80 through a pair of resistors 181 and 182. Second
A pair of resistors 183 and 184 is connected in series between the input of amplifier 178 and the junction of resistors 181 and 182. Furthermore, a fifth resistor 185
is connected to the junction of two resistors 183 and 184.

Two switching elements 186a and 186b
A first switch 186 is provided having a switch 186, and in the position shown in FIG. 8, switch 186 is open. When the switch 186 is moved to the closed position, the switching element 186a is activated by the decision time logic device 3.
6 to a 12 volt power source.

Two switching elements 187a and 187b
When the second switch 187 with
Connect 6 to a 12 volt power source. Furthermore, the switching element 187b has one end of the resistor 185 grounded,
A part of the LR signal flowing from the resistor 183 to the resistor 184 is leaked.

It is apparent that when both switches 186 and 187 are closed, decision time logic device 36 is connected to the 12 volt power supply. Both switching elements 186b
and 187b are also closed, so that the junction between resistors 183 and 184 is directly grounded through element 186b and element 187b. These resistors 18
1 to 185 and switches 186 and 187 are noise control devices 79.

Therefore, if only switch 186 is closed, time logic device 36 will close resistor 183 and
84 without leaking signals. When switch 187 is closed and switch 186 is opened, decision time logic device 36 is connected to the 12 volt power supply, but resistors 183 and 184
A part of the signal passing through leaks. Finally, when both switches 186 and 187 are closed, in addition to providing voltage to decision time logic circuit 36, the signal across resistor 183 is directly grounded. Since this signal is the L-R signal component received directly from terminal 46 of input matrix 30, if this signal is extremely noisy, both switches 186 and 187
This noise can be largely eliminated by pushing (tilting) the switch to the closed position. On the other hand, if the noise is not too bothersome, it can be reduced to some extent by closing switch 187 and leaving switch 186 open. Furthermore, if the noise is not significant, switch 186 can be closed and switch 187 can be opened, thereby eliminating leakage of the signal passing in parallel with rising edge detector 78. However, it should be noted that even if this signal does not leak, the L-R signal bypassing amplifiers 178 and 180 is relatively weak and essentially generates little noise. .

FIG. 9 is a circuit diagram of the logic drive output switching circuit 38. Switching input terminal 190 receives a signal from decision time logic device 36. The circuit 38 has an L input terminal 192 and an R input terminal 194.
It also has These are the output matrix 12
is connected to output terminals 103 and 107 of.
It also has a second L input terminal 196 and a second R input terminal 198, which are connected to output lines 32 and 34 of input matrix 30. The aforementioned L and R output terminals are designated 40 and 42, respectively.

The operation of the switching device 38 will be explained.
Logic input 190 is connected to the base of transistor Q1. The emitter of transistor Q1 is connected to a +12 volt voltage source, and the collector is connected through a resistor to a -12 volt voltage source. The collector of transistor Q1 is connected to the second transistor Q2
It is also connected to the base of. Transistor Q2
The emitter of is connected to a -12 volt voltage source and the collector to a +12 volt voltage source.

The collector of transistor Q1 is connected to the gates of two field effect transistors Q3 and Q4, and the collector of transistor Q2 is connected to the gates of third and fourth field effect transistors Q5 and Q6, respectively.

+12 volt signal to switching input terminal 190
when applied to the two transistors Q1 and Q
2 is cut off, so the field effect transistor Q3
-12 volts is supplied to the gates of Q4 and Q4, making them non-conductive. Meanwhile, a +12 volt input is applied to the gates of field effect transistors Q5 and Q6, causing them to conduct. Therefore, in this condition, the signal is transferred from input matrix 30 to line 32.
and 34 directly to outputs 40 and 42.

However, when the base of transistor Q1 goes to 0 volts, both transistors Q1 and Q2 become conductive, resulting in field effect transistors Q5 and Q6.
-12 volts will be applied to the gate of field effect transistors Q3 and Q4, while a voltage very close to +12 volts will be applied to the gates of field effect transistors Q3 and Q4.
This causes transistors Q3 and Q4 to conduct, so that the signals provided to outputs 40 and 42 are transferred to input terminal 1, which is connected to output matrix 52.
92 and 194.

Now, FIG. 10 is a block diagram showing the main functions of decision time logic device 36. The operation of this device 36 will first be described in outline with reference to FIG. 10, and then in detail with reference to FIG.

As mentioned above, the functions of the logical device 36 are as follows:
The purpose is to examine the composite FM stereo signal to determine whether it is of sufficient quality to be provided to the output terminals 40 and 42.
If the signals are found to be sufficiently strong and relatively free of distortion, the L and R signals are provided directly from the input matrix 30 to the outputs 40 and 42 of the logic driven output switching device 38. On the other hand, as a result of the logic circuit 36 inspecting the FM stereo signal,
Upon determining that the signal is insufficient to be provided directly, device 38 operates to pass the signal through the various components of the present invention and finally to output matrix 52. The outputs of output matrix 52 then pass through switching device 38 to output terminals 40 and 42.

As shown in FIG. 10, switch 200 is connected to a 12 volt voltage source. This switch 20
0 is actually combined with either switch 186 or 187, but is shown as a separate switch for convenience of explanation. Alternatively, the switch 200 may be a separate switch and may be linked so that when either the switch 186 or 187 is closed, this switch is also closed. Closing this switch 200 puts logic device 36 into operation. Switch 200 performs the mundane function of powering the various components of device 200, but also provides a 12 volt pulse to trigger device 202, and 12
Muting signal input 20 by volt input
It also works to enable 4.

Upon receiving the 12 volt input, trigger device 202 immediately triggers time logic circuit 20 for approximately 1.5 seconds.
Activate 6. At the same time, trigger device 202 provides a signal to D flip-flop 208 to enable it.

Timing logic circuit 206 generates a "window" of approximately 1.5 seconds for activating multipath distortion level indicator 210 and signal strength indicator 212. The composite signal is passed through line 213 to two indicators 21
0 and 212. If either indicator 210 or 212 determines that the composite signal is of sufficiently poor quality, indicator 210 or 212 sends a signal to the input of gate 214. In this state,
The clock input applied to gate 214 is passed to the clock terminal of D flip-flop 208;
D flip-flop 208 provides enable signals to two binary dividers that serve as time delay drive devices 216 and 218. Two time delay drive devices 216 and 218 power the two time delay devices 56 and 62 (FIG. 2) previously described.

The output from D flip-flop 208 is also connected to switching input terminal 190 of logic drive output switching device 38 through line 220.
sent to.

In addition to activating the two indicators 210 and 212, the time logic circuit 206 provides a muting signal to the main tuner via line 222 to
During the second inspection period, Chiyuna's muting circuit is activated to mute the sound. Since the muting circuit of a common tuner is well known, its explanation will be omitted. In summary, the muting circuit is activated during changing from one station to another so that random noise is not generated during changing stations.

Additionally, a line 224 connected to the tuner's existing muting circuitry provides input to the muting signal input 204. When this muting signal input 204 is activated, it activates the time logic circuit 206 to operate for a 1.5 second test period and output L and R signals to the output matrix 52.
Let them decide whether to proceed. As described above, when the decision time logic device 36 is activated,
Each time a station change occurs, time logic circuit 206 is activated for 1.5 seconds to examine the quality of the signal from the new station to determine whether the processing components of the present invention should be activated.

Also provided are two oscillators 226 and 228. Oscillator 226 is time delay driving device 2
16 and the input of gate 214 to activate these components. Oscillator 228 provides a pulsating input to time delay drive device 218 to activate it.

Before describing the details of logic circuit 36 with reference to FIG. 11, it may be helpful to explain the operation of the components described in FIG. 10. It is assumed that the main FM tuner combined with the present invention is powered on and is generating a stereo signal, and that the switch 200 is
Let's assume that it is open. In this condition, the left and right stereo signals from the tuner pass through matrix 30 and appear on lines 32 and 34, which are then fed directly to outputs 40 and 42. Assume that the listener closes switch 200 in the hope of improving the signal. The direct effect is that trigger device 202 activates time logic circuit 206 for a test period of 1.5 seconds. During this 1.5 second test period, multipath distortion level indicator 210 observes amplitude changes in the composite signal and detects sufficient distortion to warrant processing the L and R signals through the various components of the present invention. determine whether it exists. At the same time, signal strength indicator 212 examines the signal strength to determine if it is low enough to warrant processing the L and R signals. (If the signal is fairly weak, we can assume that there is enough random noise in the amplified signal, so that the output is of such quality that processing the signal through the various components of the present invention is not good.) At least 1
Assume that one indicator 210 or 212 determines that the signal is defective enough to warrant processing. Then, one or the other indicator 210 or 212 sends an activation signal to the input of gate 214 (gate 2
14) has already received a pulse from the oscillator 226), the gate 214 is connected to the D flip-flop 208.
(D flip-flop 208
has already been activated by trigger device 202). D flip-flop 208 provides enable signals to two time delay drive devices 216 and 218 to enable two time delay circuits 56 and 62. Additionally, D flip-flop 208 is connected to input 19 of logic driven output switching device 38.
0, the output from output matrix 52 is output through device 38 to output terminals 40 and 42, and the outputs on lines 32 and 34 are interrupted.

During the 1.5 second decision period, time logic circuit 206 sends a signal through line 222 to activate the tuner's muting circuit. This 1.5 second delay occurs before the sound is generated, regardless of whether indicators 210 and 212 respond immediately or do not respond at all during the beginning of the 1.5 second decision period or during the latter part of this period. Note that this is accompanied by a delay.

On the other hand, assume that switch 200 is closed, energizing time logic circuit 206, but that the stereo signal from the tuner is of sufficiently good quality. Under these conditions, the time logic circuit 206 still
sends a muting signal to Chiyuna, causing it to shut off the sound for a determined period of 1.5 seconds. However, since neither indicator 210 or 212 sends an activation signal, at the end of the 1.5 second decision period the L and R signals are routed from input matrix 30 through lines 32 and 34 to output terminals 40 and 42. Output.

Now, let us assume that the listener decides to change the station using the FM tuner while closing the switch 200 first. This will cause the mutating circuit in the tuner to generate a muting signal, which is sent through line 224 to the mutating signal input 204, which in turn sends a signal to the time logic circuit 206 so that the new station is Then another 1.5 second test period will begin. Note that the output from muting signal input 204 occurs in response to termination of the muting signal on line 224. That is, when a new station is found, the muting circuit in the tuner stops operating. Indicators 210 and 212 then examine the signal from the new station for a total period of 1.5 seconds and determine whether the signal should be processed.

Assume that a listener decides to open switch 200 and listen to music produced by unprocessed L and R stereo signals. In this case, the trigger device 202 is configured to activate the time logic circuit 206 for 1.5 seconds when the switch 200 is opened, thereby activating the tuner's muting circuit for the 1.5 seconds. This 1.5 second delay provides a temporal separation in the sound generation between the processed and unprocessed signals.

FIG. 11 shows details of decision time logic device 36. Switch 200 is line 230
is connected to the base of transistor Q10 via. The collector of transistor Q10 is connected to a +12 volt source. Line 230 bypasses transistor Q10 and connects via line 232 to 12
It is also adapted to provide volt pulses to an inverter 234. This forces the output 236 of inverter 234 to zero. This zero voltage is applied to the input terminal 238 of NAND gate 240 through resistor R2 and capacitor C1. NAND gate 24
The other input terminal of 0 is shown at 242. this
NAND gate 240 has an output 244 of zero when 12 volts is applied to both input terminals 238 and 242.
descend to while two input terminals 238 and 24
0 voltage drops to 0, the output 244 will be
Jump to 12 volts. In this case, the inverter 23
Since output 236 of 4 suddenly drops to 0, the drop of output terminal 238 to 0 causes output 244 to rise suddenly to the 12 volt level. This 12 volts is returned to the input of inverter 234 through resistor R1 to maintain output 236 at zero voltage. Note, however, that input terminal 238 is connected to the +12 volt voltage source through two voltage dividing resistors R2 and R3, and capacitor C1 is connected to the junction of resistors R2 and R3. The time constant of capacitor C1 is 1.5 seconds after NAND gate 24
0 output 244 is made low, and the inverter 23
4's output 236 towards the 12 volt level sufficiently to raise it to the 12 volt level.

Referring to the block diagram of FIG. 10, components 234-244, resistors R1-R3, and capacitor C1 form time logic circuit 206, providing a 1.5 second test window. Transistor Q10 and line 2
32 is a part of the trigger device 202.

Output 236 of inverter 234 provides a signal to multipath distortion level indicator 210, and the signal on line 222 activates a muting circuit within the FM tuner. An output 244 of NAND gate 240 provides an enable signal to signal strength indicator 212 .

Now, the signal strength indicator 212 includes an operational amplifier 250 that functions as a comparator.
One input terminal of is connected to the composite signal source from the tuner through line 213, and the other terminal is connected to the output 24 of NAND gate 240 through resistor R4.
4 and is also grounded through another resistor R5. When output 244 goes positive, it is connected to amplifier 250 through two voltage dividing resistors R4 and R5.
is supplied as a reference voltage. If the signal strength is relatively large, the output of NAND gate 254 will be zero. However, when the operational amplifier 250 acting as a comparator detects a weak signal,
This will result in an extremely low signal being output.
The output of NAND gate 254 goes high and a 12 volt signal is sent to one terminal 2 of NAND gate 214.
56. NAND gate 2
The other input terminal 260 of 14 is connected to the output of oscillator 226 (i.e., oscillator 226 is connected to terminal 2
60 with a 12 volt positive pulse applied).

The above operational amplifier 250, resistors R4 and R5,
and the NAND gate 254 is the signal strength indicator 21
It is part of 2. Oscillator 226 is of common design and will not be described in detail.

Next, the multipath distortion level indicator 210 will be explained. One terminal of operational amplifier 262 is connected through capacitor C2 and line 213 to the composite signal source. This operational amplifier 262 responds to small ripples in the composite signal, such as those due to multipath distortion. The output of amplifier 262 is applied to one terminal of operational amplifier 264, which acts as a comparator. The other terminal of comparator 264 is connected to the +12 volt power supply through resistor R6;
It is also connected to the output 236 of the inverter 234 through a variable resistor R7. When output 236 goes to 0, the two resistors R6 and R7 act as voltage divider resistors and provide a reference voltage level to comparator 264. When the output from amplifier 262 reaches a sufficiently high level, comparator 264
A signal is provided to an input terminal 256 of NAND gate 214.

From the above description, it should be clear that NAND gate 214 produces a pulsating output in response to either of its two inputs. One of these inputs is due to low signal strength and is provided by indicator 212 (consisting of comparator 250 and NAND gate 254). The other input is from multipath distortion level indicator 210 (comprised of amplifier 262 and comparator 264). As previously mentioned, oscillator 226 provides a constant pulsating voltage to terminal 260 of NAND gate 214 as soon as switch 200 is closed. NAND gate 214, when activated by either indicator 210 or 212, provides a positive pulse to clocking input 266 of D flip-flop 208.

An input terminal 268 of D flip-flop 208 is connected to the collector of transistor Q10. When switch 200 is opened, set input 2
The voltage at 68 will be 12 volts and the Q output terminal of D flip-flop 208 will remain at 12 volts. this
Time delay device 216 even when 12 volts are output
Alternatively, since the signal 218 is not activated and the switching input of the logic drive output switching device 38 is not activated, it is as if no signal is applied. However, when switch 200 is closed and transistor Q10 is activated, its collector voltage drops to almost zero and the set input 26
8 to almost zero voltage. When a positive pulse is applied to clock input 266, the Q output terminal drops to the same voltage as the D terminal, ie, zero voltage. This allows D flip-flops 274 and 27
6 set inputs 270 and 272 will now have a zero voltage level applied to them.

D flip-flops 274 and 276 are time delay drive devices 216 and 218, respectively. The pulse input to D flip-flop 274 is provided by oscillator 226. The two output lines 278 and 280 of the D flip-flop 274
provides the drive signal for the first time delay circuit 56. The pulse input to D flip-flop 276 is provided by an oscillator 228 of conventional design. The two output lines 282 and 284 of the D flip-flop 276 are connected to the second time delay device 6.
A drive signal is supplied to 2.

The Q output of D flip-flop 208 is also provided to input terminal 190 of logic drive output switching device 38 through line 220. As discussed with respect to this device 38, when the voltage on line 220 is 12 volts, the L and R outputs 40 and 42 are derived directly from the L and R inputs from matrix 30. However, line 22
When the zero voltage drops to zero, this acts on switching device 38 to cause output to be taken from output matrix 52.

The muting signal input device 204 is
It includes a NAND gate 290 having a first input terminal 292 and a second input terminal 294. Terminal 292 is switch 2
It is connected directly to 00 and receives a constant 12 volts. Another input terminal 294 is adapted to receive output from a muting circuit in the FM stereo tuner through line 224. Output terminal 296 of NAND gate 290
is connected to the input of inverter 298. The output 300 of the inverter 298 is the time logic circuit 20
6 NAND gate 240.

When the two terminals 292 and 294 of NAND gate 292 are at +12 volts, output 296 will be zero. At this time, the output of inverter 298 is 300
is +12 volts because resistor R8 is grounded. This causes NAND gate 240 to operate as described above. The switch 200 closes,
Capacitor C1 is fully charged to 12 volts,
Therefore, assume that the input terminal 238 is also 12 volts. It is assumed that the muting circuit is sending a 12 volt signal to terminal 294 as a result of operating the FM tuner to change stations. In this case, since both terminals 292 and 294 are at +12 volts, there is no effect on inverter 298. However, when the tuner moves to a new station and the muting circuit stops operating, the voltage at terminal 294 becomes 0, so the output 29 of NAND gate 290
6 becomes 12 volts, so inverter 298
The output 300 of becomes 0, and the NAND gate 240
The output 244 of will be a positive 12 volts. As a result, the output 236 of the inverter 234 becomes 0, and the time logic circuit 206 becomes activated. In this manner, the aforementioned process of signal strength indicator 212 and multipath distortion level indicator 210 is initiated to determine the strength and distortion of a new signal.

To further explain the operation of mutating signal input device 204, assume that power to the entire FM tuner is cut off and switch 200 is closed. When the power is turned on to the FM tuner,
The muting circuit will automatically operate for approximately 0.5 seconds. At the end of this 0.5 second, the voltage at terminal 294 drops to 0, causing the output 296 of NAND gate 290 to drop to 12
Since it is pulled up to the bolt, the inverter 298 and
Time logic circuit 20 through NAND gate 240
6, a 1.5 second FM stereo signal test period will begin.

Finally, assume that the main FM tuner is operating and switch 200 is closed. Assume now that the listener wishes to bypass the processed components of the present invention and listen to the original L and R stereo signals. As soon as switch 200 is opened, transistor Q10 becomes nonconductive, so that the collector voltage of transistor Q10 rises to 12 volts.
This becomes a 12 volt pulse and connects to the inverter 23.
4 and is transmitted to the time logic circuit 2 as described above.
Activate 06. This effect is simply about 1.5
Only a seconds mutating signal is provided on line 222. Therefore, there is a 1.5 second delay before the FM stereo tuner produces any sound. This temporal separation of processed and unprocessed signals is desirable to avoid any sharp transients.

This concludes the detailed explanation of the apparatus of the present invention, and the integrated operation of the present invention will be explained again based on FIG. As mentioned above, the apparatus of the invention (as shown in the embodiment) receives stereo signals and converts them into
It is used in conjunction with a common FM tuner, which is adapted to convert left and right audio output signals that can be used directly to generate FM stereo music. However, as pointed out earlier, these left and right stereo signals are transmitted L+R and L-R
Since they are reconstructed from signal components, the reconstructed left and right output signals (i.e. L and R signals)
contains defects due to multipath distortion and unwanted noise due to the LR components.

The left and right inputs are passed directly to lines 32 and 34, which connect these signals to input terminals 196 of logic driven output switching device 38.
and 198. At the same time, input matrix 30 provides the L+R signal component on line 44 and the L-R signal component on line 46. The circuit processing component of the present invention is the switch 20 of the logic device 36.
Operation is entered by closing 0. As previously discussed, this causes logic device 36 to examine the composite signal to determine if there is sufficient signal strength and if multipath distortion is sufficiently low. If both of these conditions exist, logic device 36 has no further effect and continues to apply a +12 volt signal to input 190 of logic drive output switching device 38. This causes the L and R input signals to output 40
and 42 directly.

However, if the composite signal is determined to be inferior, logic device 36 provides a 0 volt signal to terminal 190 of switching device 38 such that output terminals 40 and 42 connect to input terminals 196 and 198.
These output terminals are instead connected to output terminals 103 and 107 of output matrix 52. Decision time logic device 36 also activates two time delay drive devices 216 and 218 (which are D flip-flops 274 and 276) to power two time delay devices 56 and 62.

As discussed in the general description of the invention with reference to the block diagram of FIG. 2, the L+R signal is passed through line 54, time delay device 56 and high pass filter 58. This results in L+R components in the frequency range above about 3 KHz delayed by about 11 milliseconds. The output from high pass filter 58 is provided to summing point 59. The L+R signal also passes through a low pass filter 60, a time delay device 62, and a high pass filter 64. This results in a delay of approximately 26ms from approximately 480Hz to 3K.
Hz frequency range (including some output below 480Hz)
is obtained. This output is also supplied to summing point 59.

As previously mentioned, the output from summing point 59 is the ratio L
When -R/L+R is small, the amplitude is controlled by lowering the gain of the automatic gain control amplifier 66. On the other hand, when the ratio LR/L+R is large, the gain of the amplifier 66 becomes correspondingly high. The output of amplifier 66 is applied to summing point 80 through filter 74.

Since the L-R signal components obtained from the output terminal 46 of the matrix 30 are passed through the filter 76,
Summing point 80 is supplied with an input containing L-R information below 450 Hz. The LR signal also passes through a rising edge detector 78. As can be readily seen from the detailed description of rising edge detector 78 above, if there is no sudden change in amplitude of sufficient magnitude in the L-R signal component, detector 78 detects the L-R signal at a low level. Transmit. Therefore, the LR signal components are low level, mainly in the range below 450 Hz. The L-R signal components in the low frequency range introduce little random noise and multipath distortion, and at low levels the summing point 80
Therefore, the output of the filter 76 does not cause deterioration of the target signal.

The LR signal is also provided at a low level through device 79 to summing point 80. However, if L
If the noise in the -R component is excessive, this signal can be leaked out by selectively closing switches 186 and 187.

If there is a fairly rapid change in the amplitude of the LR signal components, the rising edge detector 78 will conduct more during this change. In the configuration shown in FIG. 8, the detector 78 is sensitive only to sudden increases in amplitude. In the variation shown in FIG. 8A, detector 78 responds to both rapid increases and decreases and transmits the L-R signal at a high level to summing point 80 during these rapid increases or decreases.

With this in mind, let's examine how the various inputs are mixed in matrix 52 to produce an output. Consider FM stereo music being played and short increments of music where there is no abrupt beginning or end of sound that could be considered the same. Further assume that the signal is weak enough or contains enough multipath distortion for the signal processing component of the present invention to operate. In this case, two delayed L+R signals appear at summing point 80, the LR signal containing frequencies below 450 Hz is also fed to summing point 80 at a lower level, and the high frequency portion of the LR component is widened. will be supplied at a lower level. This mixed signal is provided from a summing point 80 to an input terminal 82, added to the L+R signal and output at output 40, and subtracted from the L+R signal as it appears at output 42.

In this state, considering frequencies below 450Hz, the L signal component is output from the output 40, and the R signal component is output from the output 40.
The signal component is output from the output 42,
There will be some crossover due to the low level low frequency LR. At frequencies above 450Hz, extremely small LR components are added, so
Or 450Hz since the L-R components are not added at all.
The above L and R signals are L output 40 and R output 42
is output from. However, in this case, there is little directional information in the sound, so the stereo effect is hardly lost. Furthermore, since the output from summing point 59 provides L+R with a redundant delayed sound ambient component, the integrity of the musical stereo sound is not compromised.

As another case, consider the case of a music signal in which a distinct musical sound is initiated such that the rising edge detector 78 detects a "rising edge". In this case, the entire L-R signal is applied to summing point 80. This is fed to matrix 52 so that output 40 is a purer L signal and output 42 is a purer R signal. In this case, since the music contains directional information, the person will psychologically identify the newly induced sound as coming from one or the other speaker. Immediately after the person has psychologically localized the location of the sound, the rising edge detector 78, which has just detected that a sudden change in amplitude has passed, greatly reduces the L-R signals above 450 Hz. However, the mind of a person who hears the onset of stereo sound still retains the directional impression, and the stereo effect does not seem to have diminished. On the other hand, the detrimental effect of undesirable noise in the high frequencies in a sustained L-R sound is that the period during which the rising edge detector 78 transmits the entire L-R signal strength is very short and the noise during this short period is Since it is not noticeable, it is effectively reduced.

Although the above explanation is rather general and can be considered to be a reasonably correct explanation of the musical phenomena that occur, it should be understood that there are other effects that have not been mentioned in this explanation. However, regardless of the completeness or accuracy of the foregoing description, the present invention effectively reproduces the integrity of stereo sound and the directional information of stereo sound, and substantially eliminates undesirable random noise and multipath distortion. We have confirmed that it has been completely removed. It will also be readily understood that the apparatus of the present invention may be modified in various ways without departing from its basic teachings.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram illustrating a typical method for stereo recording, FIG. 2 is a block diagram illustrating the main operating components of the present invention, and FIG. 3 is a diagram illustrating the main operating components of the present invention. Fig. 4 is a graph showing the spectral shape of the filter, Fig. 4 is a circuit diagram of the input matrix, Fig. 5 is a circuit diagram of the output matrix, Fig. 6 is a circuit diagram of the comparator, and Fig. 7 is an automatic 8 is a circuit diagram of a gain control amplifier; FIG. 8 is a circuit diagram of a rising edge detector and noise control device; FIG. 8A is a circuit diagram of a partial variation of a rising edge detector; 9
10 is a circuit diagram of the logic drive output switching device, FIG. 10 is a block diagram of the decision time logic device, and FIGS. 11A and 11B are circuit diagrams of the decision time logic device of FIG.
1 set), and FIG. 11C shows the 11th
FIG. 11 is a diagram showing a method of combining FIG. A and FIG. 11B; 10,12...Microphone, 14,16,1
8, 20, 22... sound source, 30... input matrix, 36... decision time logic device, 38...
Logic driven output switching device, 40...left output, 42...right output, 52...output matrix, 56...first delay device, 58, 64...
...High pass filter, 59, 80... Addition point, 6
0,76...Low pass filter, 62...Second delay device, 65,130,132,150,
152, 154, 168, 170, 181, 18
2,183,184,185,R1,R2,R
3, R4, R5, R6, R7, R8, R9, R1
0, R11, R12...Resistor, 66...AGC amplifier, 68...Comparator, 70...L+R DC converter, 72...L-R DC converter,
74...Low-Q bandstop filter, 78...Rising edge detector, 79...Noise control device, 90,9
2...Batsuhua, 94,96,100,102,
104, 106, 108, 110, 112, 11
4,118,124,134,142,144,
156, 172, 178, 180, 250, 26
2,264... (operation) amplifier, 122... bridge, 146,148, D10, D11... diode, 158, 160, 162, 164, 16
6,174, C1, C2...Capacitor, 17
6, Q1, Q2, Q10...transistor, Q
3, Q4, Q5, Q6...Field effect transistor, 186,187,200...Switch, 20
2... Trigger device, 204... Muting signal input, 206... Time logic circuit, 208,
274, 276...D flip-flop, 210
...Multipath distortion level indicator, 212... Signal strength indicator, 214... Gate, 216, 218
...Time delay drive device, 226, 228...
Oscillator, 234, 298...Inverter, 24
0,254,290...NAND gate.

Claims (1)

[Claims] 1. L+R signal component corresponding to the sum of the L signal and R signal and L−R corresponding to the difference between the L signal and R signal
An apparatus for generating an improved FM stereo output in which signal components are present, the apparatus comprising: (a) means for supplying an input signal consisting of the L+R signal component and the L-R signal component; (b) (i) the input signal; (ii) detecting means responsive to said control signal to detect a first signal portion that includes more rapid changes in amplitude and generates a control signal representing this signal portion; When the control signal indicates that the L-R signal contains a large amount, the L-R signal to be transmitted is strengthened;
receiving the L-R signal component from the input signal and weakening the transmitted L-R signal when the control signal indicates a second signal portion containing fewer abrupt changes in amplitude; R
L-R transmitting means for transmitting signal components; (c)(i) receiving the L+R signal component and the L-R signal component from the L-R transmitting means, and transmitting these L+R signal components; a first output section that generates a first output adding the L-R signal component; (ii) receiving the L+R signal component and the L-R signal component from the L-R transmitting means;
a second output section that generates a second output obtained by subtracting the LR signal component from the +R signal component; When the L-R signal component is strengthened, the first output becomes mainly an L output signal and the second output becomes mainly an R signal output. and each of the second outputs is primarily both an L signal component and an R signal component. 2. Apparatus according to claim 1, characterized in that the control signal is adapted to attenuate primarily the high frequency part of the L-R signal components during the second signal portion. 3. said control means independently of the detector means;
3. The apparatus according to claim 2, further comprising a low-pass filter for transmitting the low frequency part of the L-R components to the matrix means. 4. said control means also comprises amplifier means for receiving the L-R signal component and transmitting said L-R signal component to the matrix means; said detector means responsive to sudden changes in amplitude and detecting Claim 3, wherein the amplifier means is adapted to transmit the L-R signal components at a higher level in response to detection of this rapid change in amplitude of the amplifier means. Device. 5. Also comprising noise control means connected to the matrix means in parallel with the amplifier means for transmitting the L-R signal components to the matrix means, the noise control means reducing noise due to the L-R signal components. L-R supplied from the noise control means so as to
5. Apparatus according to claim 4, further comprising selectively actuatable switch means for attenuating signal components. 6. Claim characterized in that said detector means are adapted to transmit L-R signal components of a first signal portion at a sufficiently high level primarily in response to an increase in the amplitude of said signal. The device according to scope 4. 7. said detector means is adapted to transmit the L-R signal components of the first signal portion at a sufficiently high level in response to both rapid increases and decreases in amplitude of said signal; A device according to claim 4, characterized in: 8. The invention further comprises a time delay means configured to receive the L+R signal component and supply the delayed L+R signal input to the output means, thereby causing the output means to generate a delayed L+R output. Apparatus according to scope 1. 9. The time delay means includes a first time delay device providing a first delayed L+R signal input with a short delay and a second delay L+ with a long delay.
and a second time delay device providing an R signal input.
The device described in. 10 The control means delays L+ according to the relative signal strength of the L−R signal component with respect to the L+R signal component.
Claim 9, further comprising time delay control means for controlling the amplitude of the R signal input.
The device described in. 11. Claim 8, further comprising time delay control means for controlling the amplitude of the delayed L+R signal input according to the relative signal strength of the L-R signal component with respect to the L+R signal component. equipment. 12. Also comprising filter means for receiving the delayed input from the time delay means, attenuating the intermediate frequency portion of the delayed input with respect to the low and high frequency portions, and supplying the modified input to the output means. 12. The device according to claim 11, characterized in that: 13. Control logic means for selectively causing the output means to respond to the control means, the control logic means being configured to: (a) respond to a value associated with an input signal so that the signal strength is less than a predetermined signal value; (b) signal strength indicator means for determining a low signal strength condition such that the multipath distortion is greater than a predetermined multipath distortion level in response to variations in value relative to the input signal; multipath distortion indicator means for indicating a state of distortion; and (c) responsive to the signal strength indicator means and the multipath distortion indicator means to indicate that the signal strength is below a predetermined signal strength level or that multipath distortion is present. Logic output means for causing the output means to respond to the control means if the multipath distortion level is higher than a predetermined multipath distortion level.
1. The device according to 1. 14. said control logic means; for initiating a predetermined test period, activating signal strength indicator means and multipath distortion indicator means during said test period, and activating said logic output means during said test period; 14. Apparatus according to claim 13, further comprising time logic circuit means for . 15. The apparatus of claim 14, wherein said time logic circuit means includes muting means for muting the sound output of said apparatus during testing. 16 said time logic circuit means initiates a test period and activates a signal strength indicator means and a multipath distortion indicator means when a station input to said apparatus changes in response to a station change instruction means of said apparatus; 16. A device according to claim 15, characterized in that the device is adapted to cause 17 The detection means includes (a) capacitor means for receiving a value associated with the L-R signal component and transmitting a differential signal associated with the rate of change of the L-R signal component; (b) this differential signal; (c) signal control means for generating a control signal related to the differential output in response to the differential output; and (c) transmitting the L-R signal components at variable output levels to the output means; Claim 1 characterized in that it comprises L-R variable transmission means responsive to the L-R signal component for transmitting the L-R signal components at higher or lower levels depending on the amplitude of the differential output from the capacitor means.
The device described in.