JPS635928B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a Reed-Solomon code encoding method for data transmission and the like. Reed-Solomon code is a type of BCH code and is a non-binary code, and is known as an effective code for burst error correction, etc. However, before explaining the Reed-Solomon encoding method, An example of a Reed-Solomon code will be explained. For example, if the data to be transmission encoded is (a ₁ , a ₂ ,
a ₃ , a ₄ , a ₅ , a ₆ ) (where each data a ₁ , a _{2 .} . . is a vector formed of m bits), the Reed-Solomon code is, for example, (c ₁ , _c2 , _c3 , _c4 , _c5 , _c6 , _c7 , _c8 ). In this case, c ₁ = a ₁ , c ₂ = a ₂ , c ₃ = a ₃ , c ₄ = a ₄ , c ₅ = a ₅ , c ₆ =
a ₆ , and c ₇ and c ₈ are It is expressed as Here, c ₁ , c ₂ , c ₃ , c ₄ , c ₅ , and c ₆ are information parts, and c ₇ and c ₈ are check parts (parity symbols). Note that α, α ² , α ³ , . . . α ⁶ in equations (1) and (2) are elements of the Galois field GF (2 ^m ) excluding 1 and 0. Also, α is a primitive element of the Galois field GF (2 ^m ), and when m = 3, α ³ + α + 1 = 0 ...(3) holds. Next, the generator matrix G in this encoding is [Each element is an element of GF(2 ³ )] If we multiply the data (a ₁ , a ₂ , a ₃ , a ₄ , a ₅ , a ₆ ) by the generator matrix G, we get the Reed-Solomon code (c ₁ , c ₂ , c ₃ , c ₄ , c ₅ , c ₆ , c ₇ , c ₈ ) can be understood from equations (1) and (2). That is, considering the generation matrix G of equation (4),
Codes with generator matrix G (c ₁ , c ₂ , c ₃ , c ₄ , c ₅ , c ₆ ,
c ₇ , c ₈ ) all satisfy the following equation. (c ₁ , c ₂ , c ₃ , c ₄ , c ₅ , c ₆ , c ₇ , c ₈ ) = k ₁ g ₁ +
k ₂ g ₂ +k ₃ g ₃ +k ₄ g ₄ +k ₅ g ₅ +k ₆ g ₆ (5) Here, gi is a vector corresponding to the i-th row of the generator matrix G. c ₁ = a ₁ , c ₂ = a ₂ , c ₃ = a ₃ , c ₄ = a ₄ , c ₅ = a ₅ , c ₆ =
The code with a ₆ components can be found using equation (5). That is, when the generator matrix G is expressed by equation (4), the value of c ₁ is
Since g ₂ to g ₂ are 0, it depends on g ₁ , and the value of c ₂ depends on g 2 because gi (i≠2) is ₀ .
Similarly, c ₃ becomes g ₃ , c ₄ becomes g ₄ , c ₅ becomes g ₅ ,
Since c ₆ depends on g ₆ , equation (5) is (a ₁ , a ₂ , a ₃ , a ₄ , a ₅ , a ₆ , c ₇ , c ₈ ) = a ₁ g ₁ + a ₂ g ₂ + a ₃ g ₃ + a ₄ g ₄ + a ₅ g ₅ + a ₆ g ₆ ...(6), and c ₇ and c ₈ are as follows. These equations (7) and (8) correspond to the above-mentioned equations (1) and (2), respectively. In this way, the conventional encoding method for Reed-Solomon code is data (a ₁ , a ₂ , a ₃ , a ₄ , a ₅ ,
a ₆ ) by the matrix G. In the generator matrix G, each element of the matrix is GF(2 ³ )
Since this is the source of

[Table] It can be expressed as shown below. Now, let P be the 8th column of the generator matrix G, then convert from column to row and get P ^T = [α+1, α ² +1, α ³ +1, α ⁴ +1, α ⁵ +
1, α ⁶ + 1〕 ...(9) If this is expressed as a 3-bit binary number as shown above (lower is the lower value) becomes. The check part _c8 in the Reed-Solomon code was formed by multiplication of equation (9), that is, equation (2). Note that the formation of the inspection portion c ₇ is determined by c ₇ = c ₈ + ₆ 〓 ⁱ⁼¹ ai from the formula (2), c ₈ = c ₇ + ₆ 〓 ⁱ⁼¹ ai. FIG. 1 is a block diagram showing an example of a conventional method. In the figure, 1 is a parallel m-bit shift register (m=3 in the numerical example above), and 2 is a Galois field GF (2 ^m ). A multiplier, 3 is a shift register that shifts and inputs parallel m-bit data (a ₁ + a ₂ , ... a ₆ ) in data units and holds samples, 4 is an exclusive OR gate, and 5 is an information section and a check section. is a selector for The input is m from the input terminal indicated by 10.
Bits are input in parallel, and the data (a ₁ , a ₂ ,...
a ₆ ) are shifted sequentially to obtain information bits (c ₁ , c ₂ ,...
c ₆ ) from the upper contact of selector 5 to output terminal 2.
0, and when this output is finished, the selector 5 is connected to the lower contact, and an arithmetic circuit consisting of a multiplier 2, an exclusive OR gate 4, and a parallel m-bit shift register 1 calculates the equation (1) and the equation ( The inspection parts c ₇ and c ₈ created by the calculation in 2) are output. At this time, multiplier 2
One input A is (a ₁ , a ₂ ,...a ₆ ), and the value given by equation (5) as the other input B is the shift register 3 in the lower part from the dashed-dotted line in Figure 1. and exclusive OR gate 4. “1” or “0” at the left end of the lower part of Figure 1 is c ₇
Indicates the input to be switched depending on the occurrence of c8 or _c8 . In other words, the conventional encoding device can be divided into a _data register section above the dashed-dotted line in ^FIG . For example, in a generator for the elements of the field GF(2 ^m ), the elements must be generated in the order shown in equation (9), and must be generated by a feedback operation using the shift register 3 and the exclusive OR gate 4. , This resulted in a disadvantage that the circuit became complicated and required many parts. The purpose of this invention is to eliminate the above-mentioned drawbacks of conventional encoding methods, and to provide an encoding method that can simplify the α _i generator.The method of the present invention will be explained in detail below. . From the explanation of equations (6) to (8) above, it is clear that the order of the terms on the right side of equation (5) may be changed arbitrarily. Therefore, by changing the order of the binary numbers in equation (10), By doing this, it is possible to easily generate the patterns included in S _P ^T ₀ (formula (7)) in order from the first item using a binary counter.
This is much simpler than the need for the shift register 3 and exclusive OR gate in Figure 1 in order to generate the patterns included in S _P T (Equation (7)) in order from the first item. This means that α ⁱ can be generated using a similar circuit. P T ₀ corresponding to S _P ^T ₀ shown in equation (11) _{is P T 0} ^{= [} α ³ +1, α+1, α ⁶ +1, α ² +1, α ⁵ +
1, α ⁴ +1] ...(12) In this case, the generator matrix corresponding to equation (4) is However, the data input order of data (a ₁ , a ₂ , a ₃ , a ₄ , a ₅ , a ₆ ) is (a ₃ , a ₁ , a ₆ , a ₂ , a ₅ , a ₄ )
...(14) Change the generation matrix to shall be. Then, by multiplying the data changed to the arrangement order expressed by equation (14) by the generator polynomial expressed by equation (15), we get (a ₃ , a ₁ , a ₆ , a ₂ , a ₅ , a ₄ ,
c ₇ , c ₈ ) ...(16) A Reed-Solomon code is obtained. In this case, the inspection part c ₈ is c ₈ = a ₃ (α ³ +1) + a ₁ (α + 1) + a ₆ (α ^{6 +} 1) +
a ₂
It is expressed as (α ² +1) +a ₅ (α ⁵ +1) + a ₄ (α ⁴ +1), which is equivalent to equation (2). Also, c ₇ can be calculated from c ₈ as in the conventional case. FIG. 2 is a block diagram showing one embodiment of the present invention. In FIG. 2, the same reference numerals as in FIG. 1 indicate the same parts and perform the same operations, so a description thereof will be omitted. The difference from FIG. 1 is that the portion below the one-dot chain line in FIG. 1, that is, the portion where α ⁱ occurs, is replaced with a binary counter 6. _{In addition ,} data in which _the arrangement _order of vectors _{a 1} , a ₂ . Ru. The count value of the binary counter 6 is sequentially changed by the system clock related to the input of the above data, that is, the shift timing. As a result of multiplication by multiplier 2, the Reed-Solomon code shown in equation (16) is output at output terminal 2.
It is clear that the output is from 0. By the way, when decoding the Reed-Solomon code encoded in this way, the decoding corresponding to the encoding of the present invention, that is, using a binary counter, is performed based on the same generation matrix shown in equation (15). When decoding, there is no problem; it is simply an inverse transformation of encoding, and the decoded data is output in the order of a ₃ , a ₁ , a ₆ , a ₂ , a ₅ , and a ₆ . On the other hand, if a Reed-Solomon code encoded by the encoding method of the present invention is to be decoded by a conventional decoding method, some kind of conversion device is required.
That is, reversible encoding/decoding conversion cannot be performed between the generation matrix generated by G ₁ in equation (15) and the generation matrix generated by G ₀ in the conventional equation (4). Therefore, in this case, when encoding according to the present invention, the array conversion of data is exactly the opposite, that is, (a ₃ , a ₁ , a ₆ , a ₂ , a ₅ , a ₄ , c ₇ , c ₈ ) →
(a ₁ , a ₂ , a ₃ , a ₄ , a ₅ , a ₆ , c ₇ , c ₈ ) is required. Note that this data array conversion can be easily handled by simply changing the connections on the input and output sides of the code and decoder. Although the above explanation has been about the embodiment of the present invention in the case of m=3, it goes without saying that the method of the present invention can be applied to the encoding of any Reed-Solomon code, and can also be applied to the decoding of Reed-Solomon codes. It is clear that it can also be applied to As described above, according to the Reed-Solomon code encoding method of the present invention, the element α ⁱ of the Galois field GF (2 ^m ) can be configured with a binary counter, which has the advantage of simplifying the circuit. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional method, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a parallel m-bit shift register, 2 is a multiplier in Galois field GF (2 ^m ), and 3 is 1
4 is an exclusive OR gate, 5 is a selector, and 6 is a binary counter. Note that the same reference numerals in each figure indicate the same parts.

Claims (1)

[Claims] 1. A shift register that sequentially holds samples of multiple pieces of data (vectors) each consisting of m bits, an m-bit binary counter that sequentially adds (or subtracts) and outputs one by one in synchronization with the shift timing of this shift register, and this binary counter. It is equipped with a multiplier that multiplies the count value of and the data value of the shift register above on the Galois field GF (2 ^m ), an adder that sequentially adds the output of this multiplier on the Galois field GF (2 ^m ), Change the input order of data to the register by increasing (or decreasing) the original binary table (binary numbers) of the Galois field GF (2 ^m ) of each data.
A Reed-Solomon code encoding method characterized by sequential correspondence.