JPS6359019A - Pulse phase adjusting circuit - Google Patents

Abstract

PURPOSE:To control a phase difference through the remote control by applying a variable DC voltage to a gate of a FET to delay the leading edge of a pulse. CONSTITUTION:The gate of a FET is connected to a connecting point between a capacitor C1 and a resistor R1 connected in series with a pulse generator 40. Then a variable resistor 20 whose DC voltage is made adjustable is connected to a ground capacitor C3 connected to other terminal of a variable resistor 20 whose one terminal is connected to the connecting point. A phase difference is made to a desired value by the variable resistor 20 before the start of measurement and the measured accuracy and the threshold value are set. Since a dotted line block including the variable resistor 20 is provided at a position parted from a case of a sensor shown in one-dashed chanin lines, the phase difference is controlled easily from a remote location without touching the case of the sensor.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention connects a series circuit of a capacitor and a resistor to a charging/discharging circuit and a pulse generator, and connects a connection point between the capacitor and the resistor to the gate of an FET. The present invention relates to pulse transmission circuits with such configurations, and in particular to circuits that adjust the phase of pulse signals in such circuits, and is applicable to water level gauges using capacitance sensors, the tip of robot hands, or on belt conveyors. It can be widely applied to the detection of objects.

[Prior Art 1] Conventionally, there have been measuring devices such as water level meters using capacitance sensors that change the resonance frequency by changing the capacitance and detect the change. However, such conventional measuring devices have drawbacks in detection accuracy and temperature compensation. In response to this, a phase comparison type measurement circuit has recently been developed. This detects the difference in capacitance between two capacitive elements as a phase difference. That is, as shown in FIG. 4, a pulse signal is supplied to the resistor R7 connected in series with the detection element C7, while the comparison element C2 is supplied with a pulse signal.
The same pulse signal is also supplied to the resistor R2 connected in series with C, and the phase change due to the change in capacitance of C is expressed as F.
Detection is performed using two inverter circuits 50 and 52 made of ET input type CMOS ICs and a 7-lip 70-tube 60 connected thereto.

In such a method based on phase difference detection, in order to increase the detection accuracy, C before starting the measurement.

It is necessary to match the phases of the side and the 02 side as precisely as possible, or to separate them by a predetermined interval. It is also desirable to be able to precisely control the phase difference in advance, depending on the difference in the object to be tested, the mode of measurement, or the setting of a threshold.

The phase of the pulse signal passing through C8 and C2 is C], Ro
are determined by the time constants (C, xR,) of the series circuit of C2 and R2 and the time constants (C2XR2) of the series circuit of C2 and R2, respectively.

Therefore, by adjusting C1, R1, C2, and R2, the above phase difference can be set arbitrarily. Generally, it is difficult to continuously and significantly adjust the capacitance of a capacitor, and it is only possible to change it in steps or to obtain minute changes using a trimmer capacitor. Fig. 5 schematically shows one side of the circuit shown in Fig. 4, and Figs. 6 and 7 show the device shown in Fig. 5 with a variable resistor 10 or trimmer capacitor 12 added as a phase adjustment means. This shows the configuration. In the case of FIG. 4, the phase difference is appropriately set by manually adjusting the variable resistor 10 as in FIG. 6.

[Problems to be Solved by the Invention] In the conventional device shown in FIG. 4 above, the portions indicated by thick lines in the figure must be wired as short as possible.

Furthermore, the tray capacity and distributed capacity may cause errors and malfunctions. The same applies to the cases of FIGS. 6 and 7. Therefore, the variable resistor 10 and trimmer capacitor 12 shown in FIGS. 4, 6, and 7 cannot be separated far from the sensor body including the capacitor CI.

For this reason, if the sensor is located at an extremely low or high location, or inside a complex device, phase adjustment is extremely difficult and, in some cases, virtually impossible. As described above, the conventional device has a problem in that phase adjustment cannot be easily performed.

[Means and effects for solving the problem] In the present invention, the time constant itself of the CR charging/discharging circuit is not changed, but instead, a DC voltage is applied to the connection point between the capacitor and the resistor, that is, the gate of the FET, and a pulse is generated. By delaying the rise of the DC voltage and adjusting this DC voltage with a variable resistor, the pulse delay time is controlled, and thus the phase difference is precisely controlled.

In this way, in the present invention, since the variable DC voltage is applied to the gate of the FET, the variable resistor does not need to be placed near the sensor body, and therefore remote control is possible.

In the present invention, the first pulse generator is connected in series to the pulse generator.
A series circuit of a resistor and a first capacitor, and an F having a gate connected to a connection point of the first resistor and the first capacitor.
In a pulse transmission circuit having an ET, a second resistor having one end connected to the connection point, a grounding capacitor connected to the other end of the second resistor, and a second resistor connected to a DC power supply and having one end connected to the second resistor.
A pulse phase adjustment circuit is provided which includes a variable resistor that can adjust the DC voltage applied to the other end of the resistor.

[Example] 1 to 4 are circuit diagrams showing embodiments of the present invention.

FIG. 1 shows an example in which an FET element is used, and FIG. 2 shows an example in which an FET input type CMOS IC is used. For the sake of simplicity, FIGS. 1 and 2 only show the detection capacitance element C1 side and omit the comparison element side. In FIG. 3, the circuits of both the detection element CI and comparison element C2 are combined. In the figure, R,, R2, and R3 are resistances, 4
0 is a pulse generator, C3 is a fundensor, 20 is a variable resistor, and Ec is a DC power supply.

In the figure, the dashed-dotted line indicates the part to be housed in the sensor case.

The resistor R3 has a high resistance value, for example, about IMΩ, and preferably has stable temperature characteristics such as a metal oxide film resistor. The capacitor c3 is a bus capacitor with one end connected to the connection point between the resistor R3 and the variable resistor 20 and the other end grounded, and serves to ground unnecessary noise.

A constant voltage power source is used as the DC power source Ee. This current voltage is divided by the variable resistor 20, and a desired voltage is applied to the connection α between the resistor R2 and the capacitor c (sensor element) via the resistor R8.

Before starting the measurement, the phase difference can be set to a desired value using the variable resistor 20, and the measurement accuracy and threshold can be set. Since the dotted line portion including the variable resistor 20 is arranged at a position away from the sensor case indicated by the dashed dot line portion, the phase difference can be easily controlled from a distance without touching the sensor case. The reason why the variable resistor 20 is removed from the sensor is because a high resistance is used for R3, so the factors that are involved in the time constant are R1, R2, C1, C2, R3 and the fundance of the semiconductor part of the FET. The cable section 22 from the capacitor C3 to the variable resistor 20 is F.
This is because the impedance is low compared to the input impedance of the ET, so even if it is extended for several meters or more, it will not affect the time constant.

The pulse generating circuit 40 may be configured to generate a triangular wave in addition to a normal pulse signal that generates a square pulse.

FIG. 4 shows an improved embodiment of the circuit shown in FIG.

In this embodiment, the buffer connected to the source of the FET is
A band pass filter (BPF) 62 is configured to operate at a commercial frequency (50~
60F12) as the center frequency, and its output has its polarity inverted by a polarity inverting circuit 64 and is connected to a capacitor C.
4 to the connection point between resistors R3 and R1.

In this embodiment, the high resistance R3 in FIG.
It is replaced by a series circuit of 3' and R4. Like R3, R3 has a high resistance value of about 114Ω,
R1 may be approximately 30Ω to 50Ω.

In the embodiment shown in FIG. 4, when a commercial frequency voltage is mixed in during measurement using the capacitive sensor C1, this is reduced by negative feedback. Such commercial frequency interference waves are often mixed in, especially when measuring liquids, and cause malfunctions and errors such as phase modulation of the pulse signal of the measuring circuit. In this embodiment, the commercial frequency component superimposed on the output signal of the FET is extracted using the BPF 62, and the polarity is inverted using the polarity inverting circuit 64.
By superimposing it on the DC bias from the FET, negative feedback is provided to the gate side of the FET. This makes it possible to suppress commercial frequency disturbances.

[Effect] With the configuration as described above, the manually operated variable resistor can be installed at a location away from the sensor section, and therefore the phase difference can be easily controlled by remote control even after the sensor is attached to the measurement location. becomes possible.

In addition, since the present invention can reliably perform phase control with a small number of parts, the configuration is simple and inexpensive, and since the number of parts connected to the gate of the FET is small, it can be stabilized without impairing the overall temperature characteristics. equipment can be provided.

[Brief explanation of the drawing]

1 to 4 are circuit diagrams explaining the present invention in detail;
7 are circuit diagrams showing conventional devices. C3...Detection capacitor C2...Comparison capacitor C3...Capacitors R1, R2, R3...Resistor 20...Variable resistor 22...Cable 40...Pulse generating circuit Ec... DC power supply.

Claims (4)

[Claims] (1) A pulse generator having a series circuit of a first resistor and a first capacitor connected in series to a pulse generator, and an FET whose gate is connected to a connection point between the first resistor and the first capacitor. In the transmission circuit, a second resistor having one end connected to the connection point, a grounding capacitor connected to the other end of the second resistor, and a grounding capacitor connected to the DC power source and having the other end of the second resistor connected to the second resistor. A pulse phase adjustment circuit comprising a variable resistor that can adjust the applied DC voltage. (2) The pulse phase adjustment circuit according to claim 1, wherein the first capacitor is a capacitance detection sensor, and the variable resistor is arranged at a position apart from the sensor. (3) The pulse phase adjustment circuit according to claim 1, wherein the FET is a FET input type CMOS IC. (4) providing a negative feedback circuit consisting of a bandpass filter connected to the source of the FET, a polarity inversion circuit connected to the output of the bandpass filter, and a capacitor connected to the output of the polarity inversion circuit; 2. The pulse phase adjustment circuit according to claim 1, wherein the second resistor is composed of two resistors connected in series, and the capacitor is connected to a connection point between the second resistors.