JPS6358694A - Memory type control circuit - Google Patents

Abstract

PURPOSE:To omit a high-speed operation of a control memory by converting a read pulse into a read pulse at a time point when a write address corresponding to a read address is obtained when the control information is written to a memory and diverting the read information omitted by a stop mode via the write information after driving a control information selecting circuit. CONSTITUTION:A write instruction is set to an instruction register b1 together with a write subject address 4 set to an address register b2 and the write information X set at a write information register b3 respectively. Then the control contents are informed to a control circuit b7 via a control line c1. The circuit b7 monitors the read address via an address line a2 and controls a control signal distributing circuit b9 via a control line c3 when the read address is equal to 4. Then a read pulse is turned into a write pulse and at the same time an information line d1 of a selector b10 is selected to deliver the information on a register b4 to an information line d3. In such a way, the contents of a control memory can be replaced while supplying continuously the control information to peripheral circuits. In this replacement mode only the read cycle time is needed to attain a high-speed operation of the control memory.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to memory type control circuits.

[Conventional technology]

FIGS. 3 and 3 are block diagrams of conventional memory-type control circuits. b/ is memo 'J, b-2 is command register, b3 is address register, b≠ is write data register, b! is a read data register, bB is an address counter, b7 is a control circuit, b♂ is a selector circuit, na/+ a-2+a3 and a4t are address signal lines, d/, d, 2 and d3 are data lines, c/+
c-2+ cJ+ cg and C! is the control line. No.! 6 and 6 show the timing relationship of reading and writing memory data in the configurations shown in FIGS. 3 and 6. 1/ is an address signal input to the control memory, [2 is a write signal line for the control memory, tj is a read signal line for the control memory, tl
A is the output of the control memory and tj is the input of the control memory. In the configuration example shown in FIG. 3, a memory machine cycle is allocated to each read and write operation even though there is no control memory. In the configuration example shown in Figure 1, a specific time is allocated for writing to the memory. Each configuration example operates as follows.

[In the case of Figure 3] When the write command is set in the command register of b/, the write target address (4) is set in the address register of b2, and the write data ■ is set in the write data register of b3, the data is transferred via the control line of C/. The control contents are then notified to the control circuit b7. The control circuit compares the target address input via the a/ address line with the read address obtained via the a2 address line, and 2. When they match, a write pulse is inserted into the clA control line after the read pulse. The data set in the write data register is written into the control memory by the pulse.

[In the case of Figure ≠]

When the write command is set in the command register of b/, the write target address (4) is set in the address register of b2, and the write data 00 is set in the write data register of b3, control is sent to the control circuit of b7 via the control line of c/. You will be notified of the content. The control circuit stops the address counter via the control line 02 at a predetermined timing and instead outputs a write address to the address line a3. Further, the selector circuit b selects the address line a3, and at the same time sends a write pulse to the control line Cμ.

When reading out the contents of the control memory, see Figure 3 and Figure μ.
In the method shown in the figure, the control circuit monitors the address signal of a2, and when it reaches the target address, C! A latch pulse is output to the control line of d2, and the signal on the data line of d2 is latched by the read data register of b.

[Problem that the invention seeks to solve]

In conventional memory-type control circuits, the circuit design takes into account two memory cycles for reading and writing in advance in order to update the contents of the control memory (Figure 3), or a special circuit is designed to update the contents of the control memory. It became necessary to create a circuit configuration in which time slots were prepared in advance (Fig. 1). 2
When designing a circuit that takes into account two memory cycles, in order to speed up the circuit, the control memory must be twice as fast as the circuit that uses control data, and the disadvantage is that the response speed of the memory determines the control performance. was there.

Although the method of preparing specific time slots can ease the constraints on operating speed, it has the disadvantage that it cannot supply control data continuously and complicates the configuration of peripheral circuits that use control data. Was. An object of the present invention is to eliminate the above-mentioned drawbacks when updating control data of a memory-type control circuit.

[Failure to solve the problem]

A feature of the present invention that achieves the above object is that when writing control data to the control memory, when the read address becomes the corresponding write address,
The read pulse is converted into a write pulse by a control signal distribution circuit, and the read data that has been stopped and has lost data is diverted to the write data by driving a selector circuit for selecting control data.

[For production]

The present invention updates the control data of a memory-type control circuit within the read cycle of the control memory, and continuously supplies the control data to peripheral circuits.

〔Example〕

FIG. 1 shows an embodiment of the present invention, in which b9 is a control signal distribution circuit and blo is a control data selection circuit. FIG. 2 shows the relationship between read and write timings of control data in the configuration example of FIG. 1. Embodiments of the invention operate as follows.

When the write command is set to the bz command register, the write target address (4) is set to the b2 address register, and the write data (X) is set to the bz write data register, the data is sent to the b7 control circuit via the c/ control line. The control details will be notified. The control circuit monitors the read address via the address line a2, and when the read address reaches (4), controls the control signal distribution circuit b via the control line c3 to start reading. Change the start pulse to the write pulse. The control signal simultaneously causes the blo selector circuit to select the d/ data line, and outputs the data in the write data register as control data to the d3 data line.

〔Effect of the invention〕

As explained above, in the present invention, when writing control data to the control memory, when the read address becomes the corresponding write address, the control signal distribution circuit converts the read pulse into a write pulse,
Since the read data that is stopped and data is lost is diverted to the write data by driving the selector circuit for selecting control data, the contents of the control memory are continuously supplied to the peripheral circuits. can be updated. Furthermore, since only the read cycle time is used during updating, there is no need to speed up the control memory. The present invention can be used in an address control circuit of a time-sharing type memory switch circuit and a sequence control circuit in which the control state changes as necessary.

[Brief explanation of drawings]

FIG. 1 is an embodiment of the present invention, FIG. 2 is a timing diagram of data input/output of a control memory in an embodiment of the present invention, and FIGS. 3 and 3 are configuration examples of a memory-type control circuit according to conventional technology. , 7 and 6 are timing diagrams of input/output of the control memory in conventional configuration examples. bz...control memory, b2...command register, bz...address register, blIL...write data register,
bz...read cheater register, bz...address counter, b7...control circuit, b and...address selection circuit, bri...control signal distribution circuit, blO...
・Output data selection circuit, a/+a-2+ a3 and a
≠...Address signal line, c/. c, 2+ c3+ c≠ and C evening...control signal line,
d/. d2 and d3... data lines, t/... address signal input to the control memory, t, 2... write signal line for the control memory, t3... read signal line for the control memory. ...The output of the control memory,
...Control memory input.

Claims (1)

[Claims] In a memory-type control mechanism that periodically reads out the contents of memory and supplies them as control data to peripheral circuits, a command register section holds a command for checking the contents of the memory, and an address holds an address to be written or read. a register section, a write data register section that holds write data, a read data register section that holds read data, an address counter section that periodically generates a read address and a read control signal of the memory, and the read control section. a control signal distribution unit that distributes a signal to a read signal or write signal terminal of the memory according to a control timing signal; a control timing signal that monitors the read address according to the contents of the command register unit and controls read and write to the memory; and a selector unit that selects an output signal of the write data register unit and an output signal of the control memory according to the control timing signal,
Data is written to the memory at the read timing of the memory, and during writing, the write data is provided to the peripheral circuit as control data, and the control data is written without stopping the supply of the control data to the peripheral circuit. A memory-type control circuit characterized by rewriting and reading data.