JPS6358485B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that regenerates a synchronous carrier wave by means of a phase control loop and uses this carrier wave to synchronously detect an amplitude modulated incoming input signal.

A synchronous detection circuit for amplitude detection is used, for example, in the video detection stage of a television receiver.
In particular, receivers for general home use must be able to operate stably against changes in various operating conditions such as changes in power supply voltage. However, in a video detector using a synchronous detection circuit, the detection phase changes more easily due to changes in the power supply voltage or ambient temperature than in a conventional envelope video detector, and therefore the image quality of the reproduced image may change. It has the disadvantage of being easy to use. For example, if the detection phase changes over a short period of time, such as when the power is turned on, an undesired 920kHz error may occur in the detected video signal.
Causes changes in beat and frequency characteristics. These problems pose practical problems such as giving viewers a sense of discomfort, and therefore, a video synchronous detector needs to be highly stable not only in the long term but also in the short term.

In addition, it takes about 1 to 2 minutes from the time the power is turned on for this type of circuit formed in an integrated circuit to reach a thermal equilibrium point, and this period is particularly important under certain temperature conditions among the operating conditions of the circuit. This will be the period of greatest change. (Hereinafter, "short term" used in this explanation means this period.) An example of a configuration for stably operating a synchronous detection circuit against changes in temperature conditions is disclosed in Japanese Patent Application Laid-Open No. 57-111 by the present applicant. -Disclosed in Publication No. 131106. This device shows a circuit arrangement in which changes in transistor characteristics caused by self-heating or changes in environmental temperature do not change the detection phase.

The present invention aims to provide a synchronous detection circuit as described above with good stability against changes in power supply voltage, and is particularly configured to be suitable for integrated circuits. .

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to drawings showing a conventional circuit and a circuit according to an embodiment of the present invention.

FIG. 1 shows the configuration of a phase detector using a conventional double-balanced cascode amplifier. Transistors 101, 1 forming the input differential amplifier stage
An input signal _E1 is supplied between the base electrodes of 02,
The emitter electrodes are connected by resistors 103 and 104, and a constant current source _I1 is placed at the midpoint of the connection. Transistors 201, 202, 203 and 204
is the transistor 101,1 due to the synchronous carrier wave _E2
02, and outputs positive and negative polarity video signals to load resistors 205 and 206.

Such a circuit, also called a four-quadrant multiplier, outputs the product of the input signal _E1 and the synchronous carrier wave _E2 , and the transistors 201 to 20
4 performs the product operation.

FIG. 2 is a block diagram of the phase detector described above, in which the amplifier 10 is a transistor 10.
1 and 102, and the multiplier 20 corresponds to a current path selection switch stage formed by transistors 201 to 204, respectively.

Resistors 103, 104 are transistors 101,
The purpose is to linearize the non-linear voltage-current exchange characteristics of 102, and it can be removed if the input signal _E1 is at an extremely low level, but normally it is 100mV.
(P-P), so it is necessary in a phase detector used as a video detector.

On the other hand, when the phase detector shown in Figure 1 is used as a phase comparator circuit (hereinafter abbreviated as APC detector) in a phase control loop for regenerating a synchronous carrier wave, the nonlinear distortion of this stage is Does not cause the above problem. Therefore, in many cases, the emitter electrodes of transistors constituting an input differential amplification stage are usually directly coupled without using a resistor in order to increase the amplification degree.

In a synchronous detection circuit, the relative phase difference between the input signal E ₁ and the synchronous carrier E ₂ in the multiplication section of the video detector and APC detector as described above is approximately 0 or π in the video detector.
(rad), and should be approximately π/2 (rad) for the APC detector. However, as mentioned above, the required performance of the two detectors is different, so the method of coupling the emitter electrodes of the input differential amplifier stage is different, and in actual transistors, the current converted to the phase of the input signal _E1 is different. Although it is difficult to maintain the phase at 0 or π (rad), as mentioned above, by using the synchronous detection device described in Japanese Patent Application Laid-open No. 57-131106 by the present applicant, it is possible to Practical problems caused by changes in transistor performance due to phase changes due to self-heating, environmental temperature changes, etc. are eliminated.

However, in a television receiver, the power supply voltage also changes easily, and the detection phase of the video synchronous detector must be maintained at a predetermined state even in response to such changes. A conventional method for making a synchronous detection circuit non-responsive to changes in the power supply voltage is to configure the entire circuit to be operated by the output voltage of a specially arranged power supply voltage stabilizing means. However, forming this type of stabilization means in an integrated circuit together with a synchronous detection circuit and other circuits not only significantly increases power consumption, but also increases the power supply voltage supplied to the stabilization means. It has attendant drawbacks, such as the need to

The present invention has been made in view of the above points, and will be described in detail below. FIG. 3 shows an embodiment of a synchronous detection circuit according to the present invention.
Note that parts having the same functions as those in FIG. 1 are designated by the same reference numerals.

In the figure, block 3 surrounded by a broken line is a double balanced cascode amplifier constituting a video phase detector, and transistor 30 of the input differential amplification stage
A predetermined DC bias is applied to signal input terminals 3a and 3b connected to the 1,302 pairs of base electrodes. The emitter electrodes of transistors 301 and 302 are connected to the collector electrode of constant current transistor 305 via resistors 303 and 304. Resistors 306 and 307 and a transistor 308 whose base and collector electrodes are shorted set the operating current of transistor 305. The emitter electrodes of each pair of transistors 310, 311, 312, and 313 are directly coupled to form transistor 3.
They are connected to collector electrodes 01 and 302, respectively.

The APC phase detector shown in block 4 surrounded by a broken line is also constructed from a double balanced cascode amplifier like the video phase detector, but the emitter electrodes of the transistor pair 401 and 402 in the input differential amplification stage are Directly coupled constant current transistor 403
is connected to the collector electrode of. The output of this APC detector, that is, the output signal obtained at the common connection point of the collectors of the transistors 408 and 410 is supplied to the voltage controlled oscillator 6 via the low-pass filter 5, and is supplied to the carrier wave frequency of the signal input terminals 4a and 4b. The oscillator 6 is synchronized with. In this circuit, this oscillator 6 is configured to be operated by a bias voltage or current generator 7 that is configured so as not to respond substantially to changes in the power supply voltage V _CC , so the oscillator 6 is set in advance. The free-running oscillation frequency is not affected by power supply voltage fluctuations.

The oscillator 6 is of the balanced output type and provides a regenerated synchronous carrier wave to the phase shifter 8 and the amplifier shown in block 9. The emitter electrode of the amplifier 9 is the resistor 9.
Constant current transistor 903 via 01,902
differential pair transistors 904, 905 connected to
Its base electrode is a signal input terminal, and its collector electrode is connected to the emitter electrode of a transistor 1001 constituting the non-stabilized bias generator 10 via load resistors 906 and 907.
A synchronous carrier wave is supplied to the video detector 3 described above.
In this circuit, the base electrode bias of the constant current transistor 903 of the amplifier 9 is supplied from the stabilized bias generator 7 described above. Therefore, since the bias current of transistor 903 does not respond to changes in the power supply voltage, differential pair transistors 904,
This has the advantage of not causing changes in the input impedance of 905, etc. That is, the transistor 904,
905 forms the load of the oscillator 6;
Therefore, it has a structural feature that does not affect the operation of the oscillator in any way. Transistor 904,9
The collector electrode bias of 05 is resistor 1002,
Since it is provided by the output of an unregulated bias generator 1003 that divides the power supply voltage, it responds to changes in the power supply voltage. Therefore, since all the biases of the double balanced cascode amplifier constituting the video detector of block 3 respond to changes in the power supply voltage, it has the characteristic that it can practically operate over a wide range of power supply voltages.

The phase shifter 8 has a phase shifting effect of approximately π/2 (rad), and its output is supplied to the amplifier shown in block 11, and the base electrode of the transistor 1101 forming a constant current source of this amplifier is A bias voltage is supplied from a stabilizing bias generator 7. The collector bias of the pair of amplification transistors 1102 and 1103 is unstabilized by the bias generator 1.
given by 0. This amplifier supplies a synchronous carrier wave to the APC detector 4, and since the bias current of transistor 1101 hardly changes when the power supply voltage changes, similar to the video detector, the input impedance of the pair of transistors 1102 and 1103 also changes. do not. Therefore, since the load condition of the phase shifter 8 does not change, there is an advantage that the amount of phase shift is also stable.

The present invention arranges a differential amplifier for synchronous carrier wave amplification using emitter electrode coupling means substantially similar to the input differential amplifier of the double-balanced cascode amplifier constituting the video detector and the APC detector as described above. In addition to this, the input impedance of this amplifier is prevented from changing by making it operate at a constant current using a stabilizing bias generator that does not respond to changes in the power supply voltage, and the output DC bias responds to changes in the power supply voltage. This is a configuration in which the voltage is supplied from a non-stabilized bias generator. Therefore differential amplifiers and video detectors for in-phase and quadrature synchronous carrier amplification,
When DC-coupling each APC detector,
Since the bias current and output DC bias voltage from the load resistor and stabilizing bias generator of these amplifiers can be set independently to desired states, the effective operating range of the double-balanced cascode amplifier can be expanded. The video detector and APC detector can be stably set to relatively orthogonal detection phases. Therefore, there are great industrial advantages, such as the ability to operate the synchronous detection circuit stably even when the power is turned on and when the power supply voltage changes over a long period of time.

Although the phase shifter 8 is arranged on the amplifier 11 side in the embodiment, it is of course possible to arrange it on the amplifier 9 side.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a phase detection circuit using a conventional double-balanced cascode amplifier, FIG. 2 is a block diagram thereof, and FIG. 3 is a circuit diagram of a synchronous detection circuit according to an embodiment of the present invention. 3... Video phase detector using a double balanced cascode amplifier, 4... APC phase detector using a double balanced cascode amplifier, 6... Voltage controlled oscillator, 7... Stabilized bias voltage or current generator , 8... Phase shifter, 9... Multiplier, 10...
...unregulated bias voltage or current generator.

Claims (1)

[Claims] 1 first and second phase detectors constructed using a double-balanced cascode amplifier; an oscillator, a phase shifter disposed on the output side of the oscillator so as to make the detection phases of the first and second phase detectors relatively orthogonal; and an output signal of the oscillator and the phase shifter. first and second differential amplifiers that amplify and supply the amplified and supplied signals to the first and second phase detectors via DC coupling means, respectively, and generate an unstabilized bias voltage or current using the power supply voltage as input; The first and second differential amplifiers include a first bias generation means and a second bias generation means that generates a bias voltage or current that is stabilized against changes in the power supply voltage. The load circuit and the first and second phase detectors are set to predetermined biases by the first bias generation means, and the DC bias currents of the first and second differential amplifiers and the oscillator are set to predetermined biases by the second bias generation means. A synchronous detection circuit characterized by being set in a state.