JPS635706B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides high-temperature continuous testing of semiconductor devices (hereinafter simply referred to as samples) performed by applying a power supply voltage.
This is a continuous test method that prevents defective products from returning to good quality due to subtle changes in the surface condition of the sample chip due to the residual heat generated by self-heating caused by the applied voltage after the applied voltage is cut off. be.

Continuous operation tests that are performed by applying a voltage to a sample in order to determine the typical failure rate of the sample and to prove its quality and reliability under specified conditions have traditionally been conducted using, for example, "JIS-C-7022 Test Method B. Various methods have been used, such as ``-1 Continuous Operation Test.'' According to the above JIS test method, the test conditions include voltage,
The load, ambient temperature, etc. are selected within a range that does not exceed the thermal rating of the sample and are generally representative of the maximum rating. In addition, the temperature of the sample chip in the test state involves power consumption in any form, so
The junction temperature is higher than the ambient temperature in which the sample is placed. Especially in samples for power amplification, the temperature difference is usually extremely large.

On the other hand, one of the typical causes of defects that occur in the above continuous tests is that the inversion layer of the P or N type layer near the chip surface is There is an outbreak. It is generally well known that when this type of defect, in which the surface condition is sensitive, is stored at a high temperature above room temperature without application of voltage, the defective product returns to a good product due to a kind of annealing effect. Although the return of a defective product to a non-defective product itself seems to be a positive phenomenon, there is a possibility that an incorrect judgment will be made in the pass/fail judgment after the above test, and if the voltage is applied again and the test is repeated, the product may become defective again. , is very skilled. Therefore, at the end of a continuous voltage application test conducted at a temperature above room temperature (normal temperature in semiconductor device testing usually means within 25°C ± 3°C), for example in a constant temperature oven, the voltage should be turned off to eliminate the above-mentioned annealing effect. It is preferable to remove the voltage from the thermostatic chamber while applying voltage, or to lower the temperature in the thermostatic chamber to room temperature, and to cut off the voltage when the internal temperature of the sample approaches room temperature. However, in the case of a sample that consumes a large amount of power, the junction temperature of the sample is usually significantly higher than the ambient temperature due to self-heating caused by voltage application. Therefore, even if the sample is placed at room temperature, due to the residual heat of the sample,
This is the same as if the sample was kept at a high temperature for a certain period of time after the voltage application was stopped, and the annealing effect described above occurs. To prevent this, there is a method of forcibly cooling the sample before turning off the voltage, but it takes time and effort to know when the junction temperature of the sample has reached room temperature, and it is also difficult to set the amount of cooling. . Furthermore, in order to lower the temperature of the chip to room temperature, the package temperature must be lowered even further, which has the disadvantage of imposing additional stress on the sample.

The present invention solves the above-mentioned problems.In a continuous operation test, even in the case of a sample that consumes a large amount of power, the voltage is lowered continuously or stepwise over a certain period of time, and the temperature of the sample chip is lowered. The annealing effect is reduced by applying voltage until it reaches room temperature and then turning off the power, and this is to prevent defective products that are sensitive to surface conditions from returning to good quality. It is characterized by the fact that

Hereinafter, the present invention will be explained in more detail using a time chart regarding the sample temperature, ambient temperature, voltage application, and disconnection from the test state to the end of the test, using a continuous operation test using a constant temperature bath as an example. .

Note that the sample temperature is the temperature of the sample chip at each time, and is transient. In addition, the ambient temperature is the temperature in the atmosphere in which the sample is placed, and when the sample is placed in a constant temperature bath, the temperature of the constant temperature bath,
When taken out to room temperature, it indicates room temperature. In Figures 1 to 3, the horizontal axis t indicates the passage of time;
Shows the state from the test state to the end of the test. The period after t=2 indicates the end of the test.

FIG. 1 shows the case of a sample with low power consumption by the conventional method.

Until t=0, the sample is placed in a constant temperature bath at a temperature higher than room temperature, and a voltage is applied to the sample in a test state.
The sample temperature is increased by self-heating due to power consumption,
The temperature is slightly higher than the ambient temperature.

At t=0, the sample is taken out from the thermostatic chamber, and at t=0
From then on, the ambient temperature remained at room temperature. As a result, the sample temperature gradually decreases, but since the voltage is applied, the sample temperature remains slightly higher than room temperature.

At t±1, the voltage is cut off and power consumption disappears. After t=1, the sample temperature decreases to room temperature.

Here, the period and amount until the residual heat due to self-heating becomes zero after the voltage is cut off is shown by the shaded area A, and it can be seen that the annealing effect is small.

FIG. 2 shows a case where a conventional method is used for a sample that consumes a large amount of power.

In the test state in a constant temperature chamber until t = 0,
Due to the large amount of self-heating, the difference between the sample temperature and the ambient temperature is larger than that in Figure 1.
Accordingly, the temperature of the constant temperature bath is set lower than that in the case of FIG.

Even if the sample is taken out of the thermostatic chamber at t=0 and left at room temperature, the sample temperature remains considerably higher than room temperature until the voltage is cut off at t=1 due to large power consumption.

Therefore, the period and amount of residual heat due to self-heating from t = 1 to zero is in the shaded area B, where the annealing effect is greater than the shaded area B in Figure 1, which shows the case of a sample with low power consumption. This becomes a problem.

FIG. 3 shows the case of a sample with large power consumption by the method of the present invention. The period up to t=1 is exactly the same as in Figure 2 for the conventional method,
Even when the sample is left at room temperature, the sample temperature remains considerably higher than room temperature due to large power consumption.

However, since the voltage is gradually reduced over a certain period of time from t=1 to t=1', at t=1' when the voltage is completely cut off, the sample temperature has dropped to near room temperature. The period and amount of residual heat due to self-heating after the voltage is cut off is shown by the shaded area A'. As can be seen from the figure, the shaded area A' in FIG. 3 is equal to or smaller than the shaded area A in FIG. In continuous operation tests for samples with large power consumption, it is possible to prevent defective products that are sensitive to surface conditions from reverting to non-defective products at the end of the test. It has the following.

In addition, as a method of lowering the voltage, we have shown an example using three steps, but the number of steps may be any number.
Alternatively, it may be decreased continuously.

Further, the amount of voltage drop change and the certain time required for the voltage drop are arbitrarily and appropriately set depending on the circuit type and power consumption of the sample. The present invention is effective when performing voltage application high temperature continuous tests on integrated circuits such as Zener, which are extremely sensitive to temperature drift, and integrated circuits with output circuits.

[Brief explanation of the drawing]

Figure 1 is a time chart for a sample with low power consumption by the conventional method, Figure 2 is a time chart for a sample with high power consumption by the conventional method, and Figure 3 is a time chart for a sample with high power consumption by the method of the present invention. This is a time chart for a large sample.

Claims (1)

[Claims] 1. Semiconductor devices are subjected to high-temperature conditions in a voltage-applied high-temperature continuous test in which a specified power supply voltage is applied and electrical operation is performed continuously under a specified ambient temperature higher than room temperature. After the release, the voltage applied to the semiconductor device is continuously or stepwise reduced to lower the junction temperature of the semiconductor device to near room temperature while the voltage remains applied, and then the test is terminated. Voltage application high temperature continuous test method for semiconductor devices.