JPS6356709B2 - - Google Patents
Info
- Publication number
- JPS6356709B2 JPS6356709B2 JP54135265A JP13526579A JPS6356709B2 JP S6356709 B2 JPS6356709 B2 JP S6356709B2 JP 54135265 A JP54135265 A JP 54135265A JP 13526579 A JP13526579 A JP 13526579A JP S6356709 B2 JPS6356709 B2 JP S6356709B2
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- gate
- layer
- electrode
- conductive region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000006073 displacement reaction Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims 1
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- IZJSTXINDUKPRP-UHFFFAOYSA-N aluminum lead Chemical compound [Al].[Pb] IZJSTXINDUKPRP-UHFFFAOYSA-N 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7428—Thyristor-type devices, e.g. having four-zone regenerative action having an amplifying gate structure, e.g. cascade (Darlington) configuration
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】
この発明は半導体装置にかかり、特に電気特性
の向上を目的とする改良構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to an improved structure for improving electrical characteristics.
従来の半導体装置の１例として第１図ないし第
３図に示される半導体制御整流装置（以降サイリ
スタと略称）がある。第１図はこの装置の上面
図、第２図は第１図のAA′線に沿う断面図、第３
図はサイリスタの断面図である。図において、１
は導電型がＮのサブストレートである第１の導電
域、２ｇ，２ａは第１の導電域の両主面に形成さ
れた導電型がＰの第２の導電域および第３の導電
域で、２ｇはゲート層、２ａはアノード層となる
もので、ゲート電極２Ｇ、アノード電極２Ａが設
けられている。また３ｃはゲート層に形成された
これと反対のＮ導電型のエミツタ層で、エミツタ
電極３Ｋが設けられている。なお、ゲート層とエ
ミツタ電極とは短絡部を設けたいわゆるエミツタ
短絡構造（シヨーテツドエミツタ）をとりdV／
dt耐量を向上させる構造になり、これについては
後に詳述する。次に、エミツタ電極の周縁と平行
にこれを取り囲む補助エミツタ電極３Ｇはエミツ
タ層とゲート電極との間に導電型Ｎに形成された
補助エミツタ層３ｅに接続する。次に第３図につ
いて、４は上述の半導体素子でこれを両主面の電
極に圧接支持する圧接電極４Ａ，４Ｋにて導出し
かつ気密に封止する外囲器５に内装されサイリス
タが形成される。 An example of a conventional semiconductor device is a semiconductor controlled rectifier device (hereinafter abbreviated as thyristor) shown in FIGS. 1 to 3. Figure 1 is a top view of this device, Figure 2 is a sectional view taken along line AA' in Figure 1, and Figure 3 is a top view of this device.
The figure is a cross-sectional view of a thyristor. In the figure, 1
2g and 2a are a first conductive region whose conductivity type is a substrate of N, and 2g and 2a are a second conductive region and a third conductive region whose conductivity type is P, which are formed on both main surfaces of the first conductive region. , 2g is a gate layer, and 2a is an anode layer, in which a gate electrode 2G and an anode electrode 2A are provided. Further, 3c is an emitter layer of N conductivity type opposite to this formed on the gate layer, and an emitter electrode 3K is provided. Note that the gate layer and the emitter electrode have a so-called short-circuited emitter structure (short-circuited emitter), and the dV/
It has a structure that improves dt resistance, which will be detailed later. Next, an auxiliary emitter electrode 3G that surrounds the emitter electrode in parallel with its periphery is connected to an auxiliary emitter layer 3e of N conductivity type formed between the emitter layer and the gate electrode. Next, referring to FIG. 3, reference numeral 4 denotes the above-mentioned semiconductor element, which is led out by press-contact electrodes 4A and 4K that are press-supported to the electrodes on both main surfaces, and is housed in an envelope 5 that is hermetically sealed to form a thyristor. be done.
サイリスタについて周知のように、順方向に急
激な立上りの電圧（dV／dt Ｔ）を印加すると変
位電流が流れ、ゲート・エミツタ間接合を順バイ
アスしキヤリアの注入を起してサイリスタをター
ン・オンさせる。また高温での動作時でも漏れ電
流により同様にターン・オンする。これらを防ぐ
ためにＰベース領域２ｇをエミツタ電極３Ｋとシ
ヨートし、発生した変位電流または漏れ電流をバ
イパスしゲート・エミツタ間接合からのキヤリア
の注入を防ぐいわゆる、エミツタ短絡構造が提案
されている。これによればdV／dt耐量はかなり
向上し効果が認められる。しかし、素子の約１〜
３割を占めるゲート部で発生する変位電流または
漏れ電流はバイパス径路がないため、エミツタ層
のある一部に集中して流れ局部的なターン・オン
を引起こす。単純なゲート構造であれば上記電流
はエミツタ電極に流れdV／dt耐量はある程度強
いが、di／dt耐量を大きくするためあるいは大口
径になればなるほどゲート構造が複雑になり、ゲ
ート近くで発生した上記電流が大きくなり、ター
ン・オンしやすくなる。 As is well known about thyristors, when a rapidly rising voltage (dV/dt T) is applied in the forward direction, a displacement current flows, which forward biases the gate-emitter junction and causes carrier injection to turn on the thyristor. let It also turns on due to leakage current even when operating at high temperatures. In order to prevent this, a so-called emitter short-circuit structure has been proposed in which the P base region 2g is shorted with the emitter electrode 3K to bypass the generated displacement current or leakage current and prevent carrier injection from the gate-emitter junction. According to this, the dV/dt tolerance is considerably improved and the effect is recognized. However, about 1~
Since there is no bypass path, the displacement current or leakage current generated in the gate portion, which accounts for 30% of the total, concentrates on a certain part of the emitter layer and causes local turn-on. If the gate structure is simple, the above current flows to the emitter electrode and the dV/dt withstand capability is strong to some extent, but as the di/dt capability is increased or the diameter becomes larger, the gate structure becomes more complex and the current occurs near the gate. The above current increases, making it easier to turn on.
この発明は従来の欠点を改良し、エミツタ電極
またはエミツタ層とゲート近傍領域を電気的に接
続する手段を設けて素子全体のdV／dt耐量を上
げ高温で動作できる半導体装置の構造を提供す
る。尚ゲート近傍とは、補助エミツタとゲート電
極との距離と同程度かそれより短い程度の距離で
ゲート電極に近接している領域を示すものであ
る。 The present invention improves the conventional drawbacks and provides a structure for a semiconductor device that can operate at high temperatures by increasing the dV/dt withstand capability of the entire device by providing means for electrically connecting the emitter electrode or emitter layer to the region near the gate. Note that the term "near the gate" refers to a region that is close to the gate electrode at a distance that is approximately the same as or shorter than the distance between the auxiliary emitter and the gate electrode.
この発明はゲート近傍部のdV／dtによる変位
電流または高温で発生する漏れ電流を直接エミツ
タへ流入しないようにして目的を達成するもので
あり、上記ゲート近傍はゲート電極の周りに発生
する変位電流をエミツタ電極に流せる部位を示す
ものである。 This invention achieves the object by preventing the displacement current due to dV/dt in the vicinity of the gate or the leakage current generated at high temperature from directly flowing into the emitter. This shows the part where the ion beam can flow to the emitter electrode.
以下に一実施例につき図面を参照して説明す
る。 One embodiment will be described below with reference to the drawings.
まず、この発明の１実施例は第４図に素子の上
面図、第５図に第４図のBB′に沿う断面図、第６
図にサイリスタの断面図で示される。図におい
て、１は導電型がＮのサブストレートである第１
の導電域、２ｇ，２ａは第１の導電域の両主面に
形成された導電型がＰの第２の導電域および第３
の導電域で、２ｇはゲート層、２ａはアノード層
となるもので、ゲート電極２Ｇ、アノード電極２
Ａが設けられている。また３ｃはゲート層に形成
されたＮ導電型のエミツタ層で、エミツタ電極３
Ｋが設けられている。なお、ゲート層とエミツタ
電極とはその間に短絡部を設けたいわゆるエミツ
タ短絡構造をとりdV／dt耐量を向上させる構造
になつている。（この構造について後述する）。 First, one embodiment of the present invention is shown in FIG. 4, a top view of the device, FIG. 5 a cross-sectional view taken along line BB' in FIG.
The figure shows a sectional view of a thyristor. In the figure, 1 is the first substrate whose conductivity type is N.
The conductive areas 2g and 2a are the second conductive area of conductivity type P formed on both main surfaces of the first conductive area, and the third conductive area.
In the conductive region, 2g is a gate layer, and 2a is an anode layer, with a gate electrode 2G and an anode electrode 2.
A is provided. Further, 3c is an N conductivity type emitter layer formed in the gate layer, and the emitter electrode 3
K is provided. Note that the gate layer and the emitter electrode have a so-called emitter short-circuit structure in which a short-circuit portion is provided between them to improve the dV/dt withstand capability. (This structure will be discussed later).
次にエミツタ電極の周縁と平行にこれを取り囲
み形成された補助エミツタ電極３Ｇはエミツタ層
とゲート電極との間に導電型Ｎに形成された補助
エミツタ層３ｅに接続されている。また、補助エ
ミツタ電極とエミツタ電極またはエミツタ層との
間のゲート層は配線６によつて接続されている。
この接続の具体例として圧接型に適するものを第
６図に示す。これは半導体素子４′が両主面のア
ノード電極２Ａとエミツタ電極３Ｋに接する圧接
電極４Ａ，４K′にて支持され、かつ、気密に封
止する外囲器５′に内装されサイリスタが形成さ
れるものにおいて、エミツタ側圧接電極４K′に
配線６を支持するスプリング６ａを収める開孔７
が設けられ、配線６が、補助エミツタ電極とエミ
ツタ電極またはエミツタ層との間のゲート層の一
部に弾接する。 Next, an auxiliary emitter electrode 3G formed parallel to and surrounding the periphery of the emitter electrode is connected to an auxiliary emitter layer 3e of conductivity type N formed between the emitter layer and the gate electrode. Further, the gate layer between the auxiliary emitter electrode and the emitter electrode or emitter layer is connected by a wiring 6.
As a specific example of this connection, one suitable for pressure contact type is shown in FIG. In this case, a semiconductor element 4' is supported by pressure contact electrodes 4A and 4K' that are in contact with an anode electrode 2A and an emitter electrode 3K on both main surfaces, and is housed in an airtightly sealed envelope 5' to form a thyristor. In this case, an opening 7 for housing a spring 6a that supports the wiring 6 is provided in the emitter side press-contact electrode 4K'.
is provided, and the wiring 6 comes into elastic contact with a part of the gate layer between the auxiliary emitter electrode and the emitter electrode or emitter layer.
上述の構造はいわゆる増幅ゲートの改良と見ら
れ、まず、増幅ゲートはゲート電流の十数倍の電
流を主サイリスタへのトリガー電流となる様にし
たものであるが、従来の増幅ゲートにあつてはゲ
ート部で発生した変位電流あるいは漏れ電流のほ
とんどは補助サイリスタのＮ・エミツタ層の下部
を通つて（第２図に破線矢にて示す）エミツタ層
３ｃに流入するようになり、これらの電流はゲー
ト部の面積に比例し大きな電流となり補助サイリ
スタのＮ・エミツタ層を順バイアスし、キヤリア
の注入を起しターン・オンさせる。しかし、この
発明によるものは変位電流あるいは漏れ電流が補
助サイリスタの下部を通ることなく、ボンデイン
グされたアルミニウムリードを通つてエミツタ電
極へ流入するためキヤリアの注入は生ぜず、
dV／dt耐量は大となり、漏れ電流によターン・
オンも防ぐことができる。上記実施例の構造をも
つた例えば40φのパターンについてみると、ボン
デイングのない場合のdV／dtが1000〜1500V／
μsであつたものに比較して2000〜3000V／μsに向
上した。なお、第７図はdV／dtを説明するため
の図で、横軸に時間ｔ、縦軸に電圧Ｖを夫々と
り、曲線VpからdV／dtを求める場合、dV／dt
＝0.632V2／t2による（但し0.632は１−１／ｅよ
り導かれる）。 The above structure can be seen as an improvement on the so-called amplification gate. First, the amplification gate uses a current that is more than ten times the gate current as the trigger current to the main thyristor. Most of the displacement current or leakage current generated at the gate part flows into the emitter layer 3c through the lower part of the N emitter layer of the auxiliary thyristor (indicated by the dashed arrow in Figure 2), and these currents becomes a large current in proportion to the area of the gate portion, forward biasing the N emitter layer of the auxiliary thyristor, causing carrier injection and turning it on. However, in the device according to the present invention, the displacement current or leakage current does not pass through the bottom of the auxiliary thyristor, but flows into the emitter electrode through the bonded aluminum lead, so no carrier injection occurs.
The dV/dt withstand capacity becomes large, and the leakage current causes a turn.
It can also be prevented from turning on. For example, for a 40φ pattern with the structure of the above example, the dV/dt without bonding is 1000 to 1500V/
Compared to the one with μs, the voltage was improved to 2000-3000V/μs. In addition, Fig. 7 is a diagram for explaining dV/dt, where the horizontal axis is time t and the vertical axis is voltage V, and when calculating dV/dt from the curve Vp, dV/dt
= 0.632V 2 /t 2 (however, 0.632 is derived from 1-1/e).
次に上記エミツタ電極に例えばリード線で接続
するゲート層部位は可能な限り補助エミツタ電極
のＮ・エミツタ層に近接させる方が有効である。
この理由は第８図に示す如く、Ｘ点で発生した変
位電流、または漏れ電流を直接エミツタ電極に注
入することなくピツクアツプしてワイヤ６を介し
てエミツタ電極に流し、この発明の目的を達する
ものである。 Next, it is effective to place the gate layer portion connected to the emitter electrode, for example, by a lead wire, as close as possible to the N emitter layer of the auxiliary emitter electrode.
The reason for this is that, as shown in FIG. 8, the displacement current or leakage current generated at point X is not directly injected into the emitter electrode, but is picked up and passed through the wire 6 to the emitter electrode, thereby achieving the object of the present invention. It is.
さらに、この発明は第９図の等価回路で示され
る如く、ゲートとエミツタとの間に抵抗ｒを挿入
したものと等価であり、この抵抗を通してノイズ
等の微小電流をバイパスでき、誤点弧を防止しう
る利点もある。 Furthermore, as shown in the equivalent circuit of FIG. 9, this invention is equivalent to inserting a resistor r between the gate and the emitter, and through this resistor, minute currents such as noise can be bypassed, preventing false firing. There are also benefits to prevention.
次に、第１０図ないし第１４図の各々にこの発
明の実施例を示す。第１０図はゲート層がエミツ
タ電極３K′の延在部６Ｋによつて接続された例、
第１１図はゲート層との接続点をゲート電極に並
列に設けた例、第１２図はエミツタ層に接続した
例、第１３図はゲート層との接続部を第１１図に
準じて設けた例、第１４図はゲート層との接続部
を第１１図（第１３図）に準じ、エミツタ層との
接続を第１２図に準じて夫々設けた例である。な
お、この発明は上に述べた実施例に限定されるこ
となく、これらを任意に取り合わせて広く一般の
半導体装置に適用できることはいうまでもない。 Next, embodiments of the present invention are shown in FIGS. 10 to 14, respectively. FIG. 10 shows an example in which the gate layer is connected by an extension 6K of the emitter electrode 3K'.
Figure 11 shows an example in which the connection point with the gate layer is provided in parallel with the gate electrode, Figure 12 shows an example in which it is connected to the emitter layer, and Figure 13 shows an example in which the connection point with the gate layer is provided in accordance with Figure 11. For example, FIG. 14 shows an example in which the connection with the gate layer is provided according to FIG. 11 (FIG. 13), and the connection with the emitter layer is provided according to FIG. 12. It goes without saying that the present invention is not limited to the above-described embodiments, and can be applied to a wide range of general semiconductor devices by arbitrarily combining these embodiments.
第１図ないし第３図は従来のサイリスタに関
し、第１図は素子の上面図、第２図は第１図の
AA′線に沿う断面図、第３図はサイリスタの断面
図、第４図ないし第６図はこの発明の１実施例の
サイリスタに関し、第４図は素子の上面図、第５
図は第４図のBB′線に沿う断面図、第６図はサイ
リスタの断面図、第７図および第８図はいずれも
この発明の機能を説明するための図、第９図は上
記の実施例のサイリスタの等価回路図、第１０図
ないし第１４図はいずれも夫々がこの発明の実施
例である素子の上面図である。
なお、図中同一符号は同一または相当部分を
夫々示すものとする。２ａ……アノード層、２Ａ
……アノード電極、２ｇ……ゲート層、２Ｇ……
ゲート電極、３ｃ……エミツタ層、３ｅ……補助
エミツタ層、３Ｋ，３K′……エミツタ電極、３
Ｇ……補助エミツタ電極、４，４′……半導体素
子、４Ａ，４Ｋ……圧接電極、６，６Ｋ……電気
接続手段（６はワイヤー、６Ｋは金属層）。
Figures 1 to 3 relate to conventional thyristors, with Figure 1 being a top view of the element and Figure 2 being the same as Figure 1.
3 is a sectional view of the thyristor, FIGS. 4 to 6 relate to a thyristor according to an embodiment of the present invention, FIG. 4 is a top view of the element, and FIG.
The figure is a cross-sectional view taken along line BB' in Figure 4, Figure 6 is a cross-sectional view of the thyristor, Figures 7 and 8 are diagrams for explaining the functions of the present invention, and Figure 9 is the The equivalent circuit diagrams of the thyristor of the embodiment, FIGS. 10 to 14, are each top views of elements that are embodiments of the present invention. Note that the same reference numerals in the figures indicate the same or corresponding parts, respectively. 2a...Anode layer, 2A
...Anode electrode, 2g...Gate layer, 2G...
Gate electrode, 3c... Emitter layer, 3e... Auxiliary emitter layer, 3K, 3K'... Emitter electrode, 3
G: auxiliary emitter electrode, 4 , 4 ': semiconductor element, 4A, 4K: pressure contact electrode, 6, 6K: electrical connection means (6 is wire, 6K is metal layer).
Claims (1)
域と、この基板の両主面に形成された反対導電型
の第２の導電域および第３の導電域と、第２の導
電域に形成された一導電型のエミツタ層と、第２
の導電域に設けられたゲート電極と、第３の導電
域に設けられたアノード電極と、前記エミツタ層
に設けられたエミツタ電極と、ゲート電極と前記
エミツタ層との間に形成された一導電型の補助エ
ミツタ層と、前記ゲート電極近傍で発生する変位
電流、あるいは漏れ電流をエミツタへバイパスす
るように、前記ゲート電極近傍と前記エミツタ電
極あるいはエミツタ層とを電気的に接続する電気
接続手段とを具備した半導体装置。1. A first conductive region having one conductivity type and being a semiconductor substrate, a second conductive region and a third conductive region of the opposite conductivity type formed on both main surfaces of this substrate, and a second conductive region. an emitter layer of one conductivity type formed in the
a gate electrode provided in a conductive region, an anode electrode provided in a third conductive region, an emitter electrode provided in the emitter layer, and a conductor formed between the gate electrode and the emitter layer. electrical connection means for electrically connecting the auxiliary emitter layer of the mold and the vicinity of the gate electrode and the emitter electrode or the emitter layer so as to bypass displacement current or leakage current generated in the vicinity of the gate electrode to the emitter; A semiconductor device equipped with.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13526579A JPS5660058A (en) | 1979-10-22 | 1979-10-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13526579A JPS5660058A (en) | 1979-10-22 | 1979-10-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5660058A JPS5660058A (en) | 1981-05-23 |
| JPS6356709B2 true JPS6356709B2 (en) | 1988-11-09 |
Family
ID=15147652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13526579A Granted JPS5660058A (en) | 1979-10-22 | 1979-10-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5660058A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011151063A (en) * | 2010-01-19 | 2011-08-04 | Sansha Electric Mfg Co Ltd | Thyristor |
| JP2014135510A (en) * | 2014-03-19 | 2014-07-24 | Sansha Electric Mfg Co Ltd | Thyristor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49104580A (en) * | 1973-01-08 | 1974-10-03 |
-
1979
- 1979-10-22 JP JP13526579A patent/JPS5660058A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49104580A (en) * | 1973-01-08 | 1974-10-03 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011151063A (en) * | 2010-01-19 | 2011-08-04 | Sansha Electric Mfg Co Ltd | Thyristor |
| JP2014135510A (en) * | 2014-03-19 | 2014-07-24 | Sansha Electric Mfg Co Ltd | Thyristor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5660058A (en) | 1981-05-23 |
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