JPS6355619U - - Google Patents
Info
- Publication number
- JPS6355619U JPS6355619U JP1986147508U JP14750886U JPS6355619U JP S6355619 U JPS6355619 U JP S6355619U JP 1986147508 U JP1986147508 U JP 1986147508U JP 14750886 U JP14750886 U JP 14750886U JP S6355619 U JPS6355619 U JP S6355619U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- bias
- avalanche photodiode
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Optical Communication System (AREA)
Description
第１図は本考案の実施例を示す回路構成図。第
２図は従来例回路構成図。第３図はＡＰＤバイア
ス回路の等価回路図。
１０１…バイアス回路出力端子、１０２…出力
可変形の高電圧発生回路、１０３…比較回路、１
０４…分圧回路、１０５…加算回路、１０６…制
御電圧入力端子、１０７…基準電圧入力端子。
FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a circuit configuration diagram of a conventional example. FIG. 3 is an equivalent circuit diagram of the APD bias circuit. 101...Bias circuit output terminal, 102...Variable output high voltage generation circuit, 103...Comparison circuit, 1
04... Voltage dividing circuit, 105... Adding circuit, 106... Control voltage input terminal, 107... Reference voltage input terminal.
Claims (1)
圧を供給する電圧制御形の直流高電圧発生回路を
備えた アバランシエホトダイオードのバイアス回路に
おいて、 前記直流高電圧発生回路の出力電圧を分圧する
分圧回路と、 この分圧回路の出力電圧を基準電圧と比較する
比較回路と、 この比較回路の誤差出力を前記直流高電圧発生
回路の制御電圧入力に加算する加算回路と を備えたことを特徴とするアバランシエホトダイ
オードのバイアス回路。[Scope of Claim for Utility Model Registration] In a bias circuit for an avalanche photodiode that is equipped with a voltage-controlled DC high voltage generation circuit that supplies a DC bias voltage to the avalanche photodiode, the output voltage of the DC high voltage generation circuit is divided into voltages. A voltage divider circuit, a comparison circuit that compares the output voltage of the voltage divider circuit with a reference voltage, and an addition circuit that adds the error output of the comparison circuit to the control voltage input of the DC high voltage generation circuit. The featured avalanche photodiode bias circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986147508U JPS6355619U (en) | 1986-09-25 | 1986-09-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986147508U JPS6355619U (en) | 1986-09-25 | 1986-09-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6355619U true JPS6355619U (en) | 1988-04-14 |
Family
ID=31060934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986147508U Pending JPS6355619U (en) | 1986-09-25 | 1986-09-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6355619U (en) |
-
1986
- 1986-09-25 JP JP1986147508U patent/JPS6355619U/ja active Pending