JPS635558A - Nonvolatile random access memory - Google Patents

Abstract

PURPOSE:To obtain an integrated circuit of high integration and large memory capacity by a method wherein recall action is made performable only by capacity difference according to existence of the channel of an EEPRON part. CONSTITUTION:A drain region 7 is provided according to an N-type diffusion layer on a P-type substrate 8, a floating gate 4 is provided on the P-type substrate 8 interposing an insulating film 100 between them, and moreover a control gate b is provided on the floating gate 4 interposing an insulating film 101 between them to construct an EEPROM 3. When recall is to be performed, a difference is provided to the capacitance value of capacity to be connected between nodes Q, Q according to existence of the channel 9 of the EEPROM part 3, and the recall condition of an SRAM is decided using the difference of the capacitance value thereof. Accordingly, the number of elements is reduced, the area of memory cells is reduced, the device is made suitable for high integration, and chip cost is also reduced.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides an SRAM and an E
Non-volatile RAM suitable for high integration consisting of EPROM
Regarding.

(Summary of the Invention) Generally, in nonvolatile RAM, reading the contents of EEPROM to SRAM is called recall.

The present invention provides EE when recalling nonvolatile RAM.
The recall operation is made possible by utilizing the capacitance difference between the presence and absence of a channel in the PROM section.

(Prior art) Conventionally, nonvolatile RAM recalls are as shown in Figure 2.
The SRAM (7) rA voltage VRC11 is lowered to the 1f "0" level, and then VRCll is gradually raised. At that time, if electrons are injected into the floating gate 4 and the EEPROM 3 is in a non-conducting state, the capacitor 5 is cut off from the node Q, and the additional capacitance of the node 0 becomes larger than that of the node Q. 1 is completely standing on the ground, node Q is “0”, node Q
are in a stable state at the "1" level, and in the end "1" is recalled.

Conversely, electrons are extracted from the floating gate 4, the floating gate 4 is positively charged, and εEPRO
If M is in interrogation state, capacitor 5 is connected to node Q, the additional capacitance of node Q is larger than that of node Q, and when VRCll is fully started up,
The node ◇ becomes stable at the "1#" level, and the node Q becomes stable at the "0" level, and eventually "0" is recalled.

(Problem to be solved by the invention) However, conventional non-volatile RAM is SRAM and EEPR.
Since a capacitor other than OM must be provided for each pit, the area of the memory cell becomes large, which not only makes it unsuitable for high integration but also increases chip cost.

SUMMARY OF THE INVENTION In order to solve these conventional drawbacks, it is an object of the present invention to provide a highly integrated circuit with a large memory capacity.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides an εEPROM
The recall operation can be performed only by the difference in capacity depending on the presence or absence of a channel.

(Function) The present invention sets the capacitance connected to the node Q, ◇ to εEPR
A difference is given to the capacitance value depending on the presence or absence of a channel in the OM section, and the recall state of the SRAM is determined using the difference in the capacitance 11E.

(Example) Below, an example of the present invention will be described in detail based on the drawings.

In FIG. 1, the gate of transistor 1 is connected to the word line 10, the drain and source are connected to the SRAM and the bottom pier 112, and the gate of transistor 2 is connected to the word line 10, the drain and source are connected to the SRAM and the bit line 112. 13, and the drain of εEPROM3 is connected to node Q. Also, VRCl 1 is SR
It is an AM power source.

In addition, FIGS. 3(a) and (b) show ε in FIG.
It is a cross-sectional view of the EPROM 3, in which a drain 7 is provided on a P-type substrate 8 by an N-type diffusion layer, and an insulating layer G11 is provided on the P-type substrate 8.
A floating gate 4 is provided through 0o, and further 7
The control gate 6 is provided on the zeroing gate 4 with an insulator 11101 interposed therebetween.

Next, its operation will be explained.

First, when performing a recall, the SRAM power supply voltage VRC
11 to the "O" level, then gradually increase the VR
We will launch Cll. At that time, as shown in FIG. 3(a), if the electrons in the floating gate 4 are removed and the floating gate 4 is in a positively charged state,
A channel 9 is formed on the substrate 8 under the floating gate 4, and the drain 7 and channel 9 are at the same potential.
A capacitance is formed between the 70-ring gate 4 and the channel 9. Therefore, node Q from node ◇
The additional capacitance of is larger, and when VRCll is fully started up, node Q is “0” and node d is “0”.
Each is in a stable state at the 1" level, and in the end, "0" will be recalled. Also, when performing the recall operation, in order to stabilize the potential of the control gate 6, the control gate 6 is connected to ground potential.

Also, as shown in Figure 3(b), when performing a recall,
If electrons are injected into the 70-ring gate 4, no channel will be formed and no capacitance will be formed. Therefore, the additional capacitance of node Q is larger than that of node Q, and when VRC is fully started up, node Q is in a stable state at "1" level and node Q is at "0" level, and eventually ,01″
will be recalled.

Therefore, as described above, the capacitance can be changed depending on whether electrons are injected into the focusing gate 4 or whether electrons are removed and the gate is positively charged, so that stable recall can be performed.

(Effects of the Invention) As explained above, the present invention does not require the additional storage required for each bit at the time of recall in conventional non-volatile RAM, so the number of elements is small and the area of the memory cell is reduced. It is small, suitable for high integration, and has the effect of reducing chip cost.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a non-volatile RAM according to the present invention, Figure 2 is a circuit diagram of a conventional non-volatile RAM in which a capacitor is connected to the source side of an EEPROM, and Figure 3 (a) is a circuit diagram of a non-volatile RAM according to the present invention. E is positively charged and a channel is formed.
A cross-sectional view of an EPROM, FIG. 3(b), shows an EPROM in which the floating gate is negatively charged and no channel is formed.
It is a sectional view of EPROM. 3...EEPROM 4...Floating gate

Claims (1)

[Claims] SRAM configured by MISFET and EEPRO
In the non-volatile RAM consisting of M, the EEPRO
When reading the contents of M to the SRAM, the contents of the EEPROM are read to the SRAM using a capacitance between the gate and drain of the EEPROM that changes depending on the presence or absence of a channel in the EEPROM section connected to the SRAM input. Non-volatile RAM.