JPS6355539U - - Google Patents
Info
- Publication number
- JPS6355539U JPS6355539U JP15002186U JP15002186U JPS6355539U JP S6355539 U JPS6355539 U JP S6355539U JP 15002186 U JP15002186 U JP 15002186U JP 15002186 U JP15002186 U JP 15002186U JP S6355539 U JPS6355539 U JP S6355539U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor device
- wiring
- lead frame
- die pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の半導体装置の一例を説明する
ための平面図であり、第２図は従来の半導体装置
の一例を説明するための平面図である。
１……半導体チツプ、２……ダイパツド、３…
…電極、４Ａ，４Ｂ……電源用配線、５……接地
用配線、６Ｄ，６ＳＡ，６ＳＢ……ボンデイング
パツド部、７Ｄ，７ＳＡ，７ＳＢ……ワイヤ、８
……ダイパツドサポートバー。
FIG. 1 is a plan view for explaining an example of a semiconductor device of the present invention, and FIG. 2 is a plan view for explaining an example of a conventional semiconductor device. 1...Semiconductor chip, 2...Die pad, 3...
...Electrode, 4A, 4B...Power supply wiring, 5...Grounding wiring, 6D, 6SA, 6SB...Bonding pad part, 7D, 7SA, 7SB...Wire, 8
...Diapad support bar.
Claims (1)
ンデイングされ、そのチツプには所定電位の配線
が施されている半導体装置において、 上記チツプの配線は複数に分割され、且つそれ
ぞれ上記ダイパツドと電気的に接続されているこ
とを特徴とする半導体装置。[Claims for Utility Model Registration] In a semiconductor device in which a chip is die-bonded to a die pad of a lead frame, and the chip is provided with wiring at a predetermined potential, the wiring of the chip is divided into a plurality of parts, and each wire is connected to the die pad of a lead frame. A semiconductor device characterized by being electrically connected to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15002186U JPS6355539U (en) | 1986-09-30 | 1986-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15002186U JPS6355539U (en) | 1986-09-30 | 1986-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6355539U true JPS6355539U (en) | 1988-04-14 |
Family
ID=31065772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15002186U Pending JPS6355539U (en) | 1986-09-30 | 1986-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6355539U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6077436A (en) * | 1983-10-04 | 1985-05-02 | Nec Corp | Semiconductor integrated circuit |
-
1986
- 1986-09-30 JP JP15002186U patent/JPS6355539U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6077436A (en) * | 1983-10-04 | 1985-05-02 | Nec Corp | Semiconductor integrated circuit |