JPS6355255B2 - - Google Patents
Info
- Publication number
- JPS6355255B2 JPS6355255B2 JP4002681A JP4002681A JPS6355255B2 JP S6355255 B2 JPS6355255 B2 JP S6355255B2 JP 4002681 A JP4002681 A JP 4002681A JP 4002681 A JP4002681 A JP 4002681A JP S6355255 B2 JPS6355255 B2 JP S6355255B2
- Authority
- JP
- Japan
- Prior art keywords
- intersymbol interference
- gain
- output
- amplifier
- equalizing amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 7
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
Description
【発明の詳細な説明】
本発明は、パルス通信方式において伝送路や等
化器等の偏差によつて生じる符号間干渉を補償す
る符号間干渉補償方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an intersymbol interference compensation method for compensating for intersymbol interference caused by deviations in transmission paths, equalizers, etc. in pulse communication systems.
従来、この種の符号間干渉を補償する技術とし
て第１図に示すようなトランスバーサルフイルタ
を用いたものが知られている。すなわち、入力信
号ａを１ビツト毎のタツプのついた遅延回路１に
加え、それぞれのタツプの出力をそれぞれ重み回
路２〜６に与え、この重み回路２〜６の出力を加
算して出力信号ｂを得るものである。この従来技
術では重み回路２〜６の重みをそれぞれ調整する
ことにより、符号間干渉を補償している。 Conventionally, a technique using a transversal filter as shown in FIG. 1 is known as a technique for compensating for this type of intersymbol interference. That is, input signal a is applied to delay circuit 1 with taps for each bit, the outputs of each tap are applied to weighting circuits 2 to 6, and the outputs of weighting circuits 2 to 6 are added to form output signal b. This is what you get. In this prior art, intersymbol interference is compensated for by adjusting the weights of weighting circuits 2 to 6, respectively.
しかし、この従来方式では必ず遅延回路と重み
回路が必要となり、このために装置が大形化、複
雑化、高価になる等の欠点を有する。 However, this conventional method necessarily requires a delay circuit and a weighting circuit, which has drawbacks such as making the device larger, more complicated, and more expensive.
本発明は、特開昭54―158805（特願昭53―
68121）をさらに改良したものである。 The present invention is disclosed in Japanese Patent Application Laid-Open No. 54-158805
68121) is further improved.
本発明はこの点を改良するもので遅延回路およ
び重み回路を必要とせず、装置を簡単化、低価格
化、小形化することができる符号間干渉補償方式
を提供することを目的とする。 The present invention improves on this point, and aims to provide an intersymbol interference compensation system that does not require a delay circuit or a weight circuit, and can simplify, reduce cost, and reduce the size of the device.
本発明は、パルス繰返し周波数に比して低周波
の利得を増加あるいは減少させることにより符号
間干渉を補償するものである。 The present invention compensates for intersymbol interference by increasing or decreasing the low frequency gain relative to the pulse repetition frequency.
本発明は、等化増幅器の出力波形の尖頭値を呈
する時点から、パルス周期T0後の符号間干渉を
検出する検出手段を設け、該検出手段による検出
出力により前記等化増幅器の低周波の利得を制御
して符号間干渉を補償することを特徴とする。 The present invention provides a detection means for detecting intersymbol interference after a pulse period T 0 from the time when the output waveform of the equalization amplifier exhibits a peak value, and detects the low frequency interference of the equalization amplifier by the detection output of the detection means. It is characterized by controlling the gain of the signal to compensate for intersymbol interference.
本発明の一実施例を図面に基づいて説明する。 An embodiment of the present invention will be described based on the drawings.
第２図は、本発明一実施例の要部ブロツク構成
図である。入力信号ａは等化増幅器８の入力に導
かれている。この等化増幅器８の出力が本装置の
出力信号ｂとされるとともに、その一部は分岐し
て符号間干渉検出器９に導かれている。この符号
間干渉検出器９の出力は前記等化増幅器８の制御
入力に導かれている。 FIG. 2 is a block diagram of essential parts of an embodiment of the present invention. Input signal a is led to the input of equalizing amplifier 8. The output of this equalizing amplifier 8 is used as the output signal b of this device, and a part of it is branched and guided to an intersymbol interference detector 9. The output of this intersymbol interference detector 9 is led to the control input of the equalization amplifier 8.
第３図は、等化増幅器８の周波数特性図であ
る。第３図で横軸は周波数（対数軸）、縦軸は増
幅利得dBをそれぞれ示す。この等化増幅器８は
周波数特性曲線に矢印で示すように低周波の利得
が可変に構成される。また、この等化増幅器８は
同軸ケーブルやペアケーブルのように高周波なる
ほど損失が増加する伝送路に対する等化増幅器で
あり、高域において利得が減少しているのは雑音
を小さくするためである。 FIG. 3 is a frequency characteristic diagram of the equalizing amplifier 8. In FIG. 3, the horizontal axis shows frequency (logarithmic axis), and the vertical axis shows amplification gain dB. This equalizing amplifier 8 is configured to have a variable low frequency gain as shown by the arrow in the frequency characteristic curve. Further, the equalizing amplifier 8 is an equalizing amplifier for a transmission line such as a coaxial cable or a pair cable where the loss increases as the frequency increases, and the reason why the gain decreases in the high frequency range is to reduce noise.
また、第４図は等化増幅器８の出力波形を示す
図である。第４図で横軸は尖頭値を零とした時間
軸、縦軸は出力レベルをそれぞれ示す。第４図で
Ａは等化が理想的に行われた場合の出力波形、Ｂ
は低周波における利得を増加した場合の出力波
形、Ｃは低周波における利得を減少させた場合の
出力波形をそれぞれ示す。 Further, FIG. 4 is a diagram showing the output waveform of the equalization amplifier 8. In FIG. 4, the horizontal axis shows the time axis with the peak value being zero, and the vertical axis shows the output level. In Figure 4, A is the output waveform when equalization is ideally performed, and B is the output waveform when equalization is ideally performed.
C shows the output waveform when the gain at low frequencies is increased, and C shows the output waveform when the gain at low frequencies is decreased.
このような回路構成で、本発明の特徴ある動作
を説明する。入力信号ａは等化増幅器８で等化さ
れ、その出力信号ｂの出力波形は第４図に示すよ
うな波形となる。このときに、符号間干渉検出器
９は出力波形の尖頭値が得られる時間（第４図で
は０の時刻）からT0後の符号間干渉を検出する。
これにより、T0後の符号波形が第４図Ｂのよう
に＋のときには利得を減少するように、第４図Ｃ
のように−のときには利得を増加させるように符
号間干渉検出器９から利得制御信号が等化増幅器
８に送出される。 The characteristic operation of the present invention will be explained using such a circuit configuration. The input signal a is equalized by the equalizing amplifier 8, and the output signal b thereof has a waveform as shown in FIG. At this time, the intersymbol interference detector 9 detects intersymbol interference after T 0 from the time when the peak value of the output waveform is obtained (time 0 in FIG. 4).
As a result, when the code waveform after T 0 is + as shown in FIG. 4B, the gain is decreased as shown in FIG. 4C.
When the signal is -, as in the case of -, a gain control signal is sent from the intersymbol interference detector 9 to the equalization amplifier 8 to increase the gain.
等化増幅器８はこの利得制御信号により、パル
ス繰返し周波数
F0＝１／T0
に比して低周波の利得を増加あるいは減少させ、
第４図Ａに示すような理想的な等化信号を出力信
号ｂとする。 The equalization amplifier 8 uses this gain control signal to increase or decrease the low frequency gain compared to the pulse repetition frequency F 0 =1/T 0 ,
An ideal equalized signal as shown in FIG. 4A is assumed to be the output signal b.
以上説明したように、本発明によれば、等化増
幅器の出力波形の尖頭値を呈する時点からT0後
の符号間干渉を検出し、その検出出力により等化
増幅器の低周波の利得を理想的な等化が行われる
よう制御することとした。 As explained above, according to the present invention, intersymbol interference is detected after T 0 from the point when the output waveform of the equalizing amplifier exhibits a peak value, and the low frequency gain of the equalizing amplifier is determined by the detected output. We decided to control so that ideal equalization was performed.
したがつて、符号間干渉を正確に補償すること
ができる。しかも、このための装置は従来のよう
なトランスバーサルフイルタを用いるものではな
く、遅延回路あるいは重み回路を必要とせず、装
置の簡単化、小形化、低価格化を図ることができ
る等の効果を有する。 Therefore, it is possible to accurately compensate for intersymbol interference. Moreover, the device for this purpose does not use a transversal filter as in the past, and does not require a delay circuit or a weighting circuit, making it possible to simplify the device, make it smaller, and lower the cost. have
第１図は従来例の要部ブロツク構成図。第２図
は本発明一実施例の要部ブロツク構成図。第３図
は上記実施例の等化増幅器の周波数特性図。第４
図は上記実施例の等化増幅器の出力波形図。
１……遅延回路、２〜６……重み回路、８……
等化増幅器、９……符号間干渉検出器。
FIG. 1 is a block diagram of the main parts of a conventional example. FIG. 2 is a block diagram of essential parts of an embodiment of the present invention. FIG. 3 is a frequency characteristic diagram of the equalizing amplifier of the above embodiment. Fourth
The figure is an output waveform diagram of the equalizing amplifier of the above embodiment. 1...Delay circuit, 2-6...Weight circuit, 8...
Equalization amplifier, 9... Intersymbol interference detector.
Claims (1)
から、パルス周期T0後の符号間干渉を検出し、
その検出出力に応じて前記等化増幅器の低周波の
利得を制御して符号間干渉を補償することを特徴
とする符号間干渉補償方式。1 Detect the intersymbol interference after the pulse period T 0 from the point when the output waveform of the equalizing amplifier reaches its peak value,
An inter-symbol interference compensation method, characterized in that inter-symbol interference is compensated for by controlling the low-frequency gain of the equalizing amplifier according to the detected output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4002681A JPS57154950A (en) | 1981-03-19 | 1981-03-19 | Compensating system for inter-code interference |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4002681A JPS57154950A (en) | 1981-03-19 | 1981-03-19 | Compensating system for inter-code interference |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57154950A JPS57154950A (en) | 1982-09-24 |
| JPS6355255B2 true JPS6355255B2 (en) | 1988-11-01 |
Family
ID=12569384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4002681A Granted JPS57154950A (en) | 1981-03-19 | 1981-03-19 | Compensating system for inter-code interference |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57154950A (en) |
-
1981
- 1981-03-19 JP JP4002681A patent/JPS57154950A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57154950A (en) | 1982-09-24 |
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