JPS6353649A - Interrupt control system - Google Patents

Abstract

PURPOSE:To use an interrupt vector without changing an interrupt vector table by reading the accommodating address of an interruption starting command, discriminating an interruption factor and determining the starting address of an interruption processing routine from the second table. CONSTITUTION:Due to the occurrence of an interruption, first, the contents of an A+v(n) address equivalent to a vector number (n) of an interrupt vector table 31 of a system area 3 are fetched and a jumped to an actual address B+r(n). Next, the instruction code of the address is checked and when it is not effective, the interruption of an exception processing occurs. Thus, from the address of a stack area 5 pointed by a stack pointer 1-1, an accommodating address [B+r(n)] of a non loaded instruction 33 is taken out and based on the address, (n) is obtained. Next, based on a head address C and a function (v) of a user vector table 40, a C+v(n) address is obtained and the contents R(n) are read. Next, the pointer 1-1 is corrected, jumped to an R(n) address and the interruption processing of an interruption factor (n) is executed. Thus, the succeeding interruption processing is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt control method in which, when an interrupt occurs, the start address of the interrupt routine is determined by searching an interrupt vector table.

[Prior Art] Conventionally, an interrupt vector table, which includes interrupt vectors at the time of reset, is generally composed of a ROM, and is managed by an operating system (OS). Therefore, in order for a user task under O8 management to use a vector open to the user, the target address must be set in a predetermined part of the vector table in advance. However, the contents of the vector table are in ROM
Once set, it cannot be changed while the system is running, so normally a jump table is provided in RAM, the address of the vector table is set in this jump table, and the actual exception is stored in this table. A method used was to set an instruction to jump to a processing routine. However, this method requires a troublesome operation in that the address of the jump table must be set in advance in the interrupt vector table on the ROM managed by the O3.

[Problems to be Solved by the Invention] The present invention has been made in view of the above conventional example, and provides an interrupt control method that can utilize interrupt vectors available to users without changing the interrupt vector table managed by O3. The purpose is to provide

Means for Solving Problem E] To achieve the above object, the interrupt control system of the present invention has the following configuration. That is, the interrupt control method branches to an interrupt processing routine corresponding to an interrupt factor based on an interrupt vector table in a system area, and includes a first table that is addressed by the interrupt vector table and stores an interrupt activation command; , a determining means for determining the cause of the interrupt based on the address where the interrupt starting command is stored, and a start address of the interrupt processing routine based on the determination result of the determining means when an interrupt is generated by the interrupt starting command; and a second table for instructing.

[Operation] In the above configuration, if an interrupt activation command is stored in the first table addressed by the interrupt vector table, an interrupt by the interrupt activation command occurs at the time of an interrupt. As a result, the address where the interrupt activation command is stored is read, the interrupt cause is determined from the address, and the start address of the interrupt processing routine is determined based on the second table based on the interrupt cause.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of Memory Configuration (FIG. 1)] FIG. 1 is a diagram showing a memory map of a system according to an embodiment of the present invention.

In the figure, 1 is a CPU such as a microprocessor, 2 is a memory 8 that stores the OS of the CPUI, a stack area 5, and user application programs, etc.
It is composed of M, RA, and M. 3 is a system area, which is an OS program section 30 composed of ROM.
, an interrupt vector table 31 managed by O8, and a reference table 32 for referencing the user vector table 40 of the user area 4. Reference numeral 4 denotes a user area normally made up of RAM, which is open to the user and stores various application programs and a vector table 40.
Contains etc.

Note that the start address of the interrupt vector table 31 is 'A'.
, the start address of the reference table 32 is "B"°, the start address of the user vector table 40 is C°, and O3
The start address of the user vector table 40 is °゛CC
It is assumed that the user is aware that the

[Operation explanation (Fig. 1, Fig. 2 (A), (B)) Fig. 2 (
A) and (B) are flowcharts of exception handling executed by O3. The operation of this embodiment will be explained below based on this flowchart.

The operation in FIG. 2(A) is based on the vector n that is open to the user.
The process starts when an exception occurs and an interrupt is generated. First, in step S1, A corresponding to vector number "n" in the system area 30 interrupt vector table 31 is
+v (n) Fetch the contents of address. Step S2
Then, the real address B+ written at address A+V (n)
r Jump to address (n). Here, v and r are expressed as functions with vector number "n" as a variable, and if memory 2 is configured in byte units and each vector table is configured in 2 bytes, r(n) = 2n. Alternatively, v (n) = 2n, and if it is composed of 3 bytes, then r (n), v (n,) = 3 n.

In step S3, after jumping to address B+r(n), the instruction code at address B+r(n) is fetched for execution, and the process proceeds to step S4. In step S4, the instruction code at address B+r(n) fetched in step S3 is checked to see if it is a valid instruction code.

If the instruction code is valid, proceed to step S5 and select 13+r.
(n) Execute the instruction at address and proceed to the interrupt processing routine.

On the other hand, if it is determined in step S4 that the instruction code at address B10r(n) is not valid, the process proceeds to step S6 and an interrupt for exception handling is generated. In this embodiment, since the unimplemented instruction 33 is stored at address B+r(n), an exception handling interrupt occurs, and the process moves to step S6. Note that this unimplemented instruction 3
3 is an instruction code that generates an interrupt that can be distinguished from other exception handling interrupts such as illegal instructions.

FIG. 2(B) is a flowchart of the exception handling interrupt routine by the unimplemented instruction 33 in step S6.

Due to the occurrence of an interrupt during the exception handling in step S6, the address B+r (n) is bushed in the stack area 5 as a return address, so in step S7, the unimplemented Address where instruction 33 was stored (B+r (n))
Take out. O8 knows the start address "B" of the reference table 32 in step S8, and uses the function r (n)
Since B+r (n) is also predetermined, n is determined based on the address B+r (n). Next, in step S9, C+V
(n) Find the address.

In step S10, C+v of the user vector table 40
(n) Read the contents R(n) of address. Step S11
Now, since exception handling has occurred twice in total, stack pointer 1-1 is corrected. Then, in step S12, R(n)
Jump to address and perform interrupt processing for interrupt cause "n". As a result, when jumping to address R(n),
The interrupt processing from step S12 onward is executed as if the unimplemented instruction exception processing at step S6 had not occurred.

As described above, according to this embodiment, when the exception handling "n" open to the user occurs, the target processing routine can be activated. There is no need for the user to rewrite the contents of the interrupt vector table 31 and reference table 32 under O8 management, and the user can manage the user-specific vector table 40 independently of O3.

[Effects of the Invention] As described above, according to the present invention, there is an effect that the effective address for interrupt processing can be changed without changing the interrupt vector table under OS management.

[Brief explanation of drawings]

Figure 1 is a diagram showing the memory It is a flowchart. In the figure, ]... CPU, 1-1... stack pointer, 2... memory, 3... system area, 4... user area, 5... stack area, 30... O3 ，
31... Interrupt vector table, 32... Reference table, 33... Unimplemented instruction, 40... User vector table. Patent applicant: Canon Corporation Figure 1 Figure 2 (A)

Claims (1)

[Claims] An interrupt control method that branches to an interrupt processing routine corresponding to an interrupt factor based on an interrupt vector table in a system area, the first table being addressed by the interrupt vector table and storing an interrupt activation command; At the time of an interrupt caused by an interrupt start command, a determination means for determining the cause of the interrupt based on the address where the interrupt start command is stored, and a start address of the interrupt processing routine based on the determination result of the determination means. and a second table for controlling an interrupt.