JPS6352471B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a MOS field effect transistor (MOS field effect transistor).
The present invention relates to a method for forming a thin film resistor that is optimal for use as a load resistor for -FET).

Conventionally, in static RAM using N-channel E/R MOS method, depletion MOS
It is necessary to reduce the area of the load and the current of the D-MOS.

One known method for this purpose is to replace the MOS load with a thin film resistive load. In this case, a high-resistivity polysilicon film (resistivity is approximately 10 ⁶
The resistivity is controlled by implanting boron B ⁺ ions into the resistivity (Ωcm). The inventor of the present invention tried to control the resistivity of the polysilicon film by implanting B ⁺ ions, and the obtained resistivity was as shown in ^Figure 1.
It was clarified that it changes depending on the dose. That is, the resistivity of the polysilicon film exhibits significant dose dependence in the vicinity of 1 to 10 ⁵ Ω·cm, making it extremely difficult to control the resistivity with high precision. When using a polysilicon film as a load resistor, its resistivity generally needs to be controlled to around 10 ² Ω・cm, but conventional ones have a resistivity of around 10 ² Ω・cm.
If the B ⁺ dose changes even slightly, the resistivity changes rapidly, making it extremely difficult to set the resistivity.
Furthermore, the uniformity is also poor.

Also, between the gate and source of the MOS-FET, a pulse voltage applied from the outside is clipped to prevent the gate oxide film from being destroyed.
A protection diode using a P-N junction is generally connected. On the other hand, when increasing the output of MOS-FETs, the gate-source capacitance increases as the gate peripheral increases, and the gate oxide film thickness must be made as thick as the characteristics allow (relative to Gm). Therefore, it is possible to avoid destruction even at a considerably large voltage without connecting a protection diode.
However, in response to repeated pulsed voltages, the amount accumulated in the gate insulating film is integrated, eventually leading to breakdown. On the other hand, gate −
By connecting a resistor with an appropriate time constant in parallel to the gate-source capacitance between the sources, it is possible to constantly release the accumulated amount through the resistor and avoid destruction. . but,
If the resistance value of this protective resistor becomes larger than the set value due to process variations, the time constant becomes large and the effect of the protective resistor is weakened. Furthermore, if the resistance value becomes smaller than the set value, there is no problem in terms of the time constant, but the gate leakage current increases, which poses a problem during use.

The present invention has been made to correct the above-mentioned problems, and includes a step of forming a silicon thin film containing impurities at a substantially saturation concentration and containing oxygen, and a step of heat-treating the silicon thin film. The present invention relates to a method for forming a thin film resistor in which the resistivity of the silicon thin film is controlled by controlling the temperature when oxygen is contained in the silicon thin film. According to the present invention configured in this way, the resistivity of a thin film resistor made of a silicon thin film can be controlled with no variation, excellent uniformity, and high precision. Also, for this purpose,
It is possible to provide an excellent thin film resistor for semiconductor devices such as MOS-FETs.

Examples of the present invention will be described below with reference to FIGS. 2 to 16.

2 to 14 show the present invention in E/R MOS
This figure shows a first example applied to.

First, the structure of the MOS-IC according to this embodiment will be explained with reference to FIGS. 2 and 3.

As shown in FIG. 2, the P-type semiconductor substrate 1 has N
A type source region 2 and a drain region 3 are formed, and a thin film resistor 5 serving as a load resistance of this MOS-FET is provided at a predetermined position on the SiO ₂ film 4 on the surface of the substrate 1.
However, it is provided. In addition, 6 is a source electrode, 7
8 is a drain electrode, 8 is a gate electrode, and 9 is a power supply side electrode of the thin film resistor 5. Therefore, the thin film resistor 5 is connected between the power supply and the drain region 3 and acts as a load resistance of the FET. Figure 3 shows the MOS-
FIG. 2 is an equivalent circuit diagram of a static RAM incorporating an FET.

Since the thin film resistor 5 is used as a load resistor,
The resistivity must be controlled with high precision and good uniformity, and is generally 10 to 500 Ω·cm (particularly about 10 ² Ω·cm). Thin film resistor, that is, this resistor film 5
4, a vapor phase growth apparatus shown in FIG. 4 is used. The apparatus shown in FIG. 4 is called a horizontal reactor, in which a silicon wafer (not shown) that has already been subjected to diffusion processing is held on a susceptor 21 in the reactor 20, and a growth temperature of 640°C is set using an external infrared lamp 22. A predetermined mixed gas 25 is introduced through the valve 23 and the flow meter 24 while heating. This mixed gas consists of monosilane (SiH ₄ ), nitrous oxide (N ₂ O), and phosphine (PH ₃ ), and is passed through the furnace 20 while flowing N ₂ as a carrier gas at a constant flow rate of 25/mm.
onto the wafer inside. As a result, _SiH4 and
PH ₃ is easily thermally decomposed and polysilicon uniformly containing P grows on the wafer, but at the same time N ₂ O
The oxidation reaction proceeds appropriately and oxygen is doped uniformly into polysilicon.

In this pyrolysis reaction, the flow rate of SiH ₄ was reduced to 30
cc/min, PH ₃ flow rate 0.198cc/min (330ppm×
600c.c./min). What is important here is that the concentration of P doped into polysilicon is near _the saturation point (solid solubility limit).
This means that the amount of On the other hand, the flow rate of N ₂ O was varied in five ways: 0, 28, 48, 68, and 88 c.c./min to grow polysilicon layers made of oxygen-phosphorus-polysilicon with different compositions. As a result of compositional analysis using an X-ray microanalyzer, it was found that the resistor film made of this polysilicon layer had the composition shown in FIG. That is, the oxygen concentration (at%: percentage of the number of atoms) increases in proportion to the flow rate of N ₂ O, and conversely, the phosphorus concentration gradually decreases. In this case, the desirable concentration range is 34~
90at%, oxygen 10 to 50at%, phosphorus 3at% or a value close to this.

Since the resistivity of the resistor film described above is extremely high as it is and cannot be controlled within the range of 10 to 500 Ω·cm, it is essential to perform annealing to activate the impurities next. Therefore, 900
℃, 1000℃ and 1100℃ for 60 minutes each (N ₂
(Middle) After annealing, the results shown in FIG. 6 are obtained. According to these results, the _resistivity of the resistor film varies depending on the annealing temperature, but it increases in proportion to the flow rate of N ₂ O, and if other conditions are held constant, the resistivity of the resistor film varies depending on the annealing temperature. It can be seen that it can be precisely controlled.

That is, as described above, by increasing the flow rate of N ₂ O while keeping the flow rate of PH ₃ constant, the resistivity increases in accordance with the amount of oxygen doping and can be set to a predetermined value. In this case, the flow rate of PH ₃ is 0.198cc/min.
Since the amount of phosphorus in the resistor film is 10 ²⁰ cm ^-3
As above, it is doped to near the saturation point and has a concentration close to the maximum saturation amount (solid solubility limit). It is considered that phosphorus cannot be doped to a concentration of 10 ²¹ cm ^-3 or more. As is clear from Figure 1, the reason why the P concentration is so high is that the change in resistivity when no oxygen is doped is 10 ¹⁷ to ^{10 19} cm ^-3
This shows that even if the P concentration changes, the resistivity does not fluctuate much and remains stable. Therefore, if oxygen is doped with N ₂ O in this state, the resistance of the resistor film can be made to a desired value only by the flow rate of N ₂ O without being affected much by changes in the P concentration.

Figure 7 shows that the SiH ₄ flow rate is constant at 30 c.c./min, the N ₂ flow rate is constant at 25/min, and the N ₂ O flow rate is 28 c.c./min.
and the resistivity when the PH ₃ flow rate was fixed at 48 c.c./min, a polysilicon layer was formed at a growth temperature of 640°C, and then annealed at 1000°C for 1 hour (in N ₂ ). Changes are shown. According to this, it can be seen that the resistivity can be controlled by the flow rate of PH ₃ , but as mentioned above, this PH ₃
Since the amount of P doping is very large depending on the flow rate, when compared with Figure 1, even if the PH ₃ flow rate (i.e. P concentration) changes, the change in specific resistance is significantly small, and it is 10 to 500 Ωcm. It is extremely easy to control the specific resistance to .

Figure 8 shows the relationship between the N ₂ O flow rate and resistivity according to another example, and shows the growth temperature of the resistor film (640°C, 660°C).
℃, 680℃), and it can be seen that the resistivity changes depending on the PH ₃ flow rate. However, the annealing conditions are 1000°C and 1 hour.

Figure 9 shows that the SiH ₄ flow rate is constant at 30 c.c./min, the N ₂ flow rate is constant at 25/min, and the PH ₃ flow rate is 0.124, 0.31,
and 0.527cc/min, _N2O flow rate 40, 50 and 60
It is shown that the resistivity changes depending on the annealing time when a polysilicon layer is formed at a growth temperature of 640° C. and then annealed at 1000° C. with the growth temperature fixed at cc/min. According to this, the resistivity decreases depending on the annealing time, but by controlling the annealing time, it can still be reduced to 10 to 500 Ωcm.
It is possible to accurately obtain the resistivity of Also the 10th
The figure shows No. 9 except that the annealing temperature is 1100℃.
It is shown that when a polysilicon layer is grown and annealed under the same conditions as in the figure, the resistivity changes depending on the annealing time, and it can be seen that the same change as in FIG. 9 is shown.

Figure 11 shows the results when polysilicon layers were grown at 600, 640 and 670°C with a constant SiH ₄ flow rate of 30 c.c./min and PH ₃ flow rate of 0.198 cc/min and annealed at 1000°C. The change in resistivity with annealing time is shown. According to this, it can be seen that as the growth temperature increases, the decomposition of N ₂ O progresses and the resistivity increases. Figure 12 shows the annealing temperature.
Similar results are shown when treated under the same conditions as described in Figure 11 except for the temperature of 1100°C.
It can be seen that due to the high annealing temperature, the doped impurities are activated and the resistivity becomes smaller.

As described above, according to ^{the present} example, N _{2 is} By controlling the flow rate of O, controlling the temperature of vapor phase growth, and further controlling the temperature and time of annealing, it is possible to adjust the resistivity of the resistor film to a desired value within a predetermined range. can. The annealing temperature is preferably 900 to 1200℃, and 950 to 1100℃.
℃ is practical. That is, the annealing temperature is
This is because if the temperature is less than 900°C, activation will be insufficient and the resistivity will not decrease, and if it exceeds 1200°C, the resistivity will decrease too much or other regions (for example, the diffusion region) will be adversely affected. Also, the annealing time is 10
~200 minutes is desirable for the same reasons as mentioned above regarding the annealing temperature. Further, the vapor phase growth temperature is preferably 580 to 750°C, but if it is too low, the resistivity will drop too much or the decomposition will be insufficient, and if it is too high, the resistivity will rise too much.

Note that the silicon concentration in the resistor film obtained in this example is preferably 34 to 90 at%, the oxygen concentration is 10 to 50 at%, and the phosphorus concentration is 3 at% or a value close to these. That is, if oxygen is less than 10 at%, it is difficult to increase the resistivity to a desired range, and if it exceeds 50 at%, it is too much and the resistivity becomes too high. Note that silicon is never doped with more than 3 at% phosphorus.

Further, the resistor film according to this embodiment may be formed on a wafer as described above and then etched into a predetermined shape to form the resistor film 5 as a load resistor as shown in FIG. Among these resistor films, for example, one with ρ = 100 Ωcm can easily make ohmic contact with metal, and is also easy to process because it is made of polysilicon material, and SiO ₂
The adhesion strength is also good.

The thin film resistance obtained by the method described above is
When used in a static RAM using the E/R MOS method shown in the figure, and manufactured as a prototype with an effective channel length of 2μ and a mask alignment accuracy of 1μ, the E/R is 21μ x 30μ (= 630μ ² ) per memory cell.
MOS type memory - 25μ x 36μ per cell (=
This is 70% compared to 900μ ² ), improving the degree of integration.
Furthermore, since the power consumption of the thin film resistor 5 according to this embodiment can easily be 50MΩ or more, the standby power consumption per cell is 5×10 ^-6 W (5V power supply).
It can be: Furthermore, since the thin film resistor 5 is provided on the substrate 1, there is an advantage that there is no substrate bias effect.

In addition, the load resistance value R _L due to the thin film resistor 5 is the resistivity of the resistor ρ = 200 Ω cm, the thickness of the thin film t
= 2000 Å, and the ratio of the width W to the length L of the resistor (rectangular) W/L = 1/5, it can be expressed as follows.

R _L =ρ/t=W/L=200/2×10 ³ ×10 ^-8 /1/5 = 100×10 ⁵ ×5=50×10 ⁶ Ω=50MΩ Note that silicon supply sources other than SiH ₄ can also be used. Also, as an oxygen source
In addition to N ₂ O, NO, NO ₂ , H ₂ O, O ₂ and the like can also be used, but NO ₂ is a desirable compound because it has appropriate reactivity at a growth temperature of around 640°C. The impurity source is not limited to PH ₃ , but also PF ₅ , AsH ₃ ,
Other compounds for supplying N-type impurities such as AsCl ₃ , SbH ₃ , SbCl _{5 ,} etc., and compounds for supplying P-type impurities such as BCl ₃ , BBr ₃ , B ₂ H ₆ etc. can also be used.

An example using B ₂ H ₆ will be described below. The reaction operation itself is the same as that described above, and SiH ₄
A mixed gas of B ₂ H ₆ and N ₂ O is introduced into the reaction system using N ₂ gas (carrier gas). As a result, a resistor film made of polysilicon containing a predetermined amount of oxygen and B can be grown on the wafer, and then annealed to form a resistor film having a desired resistivity.

Figure 13 also shows the SiH ₄ flow rate of 300c.c./min.
The polysilicon layer was grown at 660°C by keeping the N ₂ O flow rate constant at 62 c.c./min and varying the B ₂ H ₆ flow rate.
Results are shown for annealing at 1000°C for 30 minutes, 60 minutes, and 120 minutes. According to this, it can be seen that a desired resistivity can be easily obtained depending on the B ₂ H ₆ flow rate.

As the reactor to be used, the furnace shown in FIG. 14 can be used, which can accommodate a larger number of wafers than the furnace shown in FIG. 4 and provides better uniformity in film thickness and film quality. This reactor is of a reduced pressure type, and the reaction mixture gas 25 is introduced from one end of the furnace 30 in the same manner as shown in FIG. It is heated to a predetermined temperature by the heater 32 around it. In the furnace 30, a large number of wafers 33 are vertically arranged and set on a boat 31.

FIGS. 15 and 16 show another embodiment, in which the above-mentioned thin film resistor is used as a gate protection resistor of a MOS-FET.

That is, the N type semiconductor substrate 1 has an N ⁺
A type source region 2 and a P type semiconductor region 19 that determines the effective channel length are formed. Further, an N ⁺ type semiconductor region 10 is provided on the back surface of the substrate 1, and a drain electrode is taken out. On the other hand, a gate electrode 8 is provided on the surface of the substrate 1 via a SiO ₂ film 4.
and a source electrode 6 are provided, and the above-mentioned thin film resistor 5 as a gate protection resistor is formed on the SiO ₂ film 4 between these two electrodes.

According to such a MOS-FET, a thin film resistor of 5
This effectively prevents the gate from being destroyed by the pulsed voltage, but since the resistance value of the resistor 5 is well controlled and reproducible as described above,
This makes it ideal as a gate protection resistor. In addition,
If the resistance value of the resistor 5 is sufficiently high, the resistor 5 may be formed on the entire surface of the SiO ₂ film 4 before or after the formation of the electrodes, so that the resistor 5 also has a passivation function.

In the example described above, all of the reactants used to form the polysilicon layer were supplied in a gaseous state, but these reactants were initially supplied as a liquid or solid, and then supplied so that they became a gaseous state on the wafer. It's okay. Alternatively, for example, polysilicon containing a predetermined amount of oxygen is first grown on a wafer by supplying SiH ₄ and N ₂ O, and then this polysilicon is doped with impurities at a concentration near the saturation point. good. Alternatively, for example, SiH ₄ and PH ₃ may be first supplied to grow polysilicon containing impurities at a high concentration of 3 at % or close to this, and then this polysilicon may be doped with a predetermined amount of oxygen. In either case, it is possible to obtain a resistor film having a desired resistivity by annealing, but in the former case, impurities such as P can be uniformly pre-diffused from the surface of the polysilicon layer, or Thermal diffusion may be performed by a doped oxide method. Even in the latter case, a predetermined amount of oxygen can be doped by oxygen diffusion from the surface.

As described above, the present invention provides a method of forming a silicon thin film containing impurities at a substantially saturated concentration and containing oxygen, and heat-treating the silicon thin film to form a thin film resistor. By controlling the temperature during the inclusion, the resistivity of the silicon thin film is controlled. Therefore, according to the present invention, the oxygen content of the silicon thin film can be changed by changing the temperature separately from the oxygen supply amount, so it is possible to increase the number of parameters for controlling the resistivity. Therefore, the resistivity of the thin film resistor can be controlled with high precision, and can be made to have excellent uniformity without variation.

In addition, since the thin film resistor is formed thinly, there is no substrate bias effect even when the thin film resistor is formed on a substrate, and the degree of integration can be improved by multilayering, and the resistance value is selected to be relatively large. This can reduce power consumption. Therefore,
Coupled with the ability to control the resistivity of a thin film resistor with good uniformity and high precision, it is possible to provide a thin film resistor with high characteristics as a load resistor, gate protection resistor, etc. of a MOS-FET.

[Brief explanation of the drawing]

FIG. 1 shows a conventional example, and is a graph showing a change in resistivity when a thin film resistor is doped with B. 2 to 16 show examples of the present invention, in which FIG. 2 is a cross-sectional view of a MOS-FET using a thin film resistor as a load resistance, and FIG. 3 is a cross-sectional view of the MOS-FET shown in FIG. Stats incorporating
The equivalent circuit diagram of RAM, Fig. 4 is a schematic cross-sectional view of the vapor phase growth apparatus, and Fig. 5 shows the concentration of Si, O, and P in the resistor film depending on the N ₂ O flow rate when the PH ₃ flow rate is constant. Figure 6 is a graph showing the changes in resistivity at each annealing temperature when the N ₂ O flow rate is changed when the PH ₃ flow rate is constant.
The figure is a graph showing the resistivity change at each N ₂ O flow rate when the PH ₃ flow rate is changed. Figure 8 is the resistivity at each growth temperature and PH ₃ flow rate when the N ₂ O flow rate is changed. Graph showing changes in resistivity. Figure 9 is a graph showing resistivity changes at various N ₂ O and PH ₃ flow rates when annealing time at 1000°C is changed. Figure 10 is at 1100°C.
Graph showing the resistivity change at each N ₂ O and PH ₃ flow rate when the annealing time is changed, No. 11
The figure is a graph showing the resistivity change at each growth temperature when the annealing time at 1000℃ is changed.
The figure is a graph showing the resistivity change at each growth temperature when the annealing time at 1100℃ is changed.
The figure is a graph showing resistivity changes depending on annealing conditions when the B ₂ H ₆ flow rate is changed, Figure 14 is a schematic cross-sectional view of another vapor phase growth apparatus, and Figure 15 is another example of a thin film resistor in MOS. -A cross-sectional view when used as a FET gate protection resistor, Figure 16 is the 15th
FIG. 2 is an equivalent circuit diagram of FIG. In addition, in the symbols used in the drawings, 2
... Source region, 3, 10 ... Drain region, 4
. . . SiO ₂ film, 5 . . . thin film resistor, 8 . . . gate electrode.

Claims (1)

[Scope of Claims] 1. A step of forming a silicon thin film containing impurities at a substantially saturation concentration and containing oxygen; and a step of heat-treating the silicon thin film; . A method for forming a thin film resistor, characterized in that the resistivity of the silicon thin film is controlled by controlling temperature.