JPS6352254A - Memory device - Google Patents

Abstract

PURPOSE:To avoid delay of an output signal at the charge side despite an open type of a data output terminal by using a precharge means that charges previously a data bus before output of data in a memory read mode. CONSTITUTION:A data bus control signal DBC is set at 0 together with a column address strobe signal CAS set at 1, a write enable signal WE set at 0 and an output enable signal OE set at 0 respectively. Thus a signal PCG is set at 1 and an AND gate AN1 delivers 1 to supply it to the gate of a field effect transistor TR2. Then the TR2 is turned on and charging action is started to a data bus IOi via a resistance R1 and the TR2. This charging action is carried out quickly since a time constant obtained from the R1 and the stray capacity of a data bus is small. When the charging action is through, the signal OE is set at 1 and the read-out data are delivered onto the bus IOi.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a memory device that can read stored data at high speed and reliably.

``Prior Art'' Memory used for image display tends to become faster and larger in capacity in response to demands for multicolor display and high resolution display. The capacity of the frame buffer, which stores image data for image display, is proportional to the size and resolution of the display area, as well as the number of display screens (for example, when multiple screens are prepared in advance) and the number of display colors. increases accordingly.

For example, when displaying 16 colors, 4 bits are required as a color code, so four frame memories FMO to FM3 are required as frame buffers, as shown in FIG. In this case, each frame memory FMO~F
Data surrounded by a broken line at the same pit position of M3 (the direction of this broken line is hereinafter referred to as the pixel direction) corresponds to the I dot on the display surface. When displaying an image, the data in the pixel direction of each frame memory FMO to FM3 is sequentially read out as the display surface is scanned, thereby making it possible to display multiple colors.

In addition, in response to higher image quality, frame memory F
Generally, MO to FM3 are configured with dual port memories, and pixel data is read out synchronously from serial data output terminals on each side. In the case shown in FIG. 6, the access direction when accessing in word units is hereinafter referred to as the word direction (indicated by a dashed-dotted arrow in the figure).

"Problems to be Solved by the Invention" As in the case described above, when multiple frame memories are connected in parallel as frame buffers, the same data bus is connected to the output end of the same bit number, so the data The total stray capacitance of the bus increases. In this case, if the data output buffer of each memory is an open type (oven train, open collector, etc.), the time delay when the data bus changes from the "0" level to the "L" level is the sum of the above total stray capacitance and the data output buffer. It is determined by the time constant determined by the value of the pull-up resistor of the bus.The value of the pull-up resistor is usually set to a large value in order to reduce r'fM cost power. If the stray capacitance is large, the time constant becomes extremely large, causing a problem that the delay time when outputting the "L" signal becomes extremely long. Note that depending on how the logic is configured, the signal may not look like a "0" signal. There is also a case where the signal is charged to the negative side as a 1'' signal level, which is the opposite of the above, but the problem is the same.

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a memory device in which an output signal on the charge side is not delayed even if the data output terminal is of an open type.

"Means for Solving the Problems" In order to solve the above problems, the present invention connects each output end of a plurality of memory units whose output ends are open type to a data bus, and The present invention is characterized in that it includes precharging means for charging the data bus in advance before outputting data at the time of reading.

"Operation" The data bus is charged before the read data is output, so that even if the read data is on the charge level side, no time is required for the read data to be finalized.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the overall schematic configuration of an embodiment of the present invention. In this figure, M O−M 7
are 1-bit x 64K (or 128K) memories, each of which is connected in parallel to form an 8-bit x 64K (or 128K) memory block MBO. BTl and -BTl7 are memories M, respectively. - This is a bit interface that controls the exchange of data between the data buses IOo to IO7 on a bit-by-bit basis.
0 is data bus l0p-0 and bit interface B
This is a pixel interface circuit that exchanges data (hereinafter referred to as pixel data) between TIO and BTI7. This pixel interface circuit PXI-0 has bit interfaces BTU, -BT
Memory via either I7? vl o” M?
It is designed to exchange pixel data with either of the following. Timing command control circuit 1'
CC is address data supplied from the outside via address buses AO to A7, an output enable signal OE, a write enable signal WE1 and a data bus control signal DB, which are supplied via a predetermined control bus.
C, a circuit that controls access to the memory block MBO based on the row address strobe signal RAS, column address strobe signal CAS, etc., and also controls the output data buffer (see Figure 3), which will be described later. be. Mako, timing command
The control circuit TCC is the bit interface B
Memory M according to the value of the bit mask data supplied from T I o-B T I t. ~ It is designed to control the write enable signal of M7. Further, the timing command control circuit TCC decodes the command data supplied from the address buses AO to A7, and controls each part of the circuit based on the decoding result.

The above-described components constitute the memory device #OM. In this embodiment, a total of 4 memory devices #OM and memory devices #IM to #3M having the same configuration as this memory device #OM and memory devices #IM to #3M having the same configuration as the memory device
It consists of two parts.

In this case, the memory blocks in each memory device #1M to #3M are MHI-Mn2, the pixel interfaces are PXI-1 to PXI-3, and the data buses connected to each pixel interface are top-t to 10. It is expressed as RI-3 to distinguish it.

FIG. 2 shows the connection state of the memory devices #OM to #3M, and as shown in this figure, each memory device #OM
~#3M data bus I Oo''-107 is commonly connected for each bit, and each memory device #OM~#3M
The data buses l0p-0 to IOρ-3 are each individually wired.

Next, bit interface BT1. - Output data buffers provided in BTI 7 and pixel interfaces PXI-0 to PXI-3 will be described. FIG. 3 is a block diagram showing the configuration of the output data buffer, and the area surrounded by a dashed line indicates the output data buffer (symbol l).
. This output data buffer 1 includes AND gates AN I , AN 2 , AN 3 , OR gates ORI, ? as shown in the figure. It consists of a 1 m field effect transistor 2.3 and a load resistor R1. The memory N mentioned above
The signal DATA read from 1° to M7 is transferred to the data bus I after passing through this output data buffer l.
Oo~■07 or I Op -0~I Op -3
It is now output to .

In the AND gate ANI shown in FIG. 3, one input terminal has positive logic and the other has negative logic, and the signal PCG is supplied to one input terminal, and the signal DBT is supplied to the other input terminal. It looks like this.

The AND gate AN2 has first to third input terminals (all positive logic), and each input terminal receives a signal DBT and a signal DATA.
, OE are respectively supplied. ANDGATE AN3 is
One of the input terminals has negative logic and the other has positive logic, and one input terminal receives the signal DATA, and the other input terminal receives the signal O.
E is supplied to each. And gate A
The output signals of NI and AN2 are supplied to the gate of field effect transistor 2 after passing through OR gate ORI, and the output signal of AND gate A N 3 is supplied to the gate of field effect transistor 3. field effect transistor 2
A positive voltage is applied to the drain via the resistor R1, and the source is connected to the drain of the field effect transistor 3. The connection point P between the field effect transistor 2 and the field effect transistor 3 is connected to the data bus I O1 (i
= 0 to 7) or data bus l0p-0 to Iop-
3, and the source of the field effect transistor 3 is grounded. Resistor R2 is a pull-up resistor (external resistor) connected to the data bus,
Its value is set larger than that of the resistor R1.

Next, the signal PCG in the above configuration is a signal that becomes an "L" signal when performing precharging during memory reading, and becomes "0" when outputting read data and writing memory.
(The circuit that generates the signal PCG will be described later).The signal DBT is controlled so that the command code for "data buffer tri-state" is supplied to the timing command control circuit TCC as described above. It becomes an "l" signal, and becomes a "0" signal when a command code of "data buffer oven drain" is supplied.

The command "data buffer 3-state" is a command output when the output data buffer l functions as a tri-state buffer, and the command "data buffer open drain" causes the output data buffer l to function as an open-drain buffer. This is the command output when

Here, the function of signal DBT will be explained.

First, when the signal DBT is the "L" signal, the signal DATA read from the memory is at the timing when the output enable signal OE is the "1" signal.
It is supplied to the gate of field effect transistor 2 via AND gate AN2 and OR gate ORI, and its value is inverted by AND gate AN3 and supplied to the gate of field effect transistor 3. As a result, at point P,
When signal DATA is “L”, “L” level, signal DATA
When is "0", a signal of "0" level is obtained. Furthermore, when the output enable signal OE becomes a "0" signal, AND gates AN2 and AN3 are both closed, so both field effect transistors 2.3 are turned off, and as a result, point P is in a high impedance state. becomes.

In this way, when the signal DBT is a "1" signal, the output data buffer I becomes a tri-state buffer.

On the other hand, when the signal DBT is a “0” signal, the AND gate A
N2 is always in the closed state, and the AND gate ANI does not output the "L" signal unless the signal PCG becomes "L", so the field effect transistor 2 is always in the off state at the read data output timing. It is in. The signal DATA, which is read data, is inverted in value by the AND gate A N 3 and supplied to the gate of the field effect transistor 3 at the timing when the output enable signal OE is a "1" signal. As a result, a signal corresponding to the signal DATA is obtained at point P. Further, the output state in this case is an oven drain output from the field effect transistor 3 because the field effect transistor 2 is in an off state. In this way, when the signal DBT is a "0" signal, the output data buffer l becomes an open drain buffer.

Next, a circuit for generating signal PCG will be explained.

This generation circuit is provided within the timing command control circuit TCC, and its configuration is shown in FIG. In the figure, Ta, Tc=Tf are terminals, and the signals shown in the figure are supplied to each terminal. And gate AN5. AN7
, AN9 and inverter INV8 are connected to the terminal T c -
The purpose is to determine the value of the signal PCG based on the signal supplied to the T r, and in this case, the signal PCG is
” signal, as is clear from the figure, the data bus control signal DBC is “0”, the column address
The strobe signal CAS is "1", the write enable signal WE is "0", and the output enable signal OE is "0".

Next, the operation of this embodiment with the above configuration will be explained.

FIG. 5 is a waveform diagram showing the waveforms of various parts of the circuit when precharging the data bus in this embodiment.
This is an example when read modify write is performed. The operation will be explained below based on this figure. However, in the following explanation, the command ``data panf oven drain J'' is executed, and the signal DBT (see Figure 3) is
is assumed to be at the “0” signal. Further, a case where data is read in the word direction will be explained as an example.

First, time 1. When the row address strobe signal RAS rises, the row address data supplied via the data buses AO to A7 is taken in, thereby determining the row address. In addition, at time 12, as shown in the same figure, the data bus IOi
Although mask data instructing the masking of each pit is supplied from , a description thereof will be omitted since it is not the gist of the present invention. Next, at time t, the column address strobe signal CAS rises and the column address data is taken in.
The address to be accessed is determined. Further, at time t, as shown in FIG. 5, the data bus control signal DBC is "0", the column address stove signal CAS is "1", the write enable signal WE is "0", and Since the enable signal OE is "0", the signal PCG becomes "1" as described above (see FIG. 4). When the signal PCG becomes the "l" signal, the AND gate ANl shown in FIG. 3 outputs the "l" signal, and this "l" signal is supplied to the gate of the field effect transistor 2 via the OR gate ORI. As a result, the field effect transistor 2 is turned on, and the resistance R
1 and the data bus I via the field effect transistor 2.
Charging is started for Oi. In this case, the resistor R1 connected to the toilet in of the field effect transistor 2
Since the value of is not a large value, the time constant due to the resistor R1 and the data bus stray capacitance is small, so that the above-mentioned charging is performed rapidly, and at time t3 shown in FIG.
Habo Charge ends. Then, at time t4,
The output enable signal OE rises to the "L" signal, and after a predetermined delay time due to device characteristics etc. from this point, the data read by the access starting from time t, j is transferred to the data bus IOi. (see time t5).

On the other hand, at time t4, when the output enable signal OE rises, the signal PCG falls to a "0" signal, which causes the AND gate A N shown in FIG.
The respective output signals of I and the OR gate ORI become "0" signals, and the field effect transistor 2 is turned off. That is, at this time t4, the positive voltage that had been applied to the data bus via the resistor Ill is cut off. On the other hand, between time t4 and time t5, the data bus continues to be charged via the resistor R2, albeit with a small current.

As a result, at time t5, the charges charged to data bus IOi are maintained, and data bus IOi
is at the "l" signal level. As a result, even if the read data output at time t5 is a "1" signal, this "1" signal is maintained as it is. Furthermore, when the read data is a "0" signal, that is, when the field effect transistor 3 shown in FIG. 3, there is no significant time delay before the read data "0" signal is determined. The above is the memory read operation.

Then, read data output as described above,
After reading at a predetermined timing, write data is supplied to the data bus IOi.

Next, at time t, the write enable signal WE is raised to the "1" signal, thereby writing to the memory is performed. On the other hand, at time t8 before time t7 when the write data is supplied, the signal DBC is raised to the "L" signal. In this way, the signal DBC is “l”
If it is a signal, the signal PCG will never become a "1" signal (see FIG. 4), so a precharge operation will not be performed at the time of memory write, and there will be no conflict with write data.

The above is the memory write operation.

Note that although the above description takes as an example the case of accessing in the word direction, the same operation occurs when accessing in the pixel direction. That is, when accessing in the pixel direction, the pixel interfaces pxr-o to P
The output data buffer in XI-3 performs a precharge operation at the timing shown in FIG. 5 in the same manner as above, and
Data buses l0p-0 to l0p-3 (see FIG. 2) are charged prior to data read timing.

In this way, even when the memory device has a matrix configuration, there is no delay in determining the "1" signal.

Furthermore, in the above embodiment, whether a circuit for precharging was provided in each memory device #OM to #3M,
Instead, the same effect can be achieved even if a precharge circuit is provided as an external circuit for the memory device.

Furthermore, the connection relationships among the bit interface, pixel interface, timing command control circuit, and memory section and the assignment of various functions are not limited to those shown in the above embodiments, and various modifications are possible.

For example, as shown in FIG. 7, memory blocks 70 to 73 having memory interfaces Ml and memory block interfaces 75 to 78 are provided, and the memory interface Ml has a write pit masking function for bit masking when writing data. Alternatively, the memory block interfaces 75 to 78 may be provided with various other functions.

Furthermore, if the memory capacity is large, a configuration as shown in FIG. 8 may be used. In this figure, each memory block 80.81 has 4 bits x 64 K x 4 planes (4 planes), and each memory block 80.81 is provided with a memory interface MI. In this case, each memory interface MI is configured to exchange data in units of 4 bits with the memory block interface MHI. The memory block intervoice MBI is configured to send and receive data to and from external circuits in units of 8 bits in the word direction and in units of 4 bits in the pixel direction.

In the example shown in FIG.
(2) requires a word direction/pixel direction switching function.

As a result, when the input/output data of the memory interface Ml is switched to the word direction, it becomes the data of the selected I or multiple planes in the word direction, and when it is switched to the pixel direction, it becomes the data of the word direction of each plane. It becomes pixel data.

Further, the functions required for the memory block interface are a word direction/pixel direction switching function, a read pit mask, a read plane mask, and a precharge function. Then, when switching to the word direction, the 4-bit data input/output by each memory interface M1 becomes 8 bits in total, and this 8-bit data is input/output as word data according to the read plane mask. On the other hand, when switched in the pixel direction, each memory interface MI inputs and outputs the pixel data of each heavy color corresponding to the same one surface by ANDing them according to the lead pit mask. The precharge function is necessary when a plurality of NoStems shown in FIG. 8 are provided in parallel and a data bus is commonly connected.

"Effects of the Invention" As explained above, according to the present invention, each output terminal of a plurality of memory sections whose output terminals are open type,
Since it is connected to a data bus and has a precharge means that charges the data bus in advance before outputting data during memory read, the read data output on the data bus is an "L" signal (level on the charging side). Also, it does not take time for this "1" signal level to be determined, and this makes it possible to perform high-speed reading.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall schematic configuration of an embodiment of the present invention, and FIG. 2 shows each memory device #0 to ■ to #3 to 1.
FIG. 3 is a circuit diagram showing the configuration of the output data buffer l, FIG. 4 is a circuit diagram showing the configuration of the output circuit of the signal PCG, and FIG.
The figure is a waveform diagram for explaining the operation of the same embodiment, FIG. 6 is a conceptual diagram showing the relationship between the storage data of the frame memory and the display surface, and FIGS. FIG. 2 is a block diagram illustrating an example of how interface functions are connected. ■・・・Output data buffer, 2...
...Field effect transistor (precharge means), R1
...Load resistance (precharge means), A N 1.
...and gate (precharge means), OR1.
...OR gate (precharge means), AN5. A
N7. AN9...AND gate (precharge means), INV8...Inverter (precharge means), IO. ~10. ...Data bus, 10ri-0~l0p-
3...Data bus, MBO-MB3...Memory block (memory section).

Claims (2)

[Claims] (1) Each output terminal of a plurality of memory sections whose output terminals are open type is connected to a data bus, and a precharging means is provided for charging the data bus in advance before outputting data during memory reading. A memory device characterized by: (2) In the memory unit, one word consists of one or more bits, and each storage unit constituting the word can be accessed in the word direction and the pixel direction. 2. The memory device according to item 1.