JPS6352230B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ignition timing control circuit for an internal combustion engine,
In particular, the present invention relates to an ignition timing control circuit for an internal combustion engine that includes a calculation ignition timing control circuit and an abnormality response device for when the circuit does not operate normally.

The present invention is an ignition timing control circuit for an internal combustion engine, which has a fixed ignition signal generation circuit as a back-up for the calculation ignition timing control circuit, and the calculation ignition timing control circuit detects an abnormality in the calculation ignition signal and a drop in battery voltage. The fixed ignition signal generating circuit is equipped with a circuit for selecting a fixed ignition signal and a calculation ignition circuit failure detection circuit in case of a starter switch that may not guarantee operation. The purpose is to make the vehicle run more easily using the output signal.

Conventionally, ECUs (engine control units) have been announced that calculate ignition timing by inputting various engine parameters and output the appropriate ignition timing, but the calculations are mainly performed by microcontrollers. In order to maintain its correct functionality,
It is necessary to strictly control the power supply voltage for NMOS bipolar transistors, etc. to around 5V (5V±10%). Especially when starting at low temperatures, it becomes difficult to guarantee the above voltage due to a drop in battery voltage.
It is difficult to ensure the operation of microcontrollers. Furthermore, if some kind of failure occurs in a computing device such as a microcomputer, there is also the problem that the vehicle becomes unable to run.

The present invention has been made with the intention of solving the above-mentioned problems.

The present invention provides a fixed ignition signal for back-up purposes that generates a fixed ignition signal to be used instead when a situation occurs where proper operation of the arithmetic ignition circuit for generating the arithmetic ignition signal cannot be guaranteed. Assuming that a generation circuit is used, ignition or energization for a calculated ignition signal occurs only once between ignition timing or energization timing for two consecutive fixed ignition signals in order to determine whether the above situation occurs. In this case, the circuit includes a calculation ignition circuit failure detection circuit including a logic circuit that determines that the operation of the calculation ignition circuit is normal, and further selects between the calculation ignition signal and the fixed ignition signal based on the above determination result. An object of the present invention is to provide an ignition timing control circuit for an internal combustion engine, which includes an ignition signal selection signal generation circuit and an ignition signal selection circuit for generating a selection signal for ignition signal selection.

The ignition timing control circuit for an internal combustion engine according to the invention described above selects the fixed ignition signal when the operation of the calculation ignition circuit is determined to be abnormal or when the starter switch is turned on, and otherwise selects the fixed ignition signal. generates an ignition signal selection signal to select the calculated ignition signal, and the timing of switching between the two ignition signals is performed in accordance with the timing of the fixed ignition signal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of an ignition timing control circuit for an internal combustion engine according to an embodiment of the present invention will be described below with reference to the accompanying drawings. Note that in the following description, the internal combustion engine will be abbreviated as an engine.

First, the overall configuration of the ignition timing control circuit according to the present invention will be explained with reference to the block diagram of FIG.
In FIG. 1, numeral 1 is a sensor that detects various information regarding the operating state of the engine (for example, engine intake pipe pressure, engine cooling water temperature, etc.). 2
is an engine rotation sensor that detects the rotation speed and engine rotation angle of the engine by detecting, for example, the rotation of the crankshaft or camshaft.
Reference numeral 3 denotes a starter switch for switching the starter on and off, which is used when starting the engine, and outputs a starter signal 3a when the starter is on. 4 inputs detection signals from various sensors 1, rotation sensor 2, and starter switch 3, calculates the optimum ignition timing according to the current engine rotational speed, load, etc., and generates a calculated ignition timing signal 4a. This is a calculation ignition timing control circuit that outputs. 5 is a fixed ignition signal generating circuit which inputs signals from the rotation sensor 2 and the starter switch 3 and generates a fixed ignition signal 5a for igniting at a fixed fixed ignition timing in synchronization with the signal from the rotation sensor 2; It is. 6 is an output signal 4a of the calculation ignition timing control circuit 4 and an output signal 5a of the fixed ignition signal generation circuit 5.
is input, and it is checked whether the ignition coil energization start signal of the calculated ignition signal 4a comes only once between the ignition timing of the fixed ignition signal 5a (the ignition coil's energization/de-energization timing) and the next ignition timing. The abnormality detection signal 6a is output when the number of times this condition is not satisfied continues for the set number of times, and once an abnormality is detected, the abnormality detection signal 6a is output unless the number of times the above-mentioned condition is met exceeds the set number of times. This is a calculation ignition circuit failure detection circuit that continues to operate. Its action will be detailed later. 8 is an abnormality detection signal 6a from the calculation ignition circuit failure detection circuit 6, a starter signal 3a from the starter switch 3, a power-on reset signal 11a (described later) from the power supply circuit 11, and a signal from the fixed ignition signal generation circuit 5. The fixed ignition signal 5a is input, and the fixed ignition signal 5a is selected when the power is turned on, when starting the starter where there is a risk of power supply voltage drop, and when there is an abnormality in the calculation ignition timing control circuit 4. In other cases, the calculation ignition is selected. This is an ignition signal selection signal generation circuit that outputs a selection signal 8a for selecting the signal 4a. Note that the switching timing of the ignition signal selection of the selection signal 8a is synchronized with the ignition timing of the fixed ignition signal 5a. 10 selects the calculated ignition signal 4a from the calculated ignition timing control circuit 4 and the fixed ignition signal 5a from the fixed ignition signal generation circuit 5 based on the selection signal 8a from the ignition signal selection signal generation circuit 8, and generates the ignition signal. This is an ignition signal selection circuit that outputs 10a. Reference numeral 7 denotes a power amplification circuit which inputs the ignition signal 10a from the ignition signal selection circuit 10 and outputs an amplified ignition signal 7a for driving the ignition coil 9. 9 is an amplified ignition signal 7a from the power amplifier circuit 7
The ignition coil receives the supply of ignition spark voltage 9a and outputs the ignition spark voltage 9a to the ignition plug 12. Reference numeral 12 denotes an ignition plug that receives the ignition spark voltage 9a from the ignition coil 9, generates an ignition spark, and ignites the compressed air-fuel mixture in the engine cylinder. 11
1 is a known power supply circuit which inputs a voltage supplied from an on-vehicle battery, makes the voltage constant, and supplies power to the entire apparatus shown in FIG. 1. Incidentally, this power supply circuit 11 outputs a power-on reset signal 11a for initializing each circuit at the same time as the power supply switch is turned on.

Next, the operation of the device of the present invention will be explained with reference to the accompanying drawings, focusing on the operation of the arithmetic ignition circuit failure detection circuit 6.

The configuration of the operational ignition circuit failure detection circuit 6 is shown in FIG. 2a. In Figure 2a, 601, 602, 6
03 and 605 are known D flip-flops, and their truth tables are shown in FIG. 2b. Also 6
04, 606, 607 and 608 are known RS flip-flops, and their truth tables are
Shown in Figure c. Regarding the upper terminal symbols in Figure 2b, D represents the D input terminal of the D flip-flop;
R represents its reset input terminal, CL its clock input terminal, Q its output terminal, and T in the upper terminal symbol in Figure 2c is the trigger input terminal of the RS flip-flop (same as the clock input terminal described above). has a unique function). Furthermore, regarding the symbols representing signal levels in both figures above, H represents high level, L represents low level, X represents that the input signal level can be either high or low, and Q represents Q.
The output level is (the negation of Q). Further, the symbol 〓 represents a rising edge valid, and the symbol 〓 represents a falling edge valid.

In FIG. 2a, CLK2 is an output signal from an oscillation circuit (not shown), which is used as a clock signal to synchronize the operation of the circuit shown in FIG. A sufficiently higher frequency than the fixed ignition signal 5a (e.g. 40K
Hz) signal. Here, the calculated ignition signal 4a and the fixed ignition signal 5a start energizing the ignition coil when they rise, and stop energizing the ignition coil when they fall, causing ignition. Note that both ignition signals are detected at the edges marked with arrows in FIG. 2a. In addition, in each flip-flop, the CL input terminal is connected at the rising edge of the input pulse waveform.
The T input terminal performs detection at the falling edge of the input pulse waveform.

The following description will be given with reference to the time charts of FIGS. 3 to 6. Figure 3 of the same time chart is
Arithmetic ignition circuit failure detection circuit (first
At 6) in the figure, the power reset signal 11a
are flip-flops 601, 602, 603, 6
08 and the input terminal of the inverter gate 632 to start the failure detection operation, the state shown in Figure 3 indicates that the operational ignition circuit failure detection circuit 6 is operating normally, This shows a state in which the abnormality detection signal 6a of the output signal indicates normality or abnormality corresponding to the normality or abnormality of the calculated ignition signal 4a by a low or high level signal, respectively. FIG. 4 shows the first time that the detection result of the calculation ignition circuit failure detection circuit 6 is not normal, and the display of normal or abnormal of the abnormality detection signal 6a of the output signal corresponds to the abnormality or normality of the calculation ignition signal 4a, respectively. As an example of the state, a case is illustrated in which the abnormality detection signal 6a is normal and at a low level, and the calculated ignition signal 4a is abnormal. FIG. 5 shows a state in which the level of the abnormality detection signal 6a is automatically reversed when abnormal detection results of the arithmetic ignition circuit failure detection circuit 6 shown in FIG. 4 occur three times in a row. ing. FIG. 6 shows an enlarged waveform of a part of the signal that changes before and after the point in time when the level of the abnormality detection signal 6a in FIG. 5 is reversed.

In FIG. 2a, flip-flop 601
The fixed ignition signal 5a from the fixed ignition signal generation circuit 5 is applied to its D input, and as shown in FIG. Clock synchronized fixed ignition signal 60 that falls in synchronization with falling
1a is output to its Q output. Flip-flop 602 has flip-flop 60 at its D input.
Since the clock synchronous fixed ignition signal 601a from 1 is applied, the clock synchronous fixed ignition signal 601a is applied.
A clock-synchronized fixed ignition signal 602a delayed by one cycle of CLK2 from 01a is output to its Q output. The NAND gate 609 receives the clock synchronized fixed ignition signal 6 from the flip-flop 601.
Inverted signal 610 by inverted gate 610 of 01a
Since the clock synchronization fixed ignition signal 602a from the flip-flop 602 and the clock synchronization fixed ignition signal 602a are input, the fall of the clock synchronization signal is detected. That is,
A fixed ignition timing signal 609a having a pulse width of one cycle of the CLK2 signal is output. Since the flip-flop 603 receives a fixed ignition timing signal 609a at its D input, it outputs a fixed ignition timing signal 603a that is delayed by one period of CLK2 from the fixed ignition timing signal 609a.

Note that 11a is a power-on reset signal for initialization applied to the reset terminal of the flip-flop.

Flip-flops 604, 605 in FIG. 2a
In the combinational circuit, flip-flop 605
The reset input is a fixed ignition timing signal 60.
Since the inverted signal 3a is input, when the fixed ignition timing signal 603a goes low, the Q output signal 605a of flip-flop 605 goes low. The flip-flop 604 has a T input,
An inverted signal 63 by the inverting gate 631 of the calculated ignition signal 4a from the calculated ignition timing control circuit 4 in FIG.
1a, the flip-flop 60 is activated at the timing of the first calculation ignition signal 4a.
4 Q output signal 604a is inverted to high level,
It is output as a calculated energization normal signal 604a, and at the second energization timing of the calculated ignition signal 4a, the Q output signal 604a of the flip-flop 604 is inverted to a low level. The flip-flop 605 is
Since the inverted signal 614a of the normal calculation energization signal 604a is input to the CL input, the CL input rises at the timing of the second energization of the calculation ignition signal 4a, so the Q output of the flip-flop 605 becomes high level. , outputs a calculated second ignition energization detection signal 605a. The NAND gate 611 is
Since the inverted signal 612a of the second calculated ignition energization detection signal 605a of the flip-flop 605 is input, when the second calculated ignition energization detection signal 605a is at a high level, its output becomes a high level, and a reset signal is output to the flip-flop 604. By doing so, the calculation energization normal signal 604a is cleared. From then on, no matter how many times the energization signal of the calculated ignition signal 4a is received, the second calculated ignition energization detection signal 605a
This state will continue in order to maintain a high level. Note that this state is cleared when the fixed ignition timing signal 603a becomes low level. Fourth
Signals 4a, 604a and 60 indicated by broken lines in the figure
5a indicates that the above-mentioned abnormal calculation ignition signal occurs three times in a row.
This figure is based on the assumption that this occurs twice. At this time, the signal 604a is inverted to low level when the calculated ignition signal 4a rises twice, and after that, as long as the signal 605a is high level, the signal 604a is kept at low level and the calculated ignition signal is abnormal. shows. And the above state is signal 603a
is shown to be cleared when the signal 605a goes low and the signal 605a inverts to a low level.

NOR gates 615 and 616 have fixed ignition timing signal 609a from NAND gate 609 at one input, and arithmetic energization normal signal 609a from flip-flop 604 at the other input.
04a and its inverted signal 614a are input, the output signal 616a of the gate 616 is at a low level when the calculation energization is normal, and the output signal 616a of the gate 616 is at a low level.
The output signal 615a of No. 5 outputs a high level output signal when the fixed ignition timing signal 609a is at a low level, and vice versa when the calculated energization signal is abnormal, and the output signal 616a outputs a high level output signal when the fixed ignition timing signal 609a is at a low level. At certain times, it is at a high level, and the output signal 615a is at a low level.

The NOR gates 623, 624, and 625 constitute a data selector, and the output signal (abnormality detection signal) of the flip-flop 608
6a and its inverted signal 629a are, respectively,
Since it is applied to one input of NOR gates 624 and 623, when the abnormality detection signal 6a is at a high level, that is, when the calculation ignition circuit is determined to be malfunctioning, the output signal 625a of the NOR gate 625 is
Inverted signal 6 of output 615a of NOR gate 615
This signal is in the same phase as 17a. Further, when the abnormality detection signal 6a is at a low level, that is, when the calculation ignition circuit is determined to be normal, the output signal 625a of the NOR gate 625 is the output signal 625a of the NOR gate 616.
It is in the same phase as the inverted signal 618a of 16a.

Therefore, in the case shown in FIG. 4, when the abnormality detection signal is normal (the output signal 608 of the flip-flop 608
a is low level), and when the calculation energization signal is abnormal (the output signal 604a of the flip-flop 604 is low level), the output signal 625 of the NOR gate 625 is
a is in phase with the output signal (fixed ignition timing signal) 609a of the NAND gate 609. Also, when the abnormality detection signal is abnormal (flip-flop 6
Similarly, when the output signal 6a of the flip-flop 604 is at a high level) and the calculation energization signal is normal (the output signal 604a of the flip-flop 604 is at a high level), the output signal 625a of the NOR gate 625 is at a high level.
It has the same phase as the output signal 609a of No.9. Therefore,
The output signal 626a of the NOR gate 626 is the NOR
When the output signal 625a of the gate 625 is at a low level, CLK2 rises at the timing when it falls,
Its pulse width is half a cycle of CLK2. Therefore, at this time, the output signal 627a of the inverting gate 627 falls, and the output signal 606 of the flip-flop 606 falls.
A is changed from a low level to a high level as shown in FIG.

Similarly, NOR gates 619, 620, 621
A pair of data selectors are configured, and the output signal 6a from the flip-flop 608 is
and its inverted signal 629a are applied to one input of the NOR gates 620 and 619, respectively, so when the abnormality detection signal 6a is at a high level (when the abnormality detection signal is abnormal), the output signal of the NOR gate 621 621a is a signal having the same phase as the inverted signal 618a of the output signal 616a of the NOR gate 616. Also, when the abnormality detection signal 6a is at a low level (when the abnormality detection signal is normal), the NOR gate 621
The output signal 621a of is in phase with the inverted signal 617a of the output signal 615a of the NOR gate 615.

Therefore, as shown in FIG. 3, when the abnormality detection signal is normal, the output signal 6 of the flip-flop 608 is
When a is at a low level and the calculation energization signal is normal, the output signal 604a of the flip-flop 604
is at a high level, the output signal 621a of NOR gate 621 is in phase with the output signal 609a of NAND gate 609, and the output signal 621a of NOR gate 621 is in phase with the output signal 609a of NAND gate 609.
7,608 is reset. When the abnormality detection signal is abnormal, the output signal 6a of the flip-flop 608 is at a high level, and when the calculation energization signal is abnormal, the output signal 604a of the flip-flop 604 is high.
is at a low level, and the output signal 621a of the NOR gate 621 is similarly in phase with the output signal 609a of the NAND gate 609.

The reset inputs of the flip-flops 606 and 607 receive the output signal 622 of the NAND gate 622.
Since a is applied, when the output signal 622a is at a high level, the Q outputs of flip-flops 606 and 607 are respectively at a low level.

As described above, when the abnormality detection signal and the calculated energization signal are both normal or both are abnormal, as shown in FIG. 3, when the fixed ignition timing signal 609a is at a low level, the output signal 62
2a becomes high level, flipflop 60
Since the Q output signal of 6,607 becomes low level,
The output signal 628a of the NAND gate 628 remains at a high level. Therefore, the output signal level of flip-flop 608 does not change.

However, as mentioned above, the abnormality detection signal is normal (signal 6a is low level) and the calculation energization signal is abnormal (signal 6a is low level).
04a is low level) or vice versa,
When the abnormality detection signal is abnormal (signal 6a is high level) and the calculation energization signal is normal (signal 604a is high level), the output signal 622a of the NAND gate 622 is low level, as shown in FIG. can be,
When the output signal 627a of the inverting gate 627 falls from the high level to the low level, the Q output signal 606a of the flip-flop 606 is inverted from the low level to the high level.

The above action will be examined in more detail in the case where the abnormality detection signal 6a is abnormal and at a high level, and the calculated ignition signal 4a is normal and the signal 604a is at a high level. In this case, NOR gate 62
The outputs of 0 and 616 will be low level. Therefore, the output signal 618a of the inverting gate 618 goes high, and the output of the NOR gate 619 goes low. Therefore, the output signal 62 of the NOR gate 621
1a is a high level. At this time, the power reset signal 11a is at a low level, so the inverting gate 6
The output of 32 is high level, and the output of NAND gate 6
The output signal 622a of No. 22 becomes low level. On the other hand, when the signal 6a and the signal 604a are at a high level, the output signal of the NOR gate 624 is at a low level, but one input of the NOR gate 623 receives the low level output signal 629a of the inverting gate 629, and the NOR gate 624 is at a low level. The output of gate 623 is inverted gate 6
The output signal 617a of No. 17 changes from low level to high level at the timing of high level to low level. Therefore, at this timing, the output signal 625a of the NOR gate 625 changes from high level to low level.
That is, the output signal 625a changes from high level to low level at the timing when the output signal 617a changes from high level to low level, that is, the output signal 615a changes from low level to high level.

On the other hand, one input of the NOR gate 615 has
Since a low level signal is applied through the inversion gate 614, the output signal 617a changes from high level to low level at the timing when the other input signal 609a to the NOR gate 615 changes from high level to low level. It is. Therefore, NAND circuit 6
The output signal 625a changes from high level to low level at the timing when the output signal 609a of 09 changes from high level to low level. Therefore, referring to Figure 4,
When the output signal 625a becomes low level and the clock signal CLK2 falls, the NOR circuit 62
The output signal 626a of the gate 6 changes from low level to high level, and therefore the output signal 627 of the inverting gate 627 changes from low level to high level.
Since a changes from high level to low level, the output signal 606a of flip-flop 606 changes from low level to high level. In contrast to the above, the same result will occur when the abnormality detection signal 6a is normal and at a low level, and the calculated ignition signal 4a is abnormal and the signal 604a is at a low level. FIG. 4 is a signal waveform diagram illustrating the latter case.

Next, when the output signal 627a falls three times as the fixed ignition signal 5a is repeatedly generated, the first signal 607a shown in FIG. 4 is at a low level, and the signal 606a changes from low level to high level. Next, the signal 607a changes from low level to high level, the signal 606a changes from high level to low level, and then the signal 607a shown in FIGS. 5 and 6 remains at high level. The light is on, signal 6
06a changes from low level to high level, and finally, at the third fall of output signal 627a, both signals 606a and 607a become high level, so the output signal 628a of NAND circuit 628 changes from high level to low level. and inverts the abnormality detection signal 6a (FIGS. 5 and 6). Thus, when the abnormality detection signal 6a is at a low level, ie, normal, it changes to a high level, ie, when it is abnormal, and conversely, when it is high, ie, abnormal, it changes to a low level, ie, when it is normal.

Incidentally, FIG. 6 shows an enlarged time chart in the vicinity of the timing _t4 at which the signal 6a switches in FIG. When the output signal CLK2 of the oscillation circuit falls at time t ₀ , the NOR gate 626 and the inverting gate 627
Due to the delay, the output signal 627a of the inverting gate 627 falls at time _t1 . Therefore, due to the delay of flip-flop 606, output signal 606a of flip-flop 606 rises at time _t2 . Therefore, due to the delay of the NAND gate 628, the time
At _t3 , the output signal 628a of the NAND gate 628 falls. Next, due to the delay of the flip-flop 608, the output signal 6a of the flip-flop 608 is inverted from low level to high level as shown in FIG. 6 at time _t4 . Therefore, the inversion gate 627,
NOR gate 619, 621, NAND gate 62
Due to the delay of 2, the NAND gate 62 at time t ₅
The second output signal 622a rises and clears the flip-flops 606 and 607 after the delay time has elapsed. At the same time, NOR gates 624, 625,
626, due to the delay of the inversion gate 627, the time t ₅
The output signal 627a of the inverting gate 627 rises. Due to the delay of flip-flops 606 and 607, output signals 606a and 607a of flip-flops 606 and 607 fall at time _t6 , respectively. Therefore, due to the delay of NAND gate 628, output signal 62 of NAND gate 628 at time _t7
8a stands up.

To summarize the operation of the circuit of the present invention explained above, in the arithmetic ignition circuit failure detection circuit 6 shown in FIG. 1, the flip-flop 60 shown in FIG.
1,602,603 and inversion gate 610,
The NAND gate 609 generates fixed ignition timing signals 609a and 603 based on the fixed ignition signal 5a from the fixed ignition signal generation circuit 5 of FIG.
At this timing, the flip-flops 604 and 605 and the inverting gate 6 shown in FIG. 2a are formed.
31, 614, 612, 613, the calculated energization signal determined by the NAND gate 611 whether the calculated energization timing of the calculated ignition signal 4a from the calculated ignition timing control circuit 4 shown in FIG. 1 is normal, and the calculated energization signal in FIG. Abnormality detection signal 6 determined by the flip-flop 608 of whether the calculated ignition signal is normal or not.
a and enter NOR gates 615, 616,
619, 620, 621, 623, 624, 62
5, 626, NAND gate 622, inverting gates 617, 618, 627 perform selection, and control signal 627 is sent to flip-flops 606, 607.
By outputting signals a and 622a, the calculated ignition signal 4a is determined to be abnormal or normal when the abnormality or normality continues for more than a specific set number of times (three times in the above embodiment), thereby detecting a failure. It's summery.

In the embodiment described above, it was determined whether energization for calculation ignition occurs only once between the ignition timings of two consecutive fixed ignitions, but it is determined whether ignition of calculation ignition occurs only once. It may be determined by Further, as the determination period, a period between two consecutive fixed ignition energization start times may be used.

Thus, according to the present invention, the calculation ignition timing control circuit inputs detection signals from various sensors 1, rotation sensor 2, and starter switch 3, calculates appropriate ignition timing, and outputs calculation ignition timing signal 4a. 4. A fixed ignition signal generation circuit that outputs a fixed ignition signal 5a to ignite at a fixed ignition timing when the calculation ignition timing control circuit 4 is out of order or when the starter switch is turned on, which may malfunction due to battery voltage drop. 5. A calculation ignition circuit failure detection circuit 6 that inputs the calculation ignition signal 4a and the fixed ignition signal 5a, determines whether the calculation ignition signal is normal, and then outputs an abnormality detection signal 6a, the abnormality detection signal When 6a indicates an abnormality in the calculated ignition timing control circuit or when the starter switch is turned on, the fixed ignition signal 5a is output, and at other times, the calculated ignition signal 4a is output.
an ignition signal selection circuit 10 which selects the ignition signal 1 and outputs it to the power amplifier 7 as the ignition signal 10a;
0a and outputs a signal 7a for driving the ignition coil 9, and a power-on reset for supplying power to each of the circuits and initializing each circuit when the power is turned on. By configuring the ignition timing control circuit using the power supply circuit 11 that outputs the signal 11a, an excellent ignition timing control circuit with a highly safe backup function that can output an appropriate ignition signal in any situation is provided. can do.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an ignition timing control circuit for an internal combustion engine according to the present invention. FIG. 2a is a schematic circuit diagram showing the configuration of a calculation ignition circuit failure detection circuit in the ignition timing control circuit shown in FIG. FIGS. 2b and 2c show a known D flip-flop and an RS flip-flop used in the arithmetic ignition circuit failure detection circuit shown in FIG. 2a, respectively.
1 is a drawing showing a truth table of a flip-flop.
FIGS. 3, 4, and 5 are signal waveform diagrams of various parts of the arithmetic ignition circuit failure detection circuit shown in FIG. 2a for explaining the operation of the circuit. Figure 6 shows the fifth
FIG. 2 is an enlarged waveform diagram showing an enlarged waveform of a portion of a signal that switches at time _t4 in the figure. Explanation of symbols, 1...Various sensors, 2...Rotation sensor, 3...Starter switch, 3a...Starter signal, 4...Calculated ignition timing control circuit, 4a...
...Calculated ignition signal, 5...Fixed ignition signal generation circuit,
5a...Fixed ignition signal, 6...Arithmetic ignition circuit failure detection circuit, 6a...Abnormality detection signal, 7...Power amplification circuit, 7a...Amplified ignition signal, 8...Ignition signal selection signal generation circuit, 8a... ...Selection signal, 9...Ignition coil, 10...Ignition signal selection circuit, 10a...
...Ignition signal, 11...Power circuit, 11a...Power-on reset signal.

Claims (1)

[Scope of Claims] 1. A calculation ignition circuit that inputs output signals from a sensor that detects the operating state of the internal combustion engine and a starter switch of the internal combustion engine, calculates appropriate ignition timing, and outputs a calculated ignition signal; A fixed ignition signal generation circuit that outputs a fixed ignition signal to ignite at a predetermined fixed ignition timing to be used when the calculated ignition circuit fails or when a starter switch is turned on; input, and determines whether or not the calculated ignition signal and the fixed ignition signal each form a pair, thereby determining whether or not there is a failure in the calculation ignition circuit, and outputting a failure detection signal. An ignition circuit failure detection circuit, which inputs a failure detection signal from the computational ignition circuit failure detection circuit and an output signal from the starter switch, and determines whether the computational ignition circuit is determined to be malfunctioning or whether the starter switch is turned on or not. An ignition signal selection circuit that selects a fixed ignition signal when either one occurs, selects a calculated ignition signal otherwise, and outputs the selected ignition signal; inputting said selected ignition signal; a drive circuit that outputs a signal for driving the ignition coil of the internal combustion engine; and a power supply that supplies power to each of the circuits and initializes each of the circuits when the power supply starts. An ignition timing control circuit for an internal combustion engine that includes a device.