JPS6350732B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a microprocessor motion analysis device that allows selection of motion analysis modes. The apparatus according to the present invention is used for program analysis, operation check, failure diagnosis, etc. of microprocessor applied equipment such as logic analyzers, microprocessor analyzers, incircuits, emulators, etc.

[Prior art and problems to be solved by the invention]

Conventionally, this type of device has a trigger comparison circuit that compares signals from the data bus, address bus, and control bus of the microprocessor 1 of the system under test with preset comparison conditions, as shown in FIG. 5, a match pulse (hereinafter referred to as a trigger signal) is generated when the signal states of the data bus, address bus, and control bus match the comparison conditions.

On the other hand, the memory control circuit 4 generates a clock for the address counter 3 and a write signal for the memory 2 based on the signals on the control bus of the microprocessor 1. The start signal releases the inhibition of the clock of the address counter 3 and the write signal of the memory 2, and the signal states of the data bus, address bus, and control bus of the microprocessor 1 of the circuit under test are continuously stored in the memory 2. It is written as follows.

When the trigger signal is generated next, the clock of the address counter 3 and the write signal of the memory 2 are inhibited again, and the memory 2 stores the state of the bus of the microprocessor 1 before the generation of the trigger signal. The memorized bus status is converted into a hexadecimal code or a mnemonic code for the microprocessor 1 of the system under test, and displayed on a display device such as a CRT. You can see the order in which instructions are executed, which allows you to discover program errors and analyze processor behavior.

In this case, the storage memory stores the bus status continuously and sequentially, so all execution statuses of interrupt processing routines and subroutines are also stored. However, when discovering program errors or analyzing processor operation, In many cases, there is no need to remember the execution state of the program in the interrupt handling routine or subroutine (for example, if the interrupt handling routine or subroutine has already been analyzed, there is no need to analyze it anew). In some cases, the extra stored data may actually make it difficult to analyze the motion.

In other words, when you want to analyze the main routine, the interrupt handling routine and the program execution state in the subroutines are stored, making it difficult to analyze the operation of the main routine. Most of these had the problem that it was very difficult to analyze, such as when the program execution state in interrupt processing routines and subroutines was memorized.

SUMMARY OF THE INVENTION In view of the above-mentioned problems with the conventional system, an object of the present invention is to either perform a continuous storage operation in all areas or to perform an operation in which the execution state of instructions in interrupt handling routines and subroutines is not stored. Based on the idea of allowing the user to make choices, the execution status of instructions can be easily known, making it easier to discover program errors and diagnose failures, and increasing memory usage efficiency.
The purpose of this invention is to enable more effective analysis of the operation of a microprocessor.

[Means for solving problems]

In the present invention, the bus state is connected to the microprocessor of the system under test via an address bus, a data bus, and a control bus, and represents the reference point of the main routine, which is set to a desired value in advance as a comparison condition. A main routine reference comparison circuit that compares the current bus state of the microprocessor and sends out a main routine reference signal to designate the main routine as a reference when the two match, and a data bus and a control bus to the microprocessor. Interrupt, subroutine, and return detection that detects the occurrence of an interrupt and subroutine call and sends out an interrupt/subroutine detection signal, and also detects the execution of a return instruction from an interrupt or subroutine and sends out a return detection signal. Receives signals sent from the circuit, the main routine reference comparison circuit, and the interrupt, subroutine, and return detection circuits, identifies the nesting level of the subroutine, and sends a storage prohibition signal when an interrupt processing routine or an instruction within the subroutine is executed. A selection designation switch is provided, which is inserted into a connection path between the nesting counter and a memory control circuit for controlling the memory, and is turned on and off based on the selection of the microprocessor operation analysis mode. When a selection is made to exclude the execution state, the behavior of the system under test can be analyzed without storing the microprocessor bus state and instruction execution process during execution of an interrupt processing routine or subroutine. Provided is a microprocessor behavior analysis device that is capable of selecting a behavior analysis mode characterized by the following characteristics.

〔Example〕

FIG. 1 shows a microprocessor operation analysis apparatus capable of selecting an operation analysis mode as an embodiment of the present invention. In the device shown in FIG. 1, 1 is a microprocessor of the system under test, 2 is an address bus of the microprocessor 1 of the system under test,
A memory 3 stores the signals of the data bus control bus, and 3 is a counter that specifies the address of the memory 2.

4 is a memory control circuit that generates a write pulse for memory 2 and a clock for address counter 3; 5 is a memory control circuit that compares a trigger comparison condition set in advance to a desired value with the bus state of microprocessor 1 and determines whether they match. Trigger comparison circuit 6 outputs a trigger signal when the current bus status of microprocessor 1 is compared with the bus status (comparison condition) representing the reference point of the main routine, which has been set to a desired value in advance, and determines that they match. When this happens, the main routine reference comparison circuit outputs a main routine reference signal that designates that point as the main routine and as a reference.

7 is an interrupt, subroutine, or return detection circuit that detects the occurrence of an interrupt and a subroutine call, outputs an interrupt or subroutine detection signal, detects execution of a return instruction from an interrupt or subroutine, and outputs a return detection signal; 9 is an interrupt processing routine and a nesting counter for outputting a storage inhibit signal when an instruction in a subroutine is executed, and a nesting counter that identifies the level of nesting of a subroutine; 9 is an interrupt processing routine and a bus state when an instruction in a subroutine is executed; This is a switch that allows the user to select whether or not to store the information.

The operation of the FIG. 1 apparatus will now be described. When the switch 9 is off, the bus state of the microprocessor 1 of the system under test is continuously memorized by the same operation as the conventional device.

When switch 9 is on, trigger comparison circuit 5
A trigger comparison condition for terminating the storage operation is set in the main routine reference comparison circuit 6, and a main routine reference comparison condition for determining the main routine to be stored is preset in the main routine reference comparison circuit 6.

Next, when a start signal is applied to the memory control circuit 4 and the main routine reference comparison circuit 6, the memory control circuit 4 supplies a write pulse to the memory 2 and a clock to the address counter 3, and the bus state of the microprocessor 1 is changed to the memory. Meanwhile, the main routine comparison circuit 6 starts comparing the main routine reference comparison conditions with the bus state of the processor 1. When the main routine reference comparison condition and the bus state of the processor 1 match, the main routine reference signal is turned on and the nesting counter 8 becomes ready for counting.

The nesting counter 8 is an up/down counter, and counts up in response to the interrupt subroutine detection signal generated by the interrupt subroutine/return detection circuit 7, and counts down in response to the return detection signal. Further, the storage prohibition signal, which is output only when the value of the nesting counter is φ, is turned off and the storage operation is performed, and when the value is other than φ, the prohibition signal is turned on and the storage operation is prohibited. That is, when an interrupt or a subroutine call instruction is executed after the main routine reference comparison condition and the bus state of processor 1 match, the nesting counter 8
counts up to 1 and storage operation is prohibited.

Next, when an interrupt or a resane instruction from a subroutine is executed, the nesting counter 8 counts down to φ and the storage operation is restarted again. If there is another subroutine within the interrupt processing routine or subroutine, that is, if the subroutines are nested, the value of the nesting counter will be incremented by 1 each time an interrupt or subroutine call instruction is executed.
Each time the return instruction of each subroutine is executed, it is decremented by 1.

When the first return instruction corresponding to the interrupt processing routine or subroutine is executed after the main routine standard comparison condition is satisfied, the value of the nesting counter 8 becomes φ again and the storage operation is restarted.

FIG. 2 shows the value of the nesting counter and the portion stored in the memory when subroutines are nested.

In FIG. 2, the routine on the left (hatched) is the main routine, the routine in the center is subroutine A, and the routine on the right is subroutine B. Only the main routine is stored in memory.

As mentioned above, after the value of the nesting counter becomes φ and the storage operation is resumed, when an interrupt or subroutine call instruction is executed again, the same operation as above is repeated, and the bus state of microprocessor 1 is compared with the trigger. The memory 2 intermittently stores the bus state until the trigger comparison circuit 5 generates a trigger signal and the storage operation finally ends.

FIG. 3 shows a comparative example of a bus state 2A stored in the memory when the switch 9 is off and a bus state 2B stored when the switch 9 is on. The operation of the above device shown in FIG. 1 is shown in a flowchart as shown in FIG.
It will look like Figure 5.

FIG. 7 is a diagram showing an apparatus for performing a microprocessor operation analysis method as another embodiment of the present invention, and the same reference numerals as in FIG. 2 have the same functions. Here, 10 detects the execution of an interrupt and subroutine and outputs it to the return address comparison circuit,
It is also an interrupt subroutine detection circuit that generates a strobe pulse to store a return address from an interrupt and subroutine in a return address storage register. A return address storage register 11 stores return addresses of interrupts and subroutines and outputs them as a comparison condition signal to a return address comparison circuit. Reference numeral 12 denotes a return address comparison circuit that compares the return address stored in the return address storage register 11 with the state of the address bus of the microprocessor 1 and outputs a storage signal of the memory 2.

The operation of the FIG. 7 apparatus will now be described. When the switch 9 is on, a trigger comparison condition for terminating the storage operation is set in advance in the trigger comparison circuit 5 as in the device shown in FIG. 2, and a start signal is applied to the memory control circuit 4 and the return address comparison circuit 12. do. The memory control circuit 4 starts supplying a write pulse to the memory 2 and a clock to the address counter 3, and the bus state of the microprocessor 1 is stored in the memory 2.

Next, when an interrupt or subroutine call instruction is executed, the interrupt or subroutine detection circuit outputs a strobe signal of the return address of the interrupt or subroutine to the return address storage register 11, and the return address storage register 11 receives the interrupt or subroutine from the interrupt or subroutine. The return address is stored and output as a comparison condition for the return address comparison circuit 12.

On the other hand, the interrupt subroutine detection signal is output to the return address comparison circuit 12, and the return address comparison circuit 12 outputs a storage prohibition signal and also compares the state of the address bus of the microprocessor 1 with the return address stored in the return address storage register 11. Starts the comparison operation. The memory control circuit 4 prohibits the write pulse to the memory 2 and the clock to the address counter 3 by the storage inhibit signal, and the storage operation is interrupted.

Next, when an interrupt or a return instruction from the subroutine is executed and the return address is output to the address bus of the microprocessor 1, the return address comparison circuit 12 turns off the storage inhibit signal and resumes the storage operation.

The above operation is repeated every time an interrupt or subroutine call instruction is executed, and when the bus state of the microprocessor 1 matches the trigger comparison condition, the storage operation is finally completed. In the device shown in FIG. 7, the bus status during execution of the interrupt processing routine and subroutine is not stored, so program analysis and processor operation analysis can be performed appropriately.
It is easy to discover mistakes and malfunctions. FIG. 7 shows a flowchart of the operation of the apparatus as shown in FIG. 8.

〔Effect of the invention〕

According to the present invention, the user can select either full continuous storage operation or operation in which the instruction execution state in interrupt processing routines and subroutines is not stored.
The execution status of instructions can now be properly known,
Program errors can be discovered and failures diagnosed appropriately, memory usage efficiency can be improved, and microprocessor operation analysis can be performed more advantageously.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a microprocessor operation analysis device as an embodiment of the present invention, FIG. 2 is a diagram explaining the relationship between the main routine and subroutines in the operation of the device shown in FIG. 1, and FIG. 1 is a diagram showing the bus status stored in the memory in the device; FIGS. 4 and 5 are flowcharts showing the operation flow of the device in FIG. 1; and FIG. 6 is a diagram showing the configuration of a conventional diagnostic device. It is. 1...Microprocessor of the system under test,
2...Memory, 3...Address counter, 4...
Memory control circuit, 5...Trigger comparison circuit, 6...Main routine reference comparison circuit, 7...
Interrupt, subroutine, return detection circuit, 8
... Nesting counter, 9 ... Changeover switch, 10 ... Interrupt subroutine detection circuit,
11... Return address storage register, 12... Return address comparison circuit.

Claims (1)

[Scope of Claims] 1. A bus connected to the microprocessor of the system under test via an address bus, a data bus, and a control bus, and representing a reference point of a main routine that is set in advance to a desired value as a comparison condition. a main routine reference comparison circuit that compares the current bus state of the microprocessor with the current bus state of the microprocessor, and when the two match, determines that the main routine is the main routine and sends out a main routine reference signal as a reference; Interrupts, subroutines, which are connected via a control bus, detect the occurrence of an interrupt and a subroutine call, and send an interrupt/subroutine detection signal, and also detect the execution of a return instruction from an interrupt or subroutine and send a return detection signal. It receives signals sent from the return detection circuit, the main routine reference comparison circuit, and the interrupt, subroutine, and return detection circuits, identifies the nesting level of the subroutine, and generates a storage prohibition signal when executing an interrupt processing routine or an instruction within the subroutine. A nesting counter that sends out a signal, and a selection designation switch that is inserted into a connection path between the nesting counter and a memory control circuit for controlling the memory and is turned on and off based on the selection of the microprocessor operation analysis mode, When a selection is made to exclude the internal instruction execution state, the operation analysis of the system under test is performed without storing the microprocessor bus state and instruction execution process during execution of an interrupt processing routine or subroutine. A microprocessor behavior analysis device capable of selecting a behavior analysis mode, characterized in that: