JPS6350267A - Automatic linearity correction circuit - Google Patents

Abstract

PURPOSE:To freely and automatically correct the nonlinearily characteristic of a video transmission system to a linearity characteristic by sampling a linearity correction reference signal included in a video signal and generating a reference voltage continuouslly setting the correction range of linearity. CONSTITUTION:When an input video signal Si obtained by applying white compression or white expansion to its original signal is given, a pulse generator circuit 2 samples reference signals and converts them into pulse signals P1, P2 and P3. Reference signal detection circuits 3-1-3-3 take out high frequency signals superimposed with stepped waves included in the outputs of buffer amplifiers 8-1-8-3, and transmit DC outputs Vdo1-Vdo3. After comparison amplifiers 4-1-4-3 compare said outputs Vdo1-Vdo3 with the reference voltage Eb, said outputs are given to gain control circuits 6-1-6-3 and gain control signal switch circuits 5-2-5-4. In such a way a transmission system with any nonlinearily characteristic can be automatically corrected to linearily.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an automatic linearity correction circuit for video transmission using continuous polygonal line approximation in a video analog optical transmission system or the like.

(Prior art) Conventionally, as a technology in this field, video analog transmission technology <1985-1) OPlus E, Yutaka Miura,
There was something described in P2O. The configuration will be explained below.

Conventionally, in a video/analog optical transmission system using an analog direct modulation method in which an input video signal is amplified and a drive circuit outputs an optical signal from a light emitting element, an optical semiconductor element such as a light emitting diode (LE[)] is used as the light emitting element. In some cases, the nonlinearity of the optical semiconductor device becomes a problem. Therefore, in conventional circuits, 1, diodes and field effect transistors CF
A distortion circuit consisting of a non-linear element such as ET is provided, and the circuit applies a distortion opposite to that of the optical semiconductor element to the input video signal in advance to achieve linearity.
was corrected.

(Problem to be solved by the invention) However, in the circuit with the above configuration, the non-linear characteristics in the optical transmission system are known in advance, and a bri-distortion circuit having characteristics opposite to the non-linear characteristics is inserted to correct the linearity. Therefore, there were problems in that it was not possible to apply a wide range of corrections to transmission systems with arbitrary nonlinear characteristics, and automatic correction was also impossible.

The present invention 1 provides an automatic linearity correction circuit that solves the problems of the prior art 1 and tj, which are the lack of versatility and the inability to perform automatic correction.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides an automatic linearity correction circuit for video transmission that automatically corrects non-linear characteristics in an optical transmission system etc. to linear characteristics. A pulse generation circuit for extracting a reference signal consisting of a high frequency signal inserted at a specific position between the vertical blanking JIIJ in the first contest signal or before the staircase wave for correction of nearness, and each staircase wave of the reference signal. a bias circuit that generates a small number of reference voltages corresponding to the reference voltage; a plurality of limiter circuits whose limiting ranges are determined by the reference voltage; and outputs in the linear region of these limiter circuits are adjusted by comparing with the reference signal. This system is provided with a plurality of FFR control devices and a mixing circuit that mixes each signal whose gain has been controlled by these gain control devices.

(Function) According to the present invention, since the automatic linearity correction circuit is configured as described above, the pulse generation circuit extracts the reference signal for linearity correction from the video signal and generates a pulse signal corresponding to it, and the bias circuit generates a reference voltage that continuously determines the linearity correction range to determine the limit range in the limit circuit. The gain control device adjusts the linear region output of each limiter circuit based on a reference signal for linearity correction, and outputs an output signal through the mixing circuit. In addition, the non-linear characteristics of the transmission system can be arbitrarily and automatically corrected to linear characteristics.

Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a circuit diagram of an automatic linearity correction circuit showing an embodiment of the present invention.

This automatic linearity correction circuit includes an input amplifier 1 that amplifies an input video signal S1, and a linearity correction circuit that amplifies an input video signal S1.
A pulse generation circuit 2 extracts the L signal and generates a plurality of pulse signals P1 to P, and on the output side of the pulse generation circuit 2, a plurality of reference signal detection circuits 3-1 to 3-n,
Comparative amplifiers 4-1 to 4-n and gain control signal switch circuits 5-2 to 5-n are connected. Base/signal detection circuits 3-1 to 3- "1 is a circuit that detects the base signal in the input video signal Si based on each pulse signal @P 1 to Pn, and comparator amplifiers 4-1 to 4- n is a circuit that compares the reference voltage Eb with the output of each of the reference signal detection circuits 3-1 to 3-n and outputs a corresponding signal, and gain control signal switch circuits 5-2 to 5-n are each comparison amplifier. 4-2 to 4-n, each of the previous comparison amplifiers 4-1 to 4-(
This circuit is turned on and off by the output of n-1).

A plurality of gain control circuits 6- are provided on the output side of the input amplifier 1.
1 to 13-n are connected in parallel, and each gain H
A resistor 7-1 is provided on the output side of the il control circuits 6-1 to 6-n.
~7-01 Buffer amplifiers 8-1 to 8-11 and resistors 9-1 to 9-n are connected in series. The gain control circuits 6-1 to 6-0 change the output gain (q) of the input amplifier 1 based on the respective outputs of the comparison amplifier 4-1 and the switch circuits 5-2 to 5-n. Resistor 7-1
7-rl to buffer amplifiers 8-1 to 8-n. Here, comparison amplifiers 4-1 to 4-n,
Switch circuits 5-2 to 5-n, and control circuit 6-
1 to Gn constitute a control device. On the input side of each buffer amplifier 8-1 to 8-n, ideal diode circuits 10-10 and 10-11 to 1O-n (n-1
), 1O-nn, and a bias circuit 11 is connected thereto. The bias circuit 11 includes ideal diode circuits 10-10, 10-11 to 1O-n(n-1),
Biken voltage V at 1O-nn. , ■1 to \'n-1, ■, respectively. In addition, each buffer amplifier 8
An output amplifier 12 is connected to the resistors 9-1 to 9-n on the output side of -1 to 8-n. Resistor 9-1
.about.9-n and the output amplifier 12 mix the gain-controlled outputs of each of the buffer amplifiers 8-1 to 8-n to produce an output video signal S. (to send out) grain oil as a kneading circuit.

FIG. 2 shows n=1 in the pulse generation circuit 2 shown in FIG.
It is a waveform diagram of each part in the case of 0. The input video signal Si to the pulse generation circuit 2 has a vertical synchronization period, an equalization pulse period,
and a vertical blanking period, and a high frequency signal of the same level as the floor Q wave is superimposed on the floor Q wave, or a single signal is inserted at a predetermined position in the vertical blanking period. The pulse generation circuit 2 handles each staircase wave in the reference signal and outputs them in the form of pulse signals P1 to P10.

FIG. 3 is a circuit diagram showing an example of the configuration of the basic ship signal detection circuit 3-n in FIG. 1. This reference signal detection circuit 3-n
are the output of the buffer amplifier 8-n and the pulse signal P. This is a circuit that handles the high frequency signal superimposed on the staircase wave in the reference signal, and includes a band pass filter (BPF) 3^, a rectifier circuit (RFC) 3B, and a low pass filter (LPr) 3.
C, and a sample and hold circuit (St()).The input video signal required for the output of the buffer amplifier 8-n passes through a band-pass filter product and a high-frequency signal superimposed on a staircase wave is extracted. The high-frequency signal is rectified by a rectifier circuit 3B, smoothed by a low-pass filter 3C, and applied to a sample-hold circuit 3D.In the simple-hold circuit 3D, a pulse signal for a sample pulse as shown in FIG. The input DC level for a period corresponding to P is held, and the output vdon is compared with the amplifier 4-n.
supply to.

FIG. 4 shows the gain control signal switch circuit 5- in FIG.
This figure shows an example of the configuration of n.
2) is a diagram showing the operation.

This gain 1q control signal switch circuit 5-() compares the output signal Vdan of the comparison amplifier 4-n with the output signal 2 of the gain control signal switch circuit 5-(n-1).
- Equipped with a level detection circuit 5A and a switch 5B whose conduction state of the terminals 5B1 and 582 is switched depending on the level thereof and the output of the detection circuit 5A. In this circuit, Figure 4 (2)
As shown in , when the levels of the signals vdan and V, Qn-1 are within the set range, the switch 5B does not operate and the signal V
dan is applied to the control circuit 6-n through the terminal 582. Conversely, when the levels of the signals dan and VM n-1 are outside the set range, the switch 58 is switched and the signal V is applied to the gain control Qn-i circuit 13-n through the terminal 581.

Figure 5 shows the ideal diode circuit 1o-io in Figure 1.
~1O-nn and a circuit diagram rs showing a configuration example of the bias circuit 11. The ideal diode circuit 1o-io is composed of an amplifier 10 and a diode DIO. Similarly, other ideal diode circuits 1o-i1 to 10- songs are
Normal amplifiers A11-Ann and diodes D11-Dn
n'' (- consists of these ideal diode circuits 10-10 to 1O-nn with a reference voltage of 1V. to V.

The bias circuit 11 that applies a reference voltage (V). A plurality of voltage dividing resistors Rb are connected in series between Rb and ground potential.
It is composed of 1 to "bn.

Figures 6 (1) and (2) show the ideal diode circuits 1O-nn and 1O-n (n-1) in Figure 5, where (1) is the circuit diagram and (2) is the circuit diagram. is an operating waveform diagram. One ideal diode circuit 10nn is a forward diode D inserted in series between the input side of the buffer amplifier 8-n and the reference voltage V. , and to the pruritic amplifier. 7.
Similarly, the other ideal diode circuit 1O-n
(n-1) is a reverse diode D (n-1> and an operational amplifier An(n-i) inserted in series between the input side of the buffer amplifier 8-n and the base Q voltage n-1. The operation of the ideal diode circuit 1O-nn is as follows.
The input side voltage of the resistor 7-n is vi, and the output side voltage is V. Then, the voltage. is the reference voltage V. is limited to a voltage approximately equal to . That is, V. When ≧\/, operational amplifier A
The output of nn is swung to the negative side and is connected to diode D. n leads')
I! j L/ sucks current.

On the other hand, when vo>Vo, operational amplifier A. The output of 0 is swung to the positive side and the diode D. 0 is reverse biased and non-29
Become a connoisseur. Therefore, it operates as an ideal diode with extremely small operating resistance. Similarly, ideal diode circuit 1O-n
(n-1) turns off when Vo≧■n-1, and \lO<
It turns on at n-1. Therefore, the two ideal diode circuits 1O-nn and 1O-n(n-1) are
It operates as a limiter circuit with the operating waveform of 2).

FIGS. 7(1) and 7(2) are explanatory diagrams of the operation of FIG. 1, and are shown with n=3 to simplify the explanation. In the case of the input video signal S1 that has undergone white compression, (1) in the same figure shows the input video signal S1 that has undergone white compression, and (2) (input video signal Si that has undergone white expansion)
In the case of 1. Output video transmission @s in the state of tfftl control, the state of control v11 in progress, and the state of 91 control completion, respectively. So2. Waveform of So3, reference signal @ handling pulse P1. P2, P3, base signal λ(
The relationship between DC output Vdon and interest (9 control signals \lρ1 to 13) of one circuit 3-1 to 3-3 is shown.

Ward 7 1. In (2), when the input video signal Si that has undergone white compression or white expansion as the original signal is given to the automatic linearity correction circuit shown in FIG. 1, this input video signal Si is amplified by the input amplifier 1 and gain controlled. Circuit 6-1~G-
At the same time, the reference signal is extracted by the pulse generating circuit 2 to generate the pulse signal P1.3. It is converted into P2 and p3. Each of the reference signal saving λ11 circuits 3-1 to 3-3 takes out the high frequency signal half-converted into a staircase wave from the output of each buffer amplifier 8-1 to 8-3, rectifies and smooths it, and then Based on the pulse signals P1 to P3, sample bold is performed and DC outputs \' d01 to Vdo3 are sent out, respectively.

These 8 DC outputs Vdo1 to Vdo3 are compared with the reference voltage Eb by each comparator amplifier 4-1 to 4-3, and then amplified and sent to gain control circuits 6-1 to G in the form of signals cla1 to ■d and 13. -3 and gain control switch circuit 5-2
~5-4 respectively.

What is the control operation of the limiter circuit output corresponding to each step in the reference signal? The high frequency signal of the first stage of the r-base quasi-signal, the sun and the end signal vda1, is set to y:in W, and the level is adjusted by the gain control circuit 6-1, and the level is adjusted sequentially to a high level (one frequency for each staircase in this direction). signal, i.e. signal Vd
Level matching is performed using gain 1q control signal switching circuits 5-2 and 5-3 and gain control circuits G-2 and 6-3 with reference to a1 to Vda3. Second stage issue 1F1 control signal VQ2
At the start of control, the first stage level dal ””V,Q
1) or the output da2 of the second stage comparison amplifier circuit 4-2 and the first stage gain control signal 01 """Vdal
), the second stage feedback loop gain control signal V,,72 (=Vd
, 12) is controlled by the gain control circuit 6-2. The same goes for the third column, issue 1! At the start of control, the I control signal V, Q3 is equal to the control signal Vf, 2 of the second stage [H, but the output V (In2 and the gain control signal of the second stage) of the comparator amplifier 4-3 in the third stage is equal to Li + signal.

When the level difference between the
It is controlled by a control circuit 6-3.

The outputs of these gain control circuits 6-1 to 6-3 are connected to output amplifiers through resistors 7-1 to 7-3, buffer amplifiers 8-1 to 8-3, and resistors 9-1 to 9-3. The output video signal θSo (=So3) which has been mixed in step 12 and corrected by white compression or white expansion is output. In this manner, in the circuit of this practical example, linearity correction can be automatically performed for a transmission system having any nonlinear characteristic i. Therefore, L.E.
The optical transmission system of the analog direct modulation method, which uses optical semiconductor elements with non-direction and glandular characteristics of D'S, is used for J-circle one-finger operation.

Note that although FIG. 7 above shows the operation for the case of n=3, the same operation is performed for the case of n≧4. 31 diode circuits 10-10, 10-11 to 1O-n (n-1),
Various modifications are possible, such as configuring the bias circuit 11 with a circuit other than 1O-nn, or configuring the bias circuit 11 with a circuit other than the voltage dividing resistors Rbl to Rbo.

(Effects of the Invention) As described above in detail, according to the present invention, since the pulse pulse is provided with the main circuit, the bi-7nos circuit, the limiter circuit, the gain control device, and the mixing circuit, any non-direct characteristic This makes it possible to automatically correct linearity for transmission systems with

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an automatic linearity correction circuit showing an embodiment of the present invention, Fig. 2 is a waveform diagram of each part of the pulse generation circuit in Fig. 1, and Fig. 3 is a reference signal detection circuit in Fig. 1. 4(1) and (2) are circuit diagrams showing an example of the configuration of the gain control signal switch circuit in FIG. 1 and a diagram showing its operation. FIG. A circuit diagram showing the inner J1 diode circuit and bias (01 path iM configuration 19) i, FIG. 6(1). (2) (shows the circuit diagram of the ideal D1'ode circuit in Fig. 5 and its operating waveform diagram, and Fig. 7 (1) and (2) show the input video signal Si undergoing white compression and white expansion. 1 is an explanatory diagram of the operation in the case of FIG. 1. 2...Pulse generation circuit, 3-1 to 3-n...
...Group 4 (signal detection circuit, 4-1 to 4-n...
・Comparison amplifier, 5-2 to 5-1)...Gain control signal switch circuit, 6-1 to 13-n...Gain 1
7 control circuit, 10-10, 10-! 1~1O-n(n
-1). 1O-nn...Physical P1 diode circuit, 11.
...Bias circuit, 12... Output amplifier. Applicant's agent Yasushi Kakimoto Waveform diagram of each part of the pulse signal generation circuit in Figure 1 Figure 2 Figure 3 Circuit operation Gain side # signal switch circuit in Figure 1 Ideal diode circuit in Figure 1 and Iasu circuit 5th
Ideal diode circuit Figure 6 in Figure 5 of the circuit diagram

Claims (1)

[Claims] 1. A pulse generation circuit for extracting a reference signal consisting of a high frequency signal superimposed on a staircase wave inserted at a specific position in a vertical blanking period in a video signal, and each staircase wave of the reference signal. a bias circuit that generates a plurality of reference voltages corresponding to the reference voltage; a plurality of limiter circuits whose limiting ranges are determined by the reference voltage; and a linear region output of these limiter circuits that is adjusted by comparing with the reference signal. An automatic linearity correction circuit comprising: a plurality of gain control devices; and a mixing circuit that mixes signals gain-controlled by the gain control devices. 2. The gain control device adjusts the gain of the output of the corresponding limiter circuit based on the high frequency signal superimposed on the first stage of the staircase wave, and the gain control signal for the second and subsequent stages is initially adjusted to the gain of the previous stage. Using the control signal as it is, compare it with the gain control signal generated by the high frequency signal corresponding to the staircase wave, and if the difference between them is within the set value, the gain generated by the high frequency signal corresponding to the staircase wave. 2. The automatic linearity correction circuit according to claim 1, wherein the gain is adjusted by switching to a control signal, and the gain is adjusted sequentially toward a higher level. 3. The automatic linearity correction circuit according to claim 1, wherein the limiter circuit is constituted by an ideal diode circuit including an operational amplifier and a diode.