JPS634995B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording control method applied to a facsimile recording apparatus and the like.

In recent facsimile machines, a thermal head is used as a printing means, and this head has a structure as shown in FIG. 1, for example. For convenience of explanation, this figure 1 shows the case where one line consists of 40 dots, and 40 dots are arranged in one row.
The heating elements R ₁ to _{R 40} are divided into 10 blocks of 4 each with m ₁ to m ₁₀ as common selection terminals,
And these 10 blocks are na ₁ ~ na ₄ and nb ₁ ~
Two groups with nb ₄ as their respective recording input terminals
It is divided into G ₁ and G ₂ .

To record using such a head, first
Input terminal for recording signal corresponding to block of group _G1
Recording signals corresponding to the blocks of the _second group _G2 are applied in parallel to the input terminals nb1 to nb4 of _na1 to _na4 , 4 bits each, and to the selection terminals _m1 to _m10.
first m ₁ and m ₆ , then m ₂ and m ₇ , then m ₃
It is sufficient to simultaneously apply the selection signal to two blocks selected one block from each group, such as m8 and _m8 . That is, in this case, recording for one line is completed by performing the recording operation of 4 bits/1 block 5 times in 2 blocks each, so the head in Fig. 1 is recorded 10 times in 1 block without dividing into groups. The recording time is reduced to 1/2 compared to the case where the operation is performed.

However, when recording is carried out using the method described above on recording paper that is being fed in a direction perpendicular to the head in Figure 1, the recording traces created by each block of the head will be as shown in Figure 2a, resulting in two The recording interval d ₀ between groups is much larger than the recording interval d ₁ within each group.
For this reason, the horizontal line appears to be cut at the distance d ₀ and cannot be regarded as one continuous line.

Therefore, as an alternative method,
As shown in Publication No. 158774, the selection terminal in Figure 1
For m ₁ to _{m 10} , first m ₁ and m ₁₀ , then m ₂ and m ₉ , then m ₃ and m ₈ , so that the block selection order in each group is reversed. A method has been proposed in which a selection signal is applied.

According to this method, the recording trace by each block becomes as shown in FIG. 2b, and therefore, there is no substantial recording interval between the two groups. However, on the other hand, since the block selection order in each group is reversed, the input terminals na ₁ to _{na 4} receive signals from the recording signal corresponding to the leftmost block of the first group G ₁ . On the other hand, it is necessary to apply the recording signals corresponding to the rightmost block of the second group _G2 to nb ₁ to nb ₄ first. This means that the address specification when reading recording signals from the line memory must be made in opposite directions for each group, which has the disadvantage that the control circuit for the memory becomes complex. This is especially true when a line has a large number of elements, such as an actual thermal head for facsimile, and is divided into a large number of groups to shorten the recording time. It becomes a problem.

Therefore, the present invention has been made in consideration of these points, and details thereof will be explained below with reference to FIGS. 3 to 9.

FIG. 3 shows an example of a thermal head used in the present invention, and for convenience of explanation, one line is made up of 80 dots. The head in the figure has 80 heating elements R ₁ , similar to the one in Figure 1.
~ _R80 is divided into a total of 20 blocks of 4 blocks each, and the 20 blocks are divided into 4 blocks of 5 blocks each.
It is divided into two groups _G1 to _G4 .

On the other hand, FIG. 4 shows a control circuit for the head. In the figure, numerals 1 and 2 are two line memories in which one line (i.e., 80 bits) of recording signals introduced into the input terminal _T1 are alternately written via the first switch 3. be. When writing to this memory, the address counters 4 and 5, which are reset for each line by the recording start signal (FIG. 5A), are directly driven by the clock signal, so that the recording signal is transferred to the memory. One bit at a time is sequentially written starting from address 1.

Reference numeral 6 designates an address counter control circuit for addressing the memory switched to the read side among the memories 1 and 2 in a predetermined order, which will be described later.
5, the counter on the side connected by the second switch 7 is controlled.

Next, 8 is a shift register into which the recording signal read from one of the memories 1 and 2 is introduced via the third switch 9, and each group G 1 to G ₁ in FIG. Recording signals of 4×4=16 bits are stored, which are simultaneously applied to each heating element in four blocks selected one block at a time from _G4 .

Further, 10 is a parallel output of the shift register 8 each time the shift register 8 is stored as described above.
It is a latch circuit that latches S ₁ to S ₁₆ for a certain period of time.
Each latch output passes through the recording driver circuit 11 to a total of 16 recording input terminals, na ₁ to na ₄ , nb ₁ to nb ₄ , nc ₁ to nc ₄ , and nd ₁ to _{nd 4} in FIG. , are applied in this order.

Further, 12 is a circuit that creates a selection signal that is sequentially switched at the timing when the latch circuit 10 operates (FIG. 5 (e)), and each output d ₁ to _{d 5} of this selection signal creation circuit 12 is a selection driver circuit. 13 to the common selection terminals m ₁ to _{m 20} in FIG. 3 as will be described later.

Now, the circuit shown in FIG. 4 has a feature in controlling the transfer of recording signals from the line memories 1 and 2 to the shift register 8, and the control method will be explained next with reference to FIGS. 5 and 6. do.

First, in the first address designation after the start of reading from the line memory 2 [or 1], the address counter control circuit 6 controls the address counter 5 so that the address designation of the memory starts from address 1. Give instructions to [or 4]. As a result, when this counter specifies addresses 1 to 4 by the clock signal, the control circuit 6 then causes the previous address counter to skip to address 21. As a result, this counter will now start from address 21.
Specify up to 24 addresses. Similarly, addresses 41 to 44 will be specified next, and addresses 61 to 64 will be specified next. (See Figure 6). From this address counter control circuit 6 to the address counter 5
The instruction signals for addresses 1, 21, 41, and 61 sent to [or 4] are shown in FIG. 5B. Note that FIGS. 5C and 5D represent the operating modes of the line memories 1 and 2.

4 read from each address of line memory 2 [or 1] by this first addressing.
A recording signal of x4=16 bits is introduced into the shift register 8 of FIG. Therefore, as can be seen from the above explanation, in this case, the recording input terminal na ₁ in FIG.
The recording signal applied to ~nd ₄ is the common selection terminal
Each group G ₁ ~ connected to m ₁ , m ₆ , m ₁₁ , m ₁₆ respectively
It corresponds to each block on the left end of _G4 . At this time, the selection signal d ₁ (FIG. 5) is derived from the selection signal generating circuit 12, and this signal is applied to each of the common selection terminals. That is, in this case, each block at the left end of each group _G1 to _G4 in FIG. 3 is selected, and each heating element in the four selected blocks performs recording at the same time.

Next, when specifying the address for the second time, the address counter control circuit 6 initially instructs the address counter 5 [or 4] so that the address specification starts from address 17, as shown in FIG. give. As a result, this counter now specifies addresses 17 to 20, and then the control circuit 6 specifies addresses 37 to 20.
When skipped to an address, specify addresses 37 to 40. In the same way, next from address 57 to 60
Finally, addresses 77 to 80 are specified. Address counter control circuit 6 in this case
The instruction signal from is shown in FIG. 5B as in the previous case.

The recording signal read out from the line memory 2 [or 1] by this second addressing is also introduced into the shift register 8 in the same manner as described above. Therefore,
As can be seen from the comparison between Fig. 6 and Fig. 3, the recording signals applied to the recording input terminals na ₁ to nd ₄ in this case correspond to the rightmost blocks of each group G ₁ to G ₄ in Fig. 3. It has become something to do. At this time, the common selection terminals m ₅ , m ₁₀ ,
A selection signal is sent to m ₁₅ and m ₂₀ from the selection signal generation circuit 12.
d ₂ (Figure 5G) is applied. That is, in this case, the rightmost blocks of each group are selected, and recording is performed simultaneously using these four blocks.

In addition, when specifying addresses for the third time, the addresses of line memory 2 [or 1] are specified in the same order as shown in FIG. Each block is selected and recording is performed by each block. Similarly, the fourth and fifth addressing operations are performed in the order shown in Figure 6, and the fourth address designation is performed two times from the right end of each group.
Recording is performed by each block of the fifth block.
In each round, recording will be performed by the central block of each group.

Therefore, if the blocks in each group G ₁ to _{G 4} in FIG. 3 are called B ₁ , B ₂ , B ₃ , B ₄ , B ₅ from the left end, each Block is B ₁ →
One block is selected in the order of B ₅ →B ₂ →B ₄ →B ₃ , and recording is sequentially performed using each of the four selected blocks. That is, the control circuit shown in FIG. 4 is characterized in that the block selection order is selected as described above.

When recording for one line is performed in this manner, the recorded trace becomes as shown in FIG. In the diagram
G ₁ to G ₄ represent each group of heads (Fig. 3), and B ₁
〜B ₅ represents the blocks within each group, respectively,
... indicates the block selection order. As can be seen from this figure, the recording interval d ₀ between each consecutive group is about the same size as the recording interval d ₁ , d ₂ within each group (i.e.,
d ₀ = d ₂ = 2d ₁ ). That is, the recording interval d ₀ between adjacent groups does not become extremely large as shown in FIG. 2a. Incidentally, when recording is performed using the head shown in Fig. 3 by the method described above on recording paper that is fed at a speed of 7.7 lines/mm, the above-mentioned recording interval d ₀ is d ₀ = 1/7.7 x 1. /5×2≒52 μm, and d ₀ = when using the recording method shown in Figure 2 a mentioned above.
It is sufficiently small compared to 1/7.7≒131 μm and is not noticeable to the naked eye.

In addition, the recording interval d ₀ between each group in the case of Fig. 7 is
Recording interval d ₁ within the same group in case of Figure 2 a or b
(That is, in the model described above, d ₁ ≈26 μm), but since the recording interval generally becomes noticeable to the naked eye from about 70 μm, there is no problem at all.

Therefore, from this point of view, in addition to the above-mentioned order of B ₁ →B ₅ →B ₂ →B ₄ →B ₃ , the above-mentioned block selection order also includes the order shown in FIG. Conceivable. That is _, as can be seen from FIG. 9, which shows the recording trace when blocks are selected in the order shown in _FIG . Recording interval between each group
Considering the number of groups of recording heads and the number of blocks, the block selection order is set in a discrete order so that d ₀ is so large that it is not noticeable to the naked eye (that is, the above-mentioned distances are about 70 μm or less). Therefore, it is sufficient to select .

As explained above, the recording control method of the present invention is
A large number of recording elements divided into a plurality of groups and further divided into a plurality of blocks within each group are arranged in a line in a direction perpendicular to the running direction of the recording paper, and one block is selected from each group. When a plurality of selected blocks are simultaneously driven and each block is sequentially selected, one block from each group is recorded.
The block selection order in which blocks are selected one by one is common to each group, and the blocks within each group are discretely selected so that the recording interval within the same group and between each connected group is below a certain value. Since the order is set in such a manner that the printing interval is set in such an order that it is not noticeable to the naked eye, both within each group and between each group, the recording interval in the recording paper running direction can be made small enough to be unnoticeable to the naked eye. Moreover, since the above block selection order is determined in common for each group, when reading a recording signal from the memory and applying it to the recording elements of each group, the read address of the memory is specified for each group. Therefore, there is an advantage that the address control circuit for reading the memory can be realized with a relatively simple structure.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a thermal head shown for explaining the conventional recording method, FIG. 2 is a diagram schematically showing a recording trace by the conventional recording method, and FIG. 3 is a diagram of the thermal head used in the present invention. Diagram showing the configuration, Figure 4 is the 3rd
FIG. 5 is a diagram showing the control circuit of the head shown in FIG. 5, its operation time chart, FIG. 6 is a diagram for explaining the operation of the circuit shown in FIG. 4, and FIG. FIG. 8 is a diagram for explaining another embodiment of the present invention, and FIG. 9 is a diagram showing recording traces in each case of FIG.

Claims (1)

[Claims] 1. A large number of recording elements divided into a plurality of groups and further divided into a plurality of blocks within each group are aligned and arranged in a direction perpendicular to the feeding direction of the recording paper,
In this method, a plurality of blocks selected one block at a time from each group are simultaneously driven while the recording paper is running, and recording is performed for each of the sequentially selected blocks. The recording signal is read by specifying addresses in the order of , and one block is selected from each group.The block selection order is common to each group, and the blocks within each group are within the same group and between adjacent groups. 1. A recording control method characterized in that the recording interval is set to be selected discretely so that the recording interval in the section is equal to or less than a certain value.