JPS6349789A - Display device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a display device, and particularly to a display device for converting predetermined display information into a character pattern, outputting it serially, and displaying it on a screen using a rask scan method. used for things.

(Prior Art) Conventionally, predetermined display information (for example, a character code) is given to a conversion unit, this character code is converted into a corresponding character pattern, and the serialized output unit outputs the serialized character pattern. A display device that edits and outputs a screen display signal is known.

FIG. 2 is a block diagram of this type of conventional display device, and the fifth
The figure is a time chart 1- for explaining the operation of the display device shown in FIG.

As shown in FIG. 2, this display device includes a CPU 1 that controls the entire device, a refresh memory 2 that stores predetermined display information (for example, character codes of characters to be displayed on the screen), and a A conversion unit 20 that converts display information into a corresponding pattern signal (a character pattern when the display information is a character code) and outputs it serially; and a conversion unit 20 that edits and outputs the pattern signal (character pattern) from the conversion unit 20. It includes an output section 21 and a control signal generation circuit 22 that provides control signals to the refresh memory 2, conversion section 20ir3, and output section 21.

The CPU 1 operates according to a control program stored in a read-only memory (ROM) (not shown).The refresh memory 2 is, for example, a RAM.
The refresh memory 2 stores predetermined display information (for example, character code) in advance by the CPU 1.

The display information stored in the refresh memory 2 is successively outputted and sent to the conversion section 20 in response to a control signal CO from a control signal generation circuit 22.

The conversion unit 20 includes a character generator 3 that generates a character pattern corresponding to a specific character code when a specific character code is added, and converts the character pattern output from the character generator 3 into parallel/serial data and outputs the serial data. It is made up of one shift register 4. A control signal C1 for controlling the output timing of character patterns is applied to the character generator 3 from the control t+'lfl signal generation circuit 22, and a clock signal C3 for operating the shift register 4 and a control signal C1 from the character generator 3 are applied to the shift register 4. A read signal C2 is applied from the control signal generating circuit 22 to control the timing of reading character patterns in parallel and simultaneously outputting them serially.

The output section 21 consists of an AND circuit 23, to which the output signal of the shift register 4 and the display permission signal C4 from the control signal generation circuit 22 are applied, and these signals are ANDed. and is output as a video signal VD.

Next, the operation of the conventional device shown in FIG. 2 will be explained with reference to time charts 1 to 5 shown in FIG. Refresh memory 2 is CP
The display information (character code) stored in advance by U1 is sent to the gearactor generator 3 of the conversion unit 20 in accordance with the display order based on the control signal @CO. The character generator 3 outputs character patterns corresponding to the display information sent from the refresh memory 2 in parallel based on the control signal C1 (for example, outputs signals Do to D13 of 14 character patterns in parallel).

Shift 1 to register 4 operate according to the lock signal C3 as shown in FIG. 5(a), and when the read signal C2 as shown in FIG. 5(b) changes, the character generator 3
14 character pattern signals Do to D1 output from
3 in parallel.

At the same time, as shown in FIG. 5(d), the character pattern signals Do to D13 are synchronized with the clock signal C3 and sequentially and serially output to the output section 21. The AND circuit 23 of the output section 21 takes the AND of the output signal E serially output from the shift register 4 and the display permission signal @C4, and outputs the result as a serialized video signal VD.

In this way, the video signal VD from the AND circuit 23 is output serially in synchronization with the clock signal C3, so that it is possible to display predetermined characters on the screen using the rask scan method.

[Problem that the invention seeks to solve]

However, in the conventional device described above, one shift register 4 of the conversion section 20 has a key 1? All of the character patterns from the character generator 3 are added in parallel, and the shift register 4 serially converts the character patterns added in parallel into a video signal VD at one υj moment per clock signal period. Since the transfer speed of the video signal VD is the same as the frequency of the clock signal C3 applied to the shift register 4, there is a problem that a faster transfer than that of the clock signal C3 cannot be expected. there were.

In addition, without changing the configuration shown in FIG. 2, an ECL element (EMIT ER-COUPLED LO
It has been proposed to increase the speed by using GIC (GIC), but since there are only a few types of ECl- elements, the number of sets of parts increases to realize one circuit, which increases the cost. There were drawbacks. In general, the operating voltage of ECL elements differs depending on the type of element, making the circuit complicated.
There was a problem in that the current capacity became large, and therefore special measures had to be taken against heat generation.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a low-cost display device capable of transferring 8-pattern signals such as video signals at high speed.

[Means for solving problems]

In the display device according to the present invention, a pattern signal corresponding to display information outputted from a memory is generated within a converting section, and the pattern signal is divided into at least two by the converting section and serially shifted from each other in time. It is characterized in that the divided pattern signals from the conversion section are edited as one serial output signal by the output section.

[Effect]

According to the present invention, since the pattern signal is divided and serially outputted in the conversion section, the speed of parallel/serial conversion of the pattern signal becomes faster in proportion to the number of divisions, and the divided pattern Since the signals q are outputted serially with time shifts from each other, in the output section, these divided serial pattern signals do not overlap with each other in time, and are therefore collected WR as one serial output signal. work.

〔Example〕

The present invention will now be described in detail with reference to FIGS. 1, 3 and 4 of the accompanying drawings.

FIG. 1 is a configuration diagram of a display device according to an embodiment of the present invention, and FIG.
The figure is a circuit diagram of the converter shown in Figure 1, and Figure 4 is a circuit diagram of the converter shown in Figure 1.
Time chart 1 showing the operation of the device shown in Figure 3
It is ~. Note that in FIGS. 1 and 3, parts similar to those in FIG. 2 are denoted by the same reference numerals, and redundant explanation will be omitted.

In the embodiment of the present invention, as shown in FIGS. 1 and 3, the conversion unit 7 includes a character generator 3 and two shift registers 4a to which pattern signals (for example, character patterns) from the character generator 3 are sent. , 4b.

The character generator 3 receives a second signal from the control signal circuit 5.
A control signal C1 similar to the device shown in the figure is added, and this signal C1
controls the output timing of character patterns. Shift 1 to registers 4a and 4b are required as parallel/serial conversion circuits for reading character patterns from character generator 3 in parallel and outputting them serially. The shift registers 4a and 4b receive read signals C10 and C11 and a clock signal C12 from the control signal generation circuit 5, respectively.
, C13 are added. Clock signals C12, C13
Shift register 4a.

4b respectively operate, and shift 1 to registers 4a and 4b read character patterns from character generator 3 in parallel according to read signals C10 and C11, and at the same time,
It is designed to serially output the character pattern that has just been read.

Next, referring to FIG. 3, in this embodiment, the character generator 3 generates a character pattern of 14 dots on the signal bO
to b13, and the shift register 4a receives signals bO1b2 . . . , b12 are added, and the shift register 4b receives the odd-numbered dot character pattern signal b1 . b3°..., b13 are added. Therefore, shift 1 to registers 4a and 4b can each store a character pattern of 7 dots.

In order to operate the shift registers 4a and 4b alternately,
Clock signals C12, C to shift registers 4a, 4b
13, those having opposite polarities are used as shown in FIGS. 4(a) and 4(b), respectively. In other words, the phase is shifted by half a clock cycle. Further, as shown in FIG. 4(C) and (d>), the read signal C1'1 to the shift register 4a is
It is delayed by half a clock cycle compared to the read signal C10. As a result, the character pattern output signal FA serially output from the shift register 4b and the character pattern output signal EB serially output from the shift register 4a are as shown in FIG. 4(f) and l). The signals are output alternately with a shift of half a clock cycle from each other.

Further, in this embodiment, the output section 6 is an AND circuit 7°8.1
0 and an OR circuit 9.

The output signal EA of the shift register 4a and the clock signal C13 are added to the AND circuit 7, and these are ANDed to make the output signal EA a signal with a half-tallock period width.

On the other hand, the output signal [B of the shift 1 register 4b and the clock signal C12 are added to the AND circuit 8, and the output signal [B] and the clock signal C12 are added to the AND circuit 8.
The logical product of these signals is output in order to make EB a signal with a half clock period width.

The respective outputs from the AND circuits 7 and 8 are added to the OR circuit 9, and the output signals from the AND circuits 7 and 8 are added to the OR circuit 9 in order to synthesize the output signals of the character pattern that have been separated into even numbered pips 1 to odd numbered dots. The logical sum of the outputs is calculated and output. The AND circuit 10 also receives the output from the OR circuit 9 and the display permission signal C14 (
4(e)) is added to the OR circuit 9, and in order to make the output signal of the synthesized character pattern into an actual display signal, the output from the OR circuit 9 and the display permission signal are added. The logical product with C14 is taken and the video signal @VDO as shown in FIG. 4(h) is output.

Next, the operation of the above embodiment will be explained. It is assumed that display information (for example, character codes of characters to be displayed) is stored in advance in the refresh memory 2 by the CPU 1.

The refresh memory 2 sends the stored character codes to the character generator 3 in the display order based on the control signal CO. Since the character generator 3 has a dotted character pattern written in correspondence with the character code, the character generator 3 generates the character corresponding to the character code sent from the refresh memory 2 based on the control signal C1. Output the pattern. In the example shown in FIG. 3, the character pattern to be output consists of 14 dot signals bO to b13. Among the character pattern signals of 14 dots 1 to b13 outputted from the character generator 3, seven signals bO1b2 . . . , b12 are added to the shift register 4a, and seven signals b1 . b3. ....

b13 is added to the shift register 4b.

The shift register 4a operates according to the clock signal C12 shown in FIG. 4(a), and when the read signal C10 shown in FIG.゜..., read b12 in parallel. At the same time, the signal bO, which was just read,
b2. . . , b12 are sequentially read out as shown in FIG. 4(f) and serially output as the output signal EA.

On the other hand, the shift register 4b is shown in FIG.
When the read signal C11 shown in FIG. 4 (d>) is applied from the control signal generating circuit 5, the signals b1, b3, . . . , b13 for seven odd-numbered dots are read in parallel. At the same time, the signals b1, b3°, . . . , b13 that have just been read out are sequentially read out as shown in FIG.

As shown in FIG. 4(a) to ff1(d), the clock signals @C12 and C13 are inverted with each other, and the read signals C10 and C11 are shifted by half a clock period, so the shift The register 4a and the shift register 4b operate alternately. Therefore, the output signal EA from the shift register 4a and the output signal EB from the shift register 4b are as follows.
Figure 4(f).

As shown in (Ω), the signals are output alternately with a shift of half a clock cycle. This allows the speed of parallel/serial conversion to be doubled compared to the conventional device as shown in FIG.

Next, in order to synthesize the character pattern signals EA and EB that are output separately in this way to form a video signal VDO, the output signal EA from the register 4a and the shift 1 are sent to shift 1.
~Output signal FB from register 4b is sent to output section 6.

In the output section 6, AND circuits 7 and 8 perform the logical product of the output signals EA and EB and the clock signals C13 and C12, respectively. As a result, the output signals EA and EB are converted to a width of half a clock cycle, and are outputted with a shift of a half clock cycle from each other so that they do not overlap in time. That is, FIG. 4(f)
A signal bQ of a character pattern of an even number of dots as shown in FIG.

b2. ..., b12 is VO12° in Fig. 4 (h).
. . , is converted into a half clock period width as shown as Vl2. Therefore, as shown in FIG. 4(g), the signals b1, b3, . ...,b
13 is similarly shown in FIG. 4 ([)) as Vl, V3.・・・
. . , ■ 13 are converted into a clock having a half clock cycle width.

The signals whose period widths have been converted by these AND circuits 7 and 8 are as follows:
The OR circuit 9 performs a logical sum and outputs it as a serialized signal, and the AND circuit 10 performs a logical sum with the display permission signal C'14 and outputs it as a video signal VDO. The video signal VDO output in this way is, as shown in FIG. 4(h), even-numbered character pattern signals VO, V2 . ..., ■1
2 and odd-numbered dot character pattern signal V1. V3.・
....

It is a combination of Vl3 and Vl3. Therefore, this allows two signals during one clock period, i.e.
O and Vl, V2 and V3. ..., Vl2 and Vl3 can be output serially.

In this embodiment, the character pattern from the character generator 2 is divided and added to the two shift registers 4a and 4b as the even number dots 1 and the odd number dots, respectively. 1~
Since the character patterns for odd numbered dots are output serially with a shift of half a clock cycle from each other, the speed of parallel/serial conversion is doubled. Roughly speaking, the character pattern signals for the shifted even numbered dots and odd numbered dots are converted to half the width and synthesized by half a clock period in the output section 6, so the output is as shown in Figure 2. The video signal transfer rate can be doubled compared to conventional devices.

The present invention is not limited to the above embodiments, and various modifications are possible. That is, in the above embodiment, two shift registers 4a and 4b were used, but in general, two or more shift registers 1 to 4 are used to control the character generator 3.
By further dividing the character pattern from , converting it into parallel/serial, and further narrowing the width of the serialized output signal from these shift registers using an AND circuit, it is possible to produce a higher-speed video signal of 1q. . Also,
By using high-speed ECL elements in each circuit of the above-mentioned embodiments,
It is also possible to create an even faster display device by 1q. Roughly speaking, the above embodiment can be applied not only to a display device for displaying characters on a screen, but also to other display devices, such as a graphic display device.

Furthermore, each control signal generated by the control signal generation circuit 22 is C
It may be generated by the PU 1, or it may be generated in a monologue within the refresh memory 2, conversion section 7, or output section 6.

〔Effect of the invention〕

As described in detail above, in the present invention, a pattern signal generated in response to display information is divided, and these divided pattern signals are outputted serially with a time shift from each other, thereby allowing these divided pattern signals to be output serially. Since the pattern signals are edited as one serial output signal, pattern signals such as video signals can be transferred at high speed, and at the same time, good loss 1 to performance can be coupled.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a display device according to an embodiment of the present invention, and FIG.
The figure is a block diagram of a conventional display device, FIG. 3 is a detailed block diagram of the converter shown in FIG. 1, and FIG. 4 is a time diagram for explaining the operation of the display device shown in FIGS. The chart in FIG. 5 is a time chart for explaining the operation of the conventional display device shown in FIG. 1...CPU, 2...Refresh memory, 3...
・Character generator, 4a, 4b...shift register, 5...control signal generation circuit, 6...output section,
7... Conversion unit, 7,8.9... AND circuit, 9...
・Order circuit.

Claims (1)

[Scope of Claims] 1. A memory for storing display information, and a pattern signal corresponding to the display information stored in the memory is generated, and the pattern signal is divided into at least two parts, and the pattern signals are separated from each other in time. A display device comprising: a converting unit that outputs the pattern signal serially while shifting the target; and an output unit that edits and outputs the pattern signal divided into at least two parts provided from the converting unit as one serial output signal. 2. The conversion unit includes a character generator that generates a character pattern signal corresponding to display information, and a character generator that divides the character pattern signal from this character generator, adds it to the parallel signal, and temporally shifts these divided pattern signals from each other to serialize the character pattern signal. 2. The display device according to claim 1, further comprising a plurality of shift registers for outputting signals to a plurality of shift registers. 3. The output section includes an AND circuit that narrows the width of the divided serial pattern signals from multiple shift registers in proportion to the number of divisions, and a divided pattern signal whose width is narrowed by this AND circuit. 3. The display device according to claim 1, further comprising an OR circuit for editing the video signals into one serial video signal.