JPS6349180B2 - - Google Patents

Info

Publication number
JPS6349180B2
JPS6349180B2 JP6916381A JP6916381A JPS6349180B2 JP S6349180 B2 JPS6349180 B2 JP S6349180B2 JP 6916381 A JP6916381 A JP 6916381A JP 6916381 A JP6916381 A JP 6916381A JP S6349180 B2 JPS6349180 B2 JP S6349180B2
Authority
JP
Japan
Prior art keywords
circuit
horizontal
outputs
shift register
inspected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6916381A
Other languages
Japanese (ja)
Other versions
JPS57184956A (en
Inventor
Seikichi Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP6916381A priority Critical patent/JPS57184956A/en
Publication of JPS57184956A publication Critical patent/JPS57184956A/en
Publication of JPS6349180B2 publication Critical patent/JPS6349180B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84Systems specially adapted for particular applications
    • G01N21/88Investigating the presence of flaws or contamination
    • G01N21/89Investigating the presence of flaws or contamination in moving material, e.g. running paper or textiles

Description

【発明の詳細な説明】 本発明は例えば赤熱スラブ鋼材等の表面に生ず
るスラブ割れ疵を検査する表面欠陥検査装置に係
り、特にたて割れおよびよこ割れ疵のパターン認
識、判別手法を改良した表面欠陥検査装置に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a surface defect inspection device for inspecting slab cracks occurring on the surface of, for example, red-hot slab steel materials, and particularly relates to a surface defect inspection device that has an improved pattern recognition and discrimination method for vertical cracks and horizontal cracks. Related to defect inspection equipment.

スラブの表面疵を熱間において検出することは
省エネルギーおよびスラブの品質保証の点で非常
に重要になつている。これまでに種々の表面欠陥
検査装置が実施されているが、特に光学的手段を
とつたものが多い。この光学的検査手段の一つ
に、スラブ表面からの反射光を用いてスラブ表面
の影像をテレビモニタに映し出し、これを目視検
査するものがある。他の1つは、肉眼による欠陥
認識に代えて汎用の計算機を使つてスラブ表面の
画像を解析しこれから欠陥を抽出しようとするも
のがある。前者は被検査材(スラブ材)が高速で
移動する場合には疵の目視検査が不可能であると
共に定量化が困難であり、それ相当に高度な熟練
を要するところから早くから自動化を計ることの
要求があつた。一方、後者のものは、ITVカメ
ラからのビデオ出力をデイジタル化して計算機の
メモリに記憶させた後、計算機プログラムにより
処理して目視判別能力に近づけようとする手段で
あるが、こうした画像処理手段はメモリ容量が非
常に大きくなるのみならず、画像処理にかなりの
時間を要するため実現に程遠いものである。更
に、両者を問わず、この被検査材表面の疵検査を
困難にしている他の問題がある。それは被検査材
表面のスケールによる誤判定の問題である。従
来、これを解決するために目視および自動検査の
いずれの場合も、強圧水を用いてスケール疵等を
飛ばした後検査を行なつているが、これは完全な
解決策とは考えられていない。
Hot detection of surface defects on slabs has become very important from the viewpoint of energy saving and quality assurance of slabs. Although various surface defect inspection apparatuses have been implemented so far, many of them employ optical means in particular. One of these optical inspection means is to display an image of the slab surface on a television monitor using reflected light from the slab surface, and visually inspect the image. Another method uses a general-purpose computer to analyze an image of the slab surface and extract defects from the image instead of recognizing defects with the naked eye. The former is impossible to visually inspect for defects and difficult to quantify when the material to be inspected (slab material) moves at high speed, and requires a high degree of skill, so it is recommended to automate it from an early stage. A request was made. On the other hand, the latter method digitizes the video output from the ITV camera, stores it in the computer's memory, and then processes it with a computer program to bring it closer to the visual discrimination ability. Not only does this require a very large memory capacity, but it also requires a considerable amount of time for image processing, so it is far from being realized. Furthermore, there are other problems that make inspection for defects on the surface of the inspected material difficult. This is a problem of misjudgment due to the scale of the surface of the inspected material. Conventionally, to solve this problem, in both visual and automatic inspections, the inspection is carried out after using high-pressure water to blow away scale flaws, etc., but this is not considered to be a complete solution. .

本発明は上記実情にかんがみてなされたもの
で、その目的とするところは、被検査材表面の重
大欠陥である縦割れ疵および横割れ疵の欠陥パタ
ーンに注目し、多量の画像メモリを必要とせずに
確実にパターン認識を行ない、これにより低コス
トかつ高速度でリアルタイムに被検査材の縦割れ
疵および横割れ疵を検査する表面欠陥検査装置を
提供するものである。
The present invention has been made in view of the above circumstances, and its purpose is to focus on the defect patterns of vertical cracks and horizontal cracks, which are serious defects on the surface of the inspected material, and to eliminate the need for a large amount of image memory. The present invention provides a surface defect inspection device that performs pattern recognition without fail and thereby inspects vertical cracks and horizontal cracks on a material to be inspected in real time at low cost and at high speed.

以下、本発明の一実施例を第1図および第2図
を参照して説明する。なお、第1図は装置の全体
構成を示し、第2図は第1図の割れ疵検出回路の
構成を示す図である。第1図において11はA矢
印方向に移動する被検査材であつてその表面に縦
割れ疵12および横割れ疵13が欠陥として示さ
れ、さらに被検査材11の巾方向に欠陥の影像を
強調するために例えば棒状水銀灯等の光源14を
配置し被検査材表面を照射している。15は被検
査材11の表面巾方向に走査しながら被検査材1
1表面の反射光像を撮像した後、ビデオ信号とし
て出力する撮像カメラであつて、これには一次元
イメージセンサカメラを使用する。16は被検査
材11の移動方向の重複走査および間欠走査をな
くするためにその被検査材11の移動速度に応じ
て所定期間ごとに同期信号を発生する同期信号発
生部である。17は撮像カメラ15のビデオ信号
を同期化して割れ疵検出回路18へ送り縦および
横割れ疵の判別を行なわせる同期化回路である。
An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. Note that FIG. 1 shows the overall configuration of the apparatus, and FIG. 2 is a diagram showing the configuration of the crack detection circuit of FIG. 1. In Fig. 1, reference numeral 11 indicates a material to be inspected that moves in the direction of arrow A, and vertical cracks 12 and horizontal cracks 13 are shown as defects on its surface, and images of the defects are further emphasized in the width direction of the material to be inspected 11. In order to do this, a light source 14 such as a rod-shaped mercury lamp is arranged to illuminate the surface of the material to be inspected. 15 is the material to be inspected 1 while scanning in the surface width direction of the material to be inspected 11;
This is an imaging camera that captures a reflected light image of one surface and then outputs it as a video signal, using a one-dimensional image sensor camera. Reference numeral 16 denotes a synchronization signal generating section that generates a synchronization signal at predetermined intervals according to the moving speed of the inspection object 11 in order to eliminate overlapping scanning and intermittent scanning in the moving direction of the inspection object 11. 17 is a synchronization circuit that synchronizes the video signal of the imaging camera 15 and sends it to the crack detection circuit 18 to discriminate between vertical and horizontal cracks.

19は表示部である。 19 is a display section.

この割れ疵検出回路18は、第2図に示すよう
に縦割れ疵検出系20と横割れ疵検出系30とに
より構成される。縦割れ疵検出系20は、撮像カ
メラ15の一走査分に等しいビツト数を有するア
ナログシフトレジスタ21と、遅延回路22と、
この遅延回路22の出力をレジスタ21と同様な
ビツト数で記憶するアナログシフトレジスタ23
と、両シフトレジスタ21,23の出力差をとる
差動アンプ24と、加算器25およびシフトレジ
スタ26と、縦疵判別回路27とからなつてい
る。なお、同期化回路17の出力を2分岐し、そ
の一方を直接シフトレジスタ21に入力し、他方
を遅延してシフトレジスタ23に入力し、それぞ
れのシフトレジスタ21,23の出力を差動アン
プ24で差動出力することにより、横割れ疵を除
去し縦割れ疵を出力する。加算器25とシフトレ
ジスタ26はリングアナログ加算器を構成しビデ
オ信号の各ビツトをライン移動方向に積分し、縦
方向の疵を強調しその他の疵例えばスケール疵等
を平均化する機能を持つている。縦疵判別回路2
7は所定の判別レベルで積分出力と比較して縦割
れ疵を検出する機能をもつている。
The crack detection circuit 18 is composed of a vertical crack detection system 20 and a horizontal crack detection system 30, as shown in FIG. The vertical crack detection system 20 includes an analog shift register 21 having a number of bits equal to one scan of the imaging camera 15, a delay circuit 22,
An analog shift register 23 stores the output of the delay circuit 22 in the same number of bits as the register 21.
, a differential amplifier 24 that takes the difference between the outputs of both shift registers 21 and 23, an adder 25, a shift register 26, and a vertical flaw discrimination circuit 27. Note that the output of the synchronization circuit 17 is branched into two, one of which is input directly to the shift register 21, the other is delayed and input to the shift register 23, and the outputs of the respective shift registers 21 and 23 are input to the differential amplifier 24. By performing differential output at , horizontal cracks are removed and vertical cracks are output. The adder 25 and the shift register 26 constitute a ring analog adder, which has the function of integrating each bit of the video signal in the line moving direction, emphasizing vertical defects, and averaging other defects such as scale defects. There is. Vertical flaw discrimination circuit 2
7 has a function of detecting vertical cracks by comparing with the integral output at a predetermined discrimination level.

一方、横割れ疵検出系30は、シリアル接続し
てライン移動方向に2列分のデータを蓄積するシ
フトレジスタ31,32と、これらのシフトレジ
スタ31,32の出力差を取り出すことにより縦
割れ疵を除去し横割れ疵を出力する差動アンプ3
3と、この出力差を被検査材巾方向に積分する積
分回路34と、この積分回路の積分値を前記一走
査終了ごとにリセツトするリセツト制御回路35
と、横疵判別回路36とからなつている。この横
疵判別回路36は積分出力を所定の判別レベルで
比較し横疵を検出する機能をもつている。
On the other hand, the horizontal crack detection system 30 detects vertical cracks by extracting the output difference between shift registers 31 and 32 that are serially connected and store data for two columns in the line movement direction, and these shift registers 31 and 32. Differential amplifier 3 removes horizontal cracks and outputs
3, an integrating circuit 34 that integrates this output difference in the width direction of the material to be inspected, and a reset control circuit 35 that resets the integrated value of this integrating circuit every time the one scan ends.
and a horizontal flaw discrimination circuit 36. This horizontal flaw discrimination circuit 36 has a function of comparing the integral output at a predetermined discrimination level and detecting horizontal flaws.

次に、以上のように構成する装置の作用を説明
する。例えば第3図のように縦割れ疵12、横割
れ疵13およびその他の疵40例えばスケール
疵、ヘゲ疵等を有する被検査材11が図示A矢印
方向に移動しているものとする。このとき、光源
14の照射によつて被検査材11から反射光像が
得られるが、これを撮像カメラ15で被検査材巾
方向に走査して撮像しビデオ信号とした後、同期
信号発生部16と同期化回路17とにより、同期
化したビデオ信号として割れ疵検出回路18へ供
給する。
Next, the operation of the apparatus configured as above will be explained. For example, as shown in FIG. 3, it is assumed that a material to be inspected 11 having vertical cracks 12, horizontal cracks 13, and other defects 40 such as scale defects, scab marks, etc. is moving in the direction of the arrow A in the figure. At this time, a reflected light image is obtained from the material to be inspected 11 by irradiation with the light source 14, and this image is scanned in the width direction of the material to be inspected by the imaging camera 15 and is imaged as a video signal. 16 and a synchronization circuit 17, the signal is supplied as a synchronized video signal to a crack detection circuit 18.

この割れ疵検出回路18では、同期化された巾
方向一走査分のビデオ信号をシフトクロツク信号
SCに基づいてシフトレジスタ21,31および
遅延回路22で遅延の後シフトレジスタ23へ順
次格納していく。そして、シフトレジスタ21,
23の両出力差を差動アンプ24で取り出すこと
により走査方向に微分した信号を得る。次に、こ
の微分出力を、加算器25とシフトレジスタ26
よりなるリングアナログ加算器に入力し、ここで
積分処理を行なつて縦方向の疵12を強調しその
他の疵40を平均化した第3図bのような信号SI
を得、これを後続の縦疵判別回路27に入力し判
別レベルVLと比較して縦割れ疵12の信号12
Sを検出する。
This crack detection circuit 18 converts the synchronized video signal for one scan in the width direction into a shift clock signal.
Based on the SC, the signals are delayed by the shift registers 21 and 31 and the delay circuit 22, and then sequentially stored in the shift register 23. And the shift register 21,
A differential amplifier 24 extracts the difference between the two outputs of 23 to obtain a signal differentiated in the scanning direction. Next, this differential output is sent to the adder 25 and the shift register 26.
The signal SI as shown in Fig. 3b is inputted to a ring analog adder consisting of
This is input to the subsequent vertical flaw discrimination circuit 27 and compared with the discrimination level VL to determine the signal 12 of the vertical crack flaw 12.
Detect S.

一方、横割れ疵検出系30にあつては、同期化
されたビデオ信号を縦続接続せるシフトレジスタ
31,32によりライン移動方向に2列分のデー
タとして蓄積した後、これらのシフトレジスタ3
1,32の出力差を差動アンプ33で取り出して
被検査材表面の撮像を被検査材移動方向に微分す
る。そして、この微分出力を積分回路34とリセ
ツト信号制御回路35により被検査材巾方向に積
分し、第3図cのような横割れ疵13の信号13
Sを強調し縦方向の疵12やその他の疵40を平
均化した信号S2を取り出す。しかる後、後続の
横疵判別回路36で積分出力S2を所定の判別レ
ベルVLで比較し横割れ疵13を検出する。
On the other hand, in the horizontal crack detection system 30, the synchronized video signals are accumulated as data for two columns in the line movement direction by shift registers 31 and 32 that are connected in cascade, and then these shift registers 3
1 and 32 is taken out by a differential amplifier 33, and the image of the surface of the inspected material is differentiated in the moving direction of the inspected material. Then, this differential output is integrated in the width direction of the inspected material by the integrating circuit 34 and the reset signal control circuit 35, and a signal 13 of the horizontal crack 13 as shown in FIG.
A signal S2 is extracted by emphasizing S and averaging the vertical flaws 12 and other flaws 40. Thereafter, the subsequent horizontal flaw discrimination circuit 36 compares the integral output S2 at a predetermined discrimination level VL to detect a horizontal crack 13.

なお、本発明は上記実施例に限定されるもので
はない。上記実施例はアナログシフトレジスタに
よるメモリ構成としたが、ビデオ信号を高速のA
―D変換器を用いてデイジタル化すれば、アナロ
グ処理とせずにデイジタル的処理できる。その
他、本発明はその要旨を逸脱しない範囲で種々変
形して実施できる。
Note that the present invention is not limited to the above embodiments. Although the above embodiment has a memory configuration using an analog shift register, the video signal is
- If you digitize using a D converter, you can perform digital processing instead of analog processing. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

以上詳記したように本発明によれば、ビデオ映
像信号の空間について微分をとつているので、被
検査材表面の反射ムラやスケールによる反射率変
化に起因する低周波成分のビデオ出力変化は従来
に比べて大幅に取り除くことができる。さらに、
この微分後に欠陥の長手方向に積分しているの
で、他の微少なスケール疵やヘゲ疵は平均化され
割れ疵のみSN比よく検出できる。また、縦およ
び横のパターン判別が少容量のメモリで可能とな
り、これによりシステムのコストを大幅に低減化
し得て実用的価値の高い表面欠陥検査装置を提供
できる。
As described in detail above, according to the present invention, differentiation is taken with respect to the space of the video image signal, so changes in the video output of low frequency components caused by reflectance changes due to uneven reflection on the surface of the inspected material or scale are reduced compared to the conventional method. can be removed to a large extent compared to moreover,
After this differentiation, integration is performed in the longitudinal direction of the defect, so other minute scale defects and sagging defects are averaged out, and only cracks can be detected with a high signal-to-noise ratio. Additionally, vertical and horizontal pattern discrimination can be performed with a small memory capacity, thereby significantly reducing system costs and providing a surface defect inspection device with high practical value.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明装置の一実施例を示す全体構成
図、第2図は第1図の割れ疵検出回路の具体的構
成を示す図、第3図a〜cは被検査材における割
れ疵の検出信号を示す図である。 11…被検査材、15…撮像カメラ、16…同
期信号発生部、17…同期化回路、18…割れ疵
検出回路、20…縦割れ疵検出系、21,23,
26…シフトレジスタ、22…遅延回路、24…
差動アンプ、25…加算器、27…縦疵判別回
路、30…横割れ疵検出系、31,32…シフト
レジスタ、33…差動アンプ、34…積分回路、
36…横疵判別回路。
FIG. 1 is an overall configuration diagram showing an embodiment of the present invention apparatus, FIG. 2 is a diagram showing a specific configuration of the crack detection circuit shown in FIG. 1, and FIGS. It is a figure which shows the detection signal of. DESCRIPTION OF SYMBOLS 11... Material to be inspected, 15... Imaging camera, 16... Synchronization signal generation section, 17... Synchronization circuit, 18... Crack detection circuit, 20... Vertical crack detection system, 21, 23,
26...Shift register, 22...Delay circuit, 24...
Differential amplifier, 25... Adder, 27... Vertical flaw discrimination circuit, 30... Horizontal crack detection system, 31, 32... Shift register, 33... Differential amplifier, 34... Integrating circuit,
36... Horizontal flaw discrimination circuit.

Claims (1)

【特許請求の範囲】 1 被検査材表面の光学像を巾方向に走査しなが
ら撮像装置で撮像すると共にこの撮像装置から出
力するビデオ信号を同期化回路で被検査材移動方
向に同期化しながら縦割れ疵検出系および横割れ
疵検出系に供給し縦割れ疵および横割れ疵を判別
する表面欠陥検査装置において、 前記縦割れ疵検出系は、前記同期化回路から出
力するビデオ信号を前記撮像装置の一走査分に相
当するビツト数分記憶する第1のシフトレジスタ
と、前記同期化回路から出力するビデオ信号を遅
延回路を介して順次記憶する前記第1のシフトレ
ジスタと等しいビツト数を持つ第2のシフトレジ
スタと、これら両シフトレジスタの出力を差動出
力する第1の差動アンプと、この第1の差動アン
プの出力を加算する加算器およびこの加算器の出
力を順次記憶しながらこの記憶出力を前記加算器
の入力側に供給する第3のシフトレジスタよりな
り前記被検査材移動方向の疵を積分するリングア
ナログ加算器と、このリングアナログ加算器の出
力レベルが予め定めた第1の判別レベルを越えた
とき縦割れ疵であると検出する縦疵判別回路とを
備え、 一方、前記横割れ疵検出系は、前記同期化回路
から出力する前記被検査材移動方向の2列分のビ
デオ信号を順次記憶するシリアル接続された第4
および第5のシフトレジスタと、これら第4およ
び第5のシフトレジスタの出力を差動出力する第
2の差動アンプと、この第2の差動アンプの出力
を前記被検査材巾方向に積分する積分回路と、こ
の積分回路の出力レベルが第2の判別レベルを越
えたとき横割れ疵であると検出する横疵判別回路
と、前記一走査終了ごとに前記積分回路の出力を
リセツトするリセツト制御回路とを備えた ことを特徴とする表面欠陥検査装置。
[Scope of Claims] 1. An optical image of the surface of the inspected material is captured by an imaging device while scanning in the width direction, and a video signal output from the imaging device is synchronized in the direction of movement of the inspected material using a synchronization circuit while being vertically scanned. In a surface defect inspection device that supplies a crack detection system and a horizontal crack detection system to discriminate between vertical cracks and horizontal cracks, the vertical crack detection system transmits a video signal output from the synchronization circuit to the imaging device. a first shift register that stores a number of bits corresponding to one scan, and a second shift register that has an equal number of bits as the first shift register that sequentially stores the video signal output from the synchronization circuit via a delay circuit. 2 shift registers, a first differential amplifier that differentially outputs the outputs of both shift registers, an adder that adds the outputs of the first differential amplifier, and a system that sequentially stores the outputs of this adder. A ring analog adder includes a third shift register that supplies this stored output to the input side of the adder, and integrates flaws in the moving direction of the inspected material; and a vertical flaw discriminating circuit that detects a vertical crack flaw when it exceeds the discrimination level No. 1. On the other hand, the horizontal flaw detection system includes two rows in the moving direction of the inspected material outputted from the synchronization circuit. A fourth serially connected video signal that sequentially stores video signals of
and a fifth shift register, a second differential amplifier that differentially outputs the outputs of the fourth and fifth shift registers, and integrates the output of the second differential amplifier in the width direction of the material to be inspected. a horizontal flaw discriminating circuit that detects a horizontal flaw when the output level of the integrator circuit exceeds a second discrimination level; and a reset circuit that resets the output of the integrator circuit every time one scan is completed. A surface defect inspection device characterized by comprising a control circuit.
JP6916381A 1981-05-08 1981-05-08 Inspecting device of surface defect Granted JPS57184956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6916381A JPS57184956A (en) 1981-05-08 1981-05-08 Inspecting device of surface defect

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6916381A JPS57184956A (en) 1981-05-08 1981-05-08 Inspecting device of surface defect

Publications (2)

Publication Number Publication Date
JPS57184956A JPS57184956A (en) 1982-11-13
JPS6349180B2 true JPS6349180B2 (en) 1988-10-03

Family

ID=13394757

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6916381A Granted JPS57184956A (en) 1981-05-08 1981-05-08 Inspecting device of surface defect

Country Status (1)

Country Link
JP (1) JPS57184956A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0612343B2 (en) * 1983-03-31 1994-02-16 株式会社東芝 Surface inspection device
JPH065215B2 (en) * 1985-05-31 1994-01-19 日本放送協会 Inspection device for tape-shaped recording medium
JPH0412257A (en) * 1990-04-27 1992-01-16 Kawasaki Steel Corp Method and device for detecting linear flaw on steel plate
JP6809510B2 (en) * 2018-03-09 2021-01-06 Jfeスチール株式会社 Inspection method and inspection device for widthwise linear pattern defects on the surface of metal strips

Also Published As

Publication number Publication date
JPS57184956A (en) 1982-11-13

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