JPS6349098Y2 - - Google Patents

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Publication number
JPS6349098Y2
JPS6349098Y2 JP1981153633U JP15363381U JPS6349098Y2 JP S6349098 Y2 JPS6349098 Y2 JP S6349098Y2 JP 1981153633 U JP1981153633 U JP 1981153633U JP 15363381 U JP15363381 U JP 15363381U JP S6349098 Y2 JPS6349098 Y2 JP S6349098Y2
Authority
JP
Japan
Prior art keywords
gate
circuit
gto
voltage
light emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1981153633U
Other languages
Japanese (ja)
Other versions
JPS5859379U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15363381U priority Critical patent/JPS5859379U/en
Publication of JPS5859379U publication Critical patent/JPS5859379U/en
Application granted granted Critical
Publication of JPS6349098Y2 publication Critical patent/JPS6349098Y2/ja
Granted legal-status Critical Current

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  • Thyristor Switches And Gates (AREA)
  • Power Conversion In General (AREA)

Description

【考案の詳細な説明】 本考案はゲートでON−OFF可能なゲートター
ンオフサイリスタの故障検出装置に係り、特に故
障検出部を低圧側に配置することによつて低耐圧
のパーツ品を適用できるようにした故障検出装置
を提供しようとするものである。
[Detailed description of the invention] The present invention relates to a failure detection device for a gate turn-off thyristor that can be turned on and off with a gate, and in particular, by locating the failure detection part on the low voltage side, it is possible to apply parts with low withstand voltage. The present invention is intended to provide a failure detection device that has the following features.

ゲートでON−OFF可能なゲートターンオフサ
イリスタ(以下GTOと略称する)は高耐圧、大
容量化が進みパルス幅変調形の無停電電源装置、
さらには可変周波電源としての電流形インバー
タ、電圧形インバータ等に用いられつつある。か
かるGTOの故障を検出するものとして従来では
第1図に示すように、GTO1のアノード−カソ
ード間に並列に発光ダイオード3、−フオトトラ
ンジスタ32−抵抗33−ダイオード34より構成
される故障検出装置3なるものを接続して、この
プリント板に搭載されるゲート回路よりのOFF
ゲート信号を以つてGTO1をOFFした場合に、
当該GTO1のアノード−カソード間に印加され
る主回路電源電圧を以つて、抵抗33→発光ダイ
オード31の経路で発光ダイオード31を点弧さ
せ、フオトトランジスタ32の出力が「0」レベ
ルであればGTOは正常、これとに反対にGTOが
順方向の阻止能力を失なつて導通しつ放しの状態
になると、31の発光ダイオードはOFFゲート信
号の送出した時点で発光せず、フオトトランジス
タ32の出力は「1」レベルのままとなる。この
ようにフオトトランジスタ32の出力が「1」レ
ベルを継続すると云う条件をとらえて、GTOが
故障した旨を判定するものであるが、かかる方法
であれば、故障検出装置が主回路側に設けている
ので、発光ダイオード31等の各パーツ品は手回
路電源電圧に耐え得るだけの耐圧を持たせなけれ
ばならず、装置そのものが非常に不経剤となるこ
とである。さらに重要なことは、主回路に通電し
ないと所定の故障検出を行なえないと云う点であ
る。
Gate turn-off thyristors (hereinafter abbreviated as GTO), which can be turned on and off by a gate, are becoming increasingly high in voltage and capacity, and are used in pulse width modulation type uninterruptible power supplies.
Furthermore, they are being used in current source inverters, voltage source inverters, etc. as variable frequency power sources. As shown in FIG. 1, conventional methods for detecting such GTO failures include a light emitting diode 3, a phototransistor 3 2 , a resistor 3 3 , and a diode 3 4 connected in parallel between the anode and cathode of the GTO 1. Connect the detection device 3 and turn off the signal from the gate circuit mounted on this printed board.
When GTO1 is turned off using the gate signal,
With the main circuit power supply voltage applied between the anode and cathode of the GTO 1, the light emitting diode 31 is ignited through the path of the resistor 33 → light emitting diode 31 , and the output of the phototransistor 32 is set to the "0" level. If so, the GTO is normal.On the other hand, if the GTO loses its forward blocking ability and remains conductive, the light emitting diode 31 will not emit light when the OFF gate signal is sent. The output of the phototransistor 32 remains at the "1" level. In this way, the condition that the output of the phototransistor 32 continues to be at the "1" level is used to determine that the GTO has failed, but with this method, the failure detection device is placed on the main circuit side. Therefore, each part such as the light emitting diode 31 must have a withstand voltage sufficient to withstand the power supply voltage of the hand circuit, which makes the device itself extremely difficult to use. What is more important is that specified failure detection cannot be performed unless the main circuit is energized.

本考案はこの点に鑑みて考案されたものであつ
て、特に本願は低圧側に検出装置を配した点に一
大特徴を有し、以下第2図に示す実施例に基づき
詳述する。
The present invention has been devised in view of this point, and in particular, the present invention has a major feature in that a detection device is disposed on the low pressure side, and will be described in detail below based on the embodiment shown in FIG.

第2図の実施例で4はONゲート用の整流回路
で、5は同様にOFF用の整流回路で、6はONゲ
ート用のスイツチング素子で、7は同様にOFF
ゲート用のスイツチング素子で、8は本願の要部
たるON時に動作する第1の故障検出回路で、こ
の検出回路8は図示するように低圧側のプリント
板に実装され発光ダイオード81−フオトトラン
ジスタ82−抵抗83−ダイオード84で構成され
る。9は他方の要部たるOFF時に動作する第2
の故障検出回路で、この回路は図示するように低
圧側のプリント板に実装される発光ダイオード9
−フオトトランジスタ92−抵抗93−ダイオー
ド94で構成される。
In the embodiment shown in Fig. 2, 4 is a rectifier circuit for ON gate, 5 is a rectifier circuit for OFF, 6 is a switching element for ON gate, and 7 is a switching element for OFF.
8 is a switching element for the gate, and 8 is a first failure detection circuit that operates when ON, which is the main part of the present application. As shown in the figure, this detection circuit 8 is mounted on a printed board on the low voltage side and includes a light emitting diode 8 1 -phototransistor. It is composed of 8 2 -resistor 8 3 -diode 8 4 . 9 is the second main part that operates when the other is OFF.
As shown in the figure, this circuit has a light emitting diode 9 mounted on a printed circuit board on the low voltage side.
1 - phototransistor 9 2 - resistor 9 3 - diode 9 4 .

以上のように構成される本実施例の動作を第3
図の動作波形図を参照し乍ら詳述するに、先ず
GTO1が挿入される主回路を通電しない場合の
検出法に関して述べる。プリント板に実装される
ゲート回路等に所定の制御電源電圧を印加して
ON用のスイツチング素子6に所望のONゲート
信号を与えた場合、整流回路4→スイツチング素
子6→GTOのゲート及びカソード→整流回路4
の経路で電流が流れる。このONゲート信号の印
加時点で、GTOのゲート−カソード間が高イン
ピーダンスにあれば、第1の故障検出回路8の発
光ダイオード81の端子間にG−K間電圧が印加
され81の発光ダイオードは発光する。このよう
にダイオード81が発光するとフオトトランジス
タ82の出力が「0」レベルとなり、GTOが正常
である旨を判定される。次にOFF用のスイツチ
ング素子7に所望のOFFゲート信号を与えると、
整流回路5→GTOのカソード及びゲート→スイ
ツチング素子7→整流回路の経路でで電流が流
れ、このOFFゲート信号の印加時点で、GTOの
ゲート−カソード間が高インピーダンスにあれば
G−K間に電圧が表われ発光ダイオード91が発
光する。このように発光ダイオード91が発光す
ると、92のフオトトランジスタが導通してその
出力は「0」レベルとなり、この検出信号を以つ
てGTOは正常である旨が判定される。以上の動
作モードを示したのが第3図で、同図のAは
GTOのゲート−カソード間に表われる電圧を示
し、Bはフオトトランジスタより出力される検出
信号の電圧波形図を示す。これら電圧波形図より
明らかなように、GTOが正常であればt1点以前
の波形図の如くONゲート信号−OFFゲート信号
の印加時点では、GTOのG−K間には所定の電
圧が表われ検出信号は「0」レベルとなつてい
る。これに対して何らかの原因でGTOのG−K
間が短絡し故障すると、ONゲート信号および
OFFゲート信号を印加した時点でG−K間のイ
ンピーダンスは零或いは零に近い値となつている
ので、第3図のt1点以後に示すようにG−K間電
圧は零となり検出信号のレベルが「1」となる。
このように検出信号が「1」と云う条件でGTO
が故障である旨を判定するものである。なお以上
の動作説明は、主回路を通電しない場合の故障検
出法に関して述べたが、主回路をを通電した場合
でも所定のON−OFF制御時に、例えばOFFゲー
ト信号を与えてGTOがOFFすれば、GTOのG−
K間インピーダンスが高くなつて当該G−K間に
電圧が表われ検出信号も「0」レベルとなり、こ
れとは反対にONゲート信号を与えてGTOがON
すれば、G−K間のインピーダンスが略零値に低
下するまでの期間G−K間は電圧が表われるの
で、検出信号も「0」レベルとなつて正常である
旨を判定すると云うように、GTOの常時の動作
中であつても故障は確実に検出できるものであ
る。
The operation of this embodiment configured as described above is explained in the third section.
To explain in detail with reference to the operation waveform diagram in the figure, first,
The detection method when the main circuit into which GTO1 is inserted is not energized will be described. A predetermined control power supply voltage is applied to the gate circuit etc. mounted on the printed board.
When a desired ON gate signal is given to the ON switching element 6, the rectifier circuit 4 → switching element 6 → GTO gate and cathode → rectifier circuit 4
Current flows through the path. If the gate-cathode of the GTO is at high impedance at the time of application of this ON gate signal, a G-K voltage is applied between the terminals of the light emitting diode 81 of the first fault detection circuit 8, causing the light emitting diode 81 to emit light. The diode emits light. When the diode 8 1 emits light in this way, the output of the phototransistor 8 2 becomes "0" level, and it is determined that the GTO is normal. Next, when a desired OFF gate signal is applied to the OFF switching element 7,
A current flows in the path of rectifier circuit 5 → GTO cathode and gate → switching element 7 → rectifier circuit, and if there is a high impedance between the gate and cathode of GTO at the time of application of this OFF gate signal, there will be a current between G and K. A voltage appears and the light emitting diode 91 emits light. When the light emitting diode 9 1 emits light in this manner, the phototransistor 9 2 becomes conductive and its output becomes the "0" level, and it is determined from this detection signal that the GTO is normal. Figure 3 shows the above operation mode, and A in the figure is
The voltage appearing between the gate and cathode of the GTO is shown, and B shows the voltage waveform diagram of the detection signal output from the phototransistor. As is clear from these voltage waveform diagrams, if the GTO is normal, a predetermined voltage will appear between G and K of the GTO when the ON gate signal and OFF gate signal are applied, as shown in the waveform diagram before point t . The detection signal is at the "0" level. For some reason, G-K of GTO
If a fault occurs due to a short circuit between the
Since the impedance between G and K is zero or close to zero at the time when the OFF gate signal is applied, the voltage between G and K becomes zero as shown after point t1 in Figure 3, and the detection signal The level becomes "1".
In this way, under the condition that the detection signal is "1", GTO
This is to determine that there is a failure. The above explanation of the operation has been about the failure detection method when the main circuit is not energized, but even if the main circuit is energized, if the GTO is turned OFF during the specified ON-OFF control, for example by giving an OFF gate signal. , G- of GTO
The impedance between K increases and a voltage appears between the G and K, and the detection signal also goes to the "0" level.On the contrary, the ON gate signal is applied and the GTO is turned ON.
Then, a voltage will appear between G and K until the impedance between G and K decreases to approximately zero value, so the detection signal will also be at the "0" level and it will be determined that it is normal. , failures can be reliably detected even when the GTO is in constant operation.

以上のように、本考案に於ては故障検出装置を
低圧側に配して所定の故障検出を行なうものであ
るから、以下に示すように種々の効果を奏するも
のである。
As described above, in the present invention, since the failure detection device is disposed on the low voltage side to perform predetermined failure detection, various effects can be achieved as described below.

故障検出装置を構成する各パーツ品は耐圧の
低いものを適用できるので、非常に経剤的な装
置を実現することができる。
Since each part constituting the failure detection device can have a low pressure resistance, it is possible to realize a very cost-effective device.

主回路を通電しなくとも異常の有無の試験を
実施できるので、試験時の消費パワーを著しく
軽減できる GTOのON時およびOFF時に対拠させて故
障検出回路を構成したので、高精度で故障を検
出することができる。
Tests for the presence or absence of abnormalities can be performed without energizing the main circuit, which significantly reduces power consumption during testing.The fault detection circuit is configured for when the GTO is ON and OFF, so it detects faults with high accuracy. can be detected.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の故障検出装置を示す具体的な回
路図、第2図は本考案による一実施例を示す故障
検出装置の具体的な回路図、第3図はその動作を
示すタイムチヤート図。 1はゲートターンオフサイリスタ、4−5は整
流回路、6−7はスイツチング素子、8−9は故
障検出回路、81−91は発光ダイオード、82
2はフオトトランジスタ。
Fig. 1 is a specific circuit diagram showing a conventional fault detection device, Fig. 2 is a specific circuit diagram of a fault detection device showing an embodiment of the present invention, and Fig. 3 is a time chart showing its operation. . 1 is a gate turn-off thyristor, 4-5 is a rectifier circuit, 6-7 is a switching element, 8-9 is a failure detection circuit, 8 1 -9 1 is a light emitting diode, 8 2 -
9 2 is a phototransistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 交流入力電源電圧を整流する第1の整流回路
と、この回路の直流出力側に設けられ所定のON
ゲート信号をゲート−カソードの経路で与える第
1のスイツチング素子と、交流入力電源電圧を整
流する第2の整流回路と、この回路の直流出力側
に設けられ所定のOFFゲート信号をカソード−
ゲートの経路で与える第2のスイツチング素子
と、OFF時のゲート・カソード間の電圧に応動
する第1の発光素子と、ON時のゲート・カソー
ド間の電圧に応動する第2の発光素子と、これら
発光素子の出力に応動して所定の検出信号を取出
す第1及び第2の受光素子とでそれぞれ構成した
ことを特徴とするゲートターンオフサイリスタの
故障検出装置。
A first rectifier circuit that rectifies the AC input power supply voltage, and a predetermined ON circuit provided on the DC output side of this circuit.
A first switching element that provides a gate signal through a gate-cathode path, a second rectifier circuit that rectifies the AC input power supply voltage, and a second rectifier circuit that is provided on the DC output side of this circuit and applies a predetermined OFF gate signal to the cathode.
a second switching element applied through the gate path; a first light emitting element that responds to the voltage between the gate and cathode when OFF; and a second light emitting element that responds to the voltage between the gate and cathode when ON; 1. A failure detection device for a gate turn-off thyristor, comprising first and second light receiving elements that output predetermined detection signals in response to the outputs of these light emitting elements.
JP15363381U 1981-10-16 1981-10-16 Gate turn-off thyristor failure detection device Granted JPS5859379U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15363381U JPS5859379U (en) 1981-10-16 1981-10-16 Gate turn-off thyristor failure detection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15363381U JPS5859379U (en) 1981-10-16 1981-10-16 Gate turn-off thyristor failure detection device

Publications (2)

Publication Number Publication Date
JPS5859379U JPS5859379U (en) 1983-04-21
JPS6349098Y2 true JPS6349098Y2 (en) 1988-12-16

Family

ID=29946245

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15363381U Granted JPS5859379U (en) 1981-10-16 1981-10-16 Gate turn-off thyristor failure detection device

Country Status (1)

Country Link
JP (1) JPS5859379U (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5983569A (en) * 1982-10-30 1984-05-15 Toshiba Corp Trouble detecting circuit for gate turn-off thyristor
JPS62199117A (en) * 1986-02-27 1987-09-02 Fuji Electric Co Ltd Fault detection circuit for gto thyristor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS506272A (en) * 1973-05-17 1975-01-22
JPS5219955A (en) * 1975-08-08 1977-02-15 Toshiba Corp Gate turn-off thyristor protector
JPS5545274A (en) * 1978-09-26 1980-03-29 Hitachi Ltd Gate circuit of gate turn-off thyristor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS506272A (en) * 1973-05-17 1975-01-22
JPS5219955A (en) * 1975-08-08 1977-02-15 Toshiba Corp Gate turn-off thyristor protector
JPS5545274A (en) * 1978-09-26 1980-03-29 Hitachi Ltd Gate circuit of gate turn-off thyristor

Also Published As

Publication number Publication date
JPS5859379U (en) 1983-04-21

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