JPS6348030B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic device with a counter function that includes a plurality of counters that count pulse signals input by operating an external operation switch.

Recently, electronic digital watches, small electronic calculators, etc. have become more and more multi-functional, and some are known to have a counter function with multiple counters that count pulse signals input by operating an external operation switch. This counter function is used, for example, as a game score display function by setting game scores for each individual or team in each counter and displaying the contents set on each of these counters.

However, when the same game is repeated many times and the winner or loser is decided based on the total score, the content displayed is the content of one game, and the game moves on to a new game. To display the score, change the display content (i.e.
They had to clear the previous game's score. Therefore, each time a game is completed, the displayed contents are transferred to the score sheet, and
At the end of the final game, the total score for each individual or team had to be calculated by hand or in the head, depending on the number of games played, which was time-consuming and resulted in errors in writing and calculations. .

The present invention has been made based on the above circumstances, and its object is to provide a memory that includes a plurality of counters that count pulse signals input by operating an external operation switch, and that stores the contents of each of the counters. By providing the counter function, for example, when the counter function is used as a game score display function, it is possible to know all the game results up to that point during the game, and also to know the total score. An object of the present invention is to provide an electronic device with a counter function that is extremely convenient as a game score display function.

Hereinafter, the present invention will be specifically described based on an embodiment shown in the drawings. In the figure, numeral 1 is an oscillation circuit that generates a reference clock signal, 2 is a frequency divider circuit that divides the frequency of the reference clock signal into a 1-second signal, and 3 is a frequency divider that counts the 1-second signal to provide time information in hours, minutes, and seconds. and a counter counting circuit that obtains date information of the month, day, and day of the week. The clock information obtained by the counting circuit 3 is sent to the liquid crystal display section 5 via the gate circuit _G1 and the display switching control circuit 4 in order, and is digitally displayed.

Here, the configuration of the liquid crystal display section 5 will be explained with reference to FIG. The liquid crystal display section 5 includes number display bodies 5A to 5E that each display two-digit numbers, a character display body 5F that displays the day of the week, and an AM/PM display body that displays AM/PM, as well as a number display body 5A. ~5
Rod-shaped display bodies 5Ga to 5Gd provided corresponding to D
has. In addition, the bar-shaped display bodies 5Ga to 5Gd correspond to the corresponding number display bodies 5A to 5D depending on their lighting display.
In addition to clearly indicating that the number displayed is negative, the bar-shaped display 5Gb and 5Gd are number display 5A.
and 5B or 5C and 5D.

Next, referring back to FIG. 1, another circuit configuration will be explained. Symbols S ₁ to _{S 5} are external operation switches that can be operated from outside the watch, and each of these switches S ₁ to _{S 5}
The operation signals of the corresponding one-shot circuits 6 to 1
0 and each of these one-shot circuits 6 to 1
Outputs a one-shot pulse signal from 0. The pulse signal output from the one-shot circuit 6 is applied to a quaternary mode counter 11 which specifies various operation modes, and increments its contents.
The mode designation signal "0" outputted when the content of the mode counter 11 is "0" is given to the gate circuit _G1 as a gate control signal. Further, the pulse signal output from the one shot circuit 7 is applied to a quaternary selection counter 12 that selectively specifies a plurality of up/down counters 15 to 18, which will be described later, to increment the contents thereof. This selection counter 1
The selection signals “0” to “3” output when the contents of “2” are “0”, “1”, “2”, and “3” are respectively sent to the decoder 1.
given to 3. The decoder 13 is also supplied with the mode designation signal "1" from the mode counter 11 and the pulse signals output from the one-shot circuits 8-10, respectively. In addition, the one-shot circuit 10
The pulse signal output from decimal counter 1
4 and advances its contents. In addition, 10
The advance counter 14 is configured so that its contents are incremented in synchronization with the falling edge of the input pulse signal.

When the mode designation signal "1" is input to the decoder 13, the one shot circuit 8
Each time a pulse signal is given from
It outputs a ₀ to a ₃ , and every time a pulse signal is given from the one-shot circuit 9, the selection counter 12
One-shot pulse signal b ₀ ~ corresponding to the content of
_b3 , and further outputs a one-shot pulse signal C every time a pulse signal is given from the one-shot circuit 10. The pulse signals _a0 to _a3
are applied to the +1 input terminals of the corresponding up-down counters 15 to 18, and increment the contents by +1, and the pulse signals b ₀ to b ₃ are applied to the -1 input terminals of the corresponding up-down counters 15 to 18. The pulse signal C is applied to the input terminal and increments its contents by -1, and furthermore, the pulse signal C is applied to the reset terminal R of each up-down counter 15 to 18 via the delay circuit 19 to clear the contents.

The contents of the up-down counters 15 to 18 are sequentially sent to the display section 5 via the gate circuit G ₂ to which the mode designation signal "1" is applied as a gate control signal and the display switching control circuit 4, and are digitally displayed. In addition, the pulse signal C output from the decoder 13 is sent to the memory section 20 via the gate circuit _G3 provided as a gate control signal.

The memory section 20 has a storage capacity of 4 columns and 10 rows, and each column address is assigned to an up/down counter 15 to 15.
18, and each row address corresponds to the contents of the decimal counter 14. The memory section 20 is given the pulse signal C output from the decoder 13 as a read/write signal R/W, and when the pulse signal C is at a binary logic level of "0", the memory section 20 After receiving the read specification,
Also, when it is "1", a write designation is received. Also,
The contents of the decimal counter 14 are given to the memory section 20 as address information for specifying a row address via the gate circuit _G4 , and when a write instruction is received, each column of the specified row address is The contents of the corresponding up-down counters 15 to 18 are written, and when a read instruction is received, the contents stored in each column of the specified row address are read out in parallel. This memory section 2
The contents read from 0 are sequentially sent to the display section 5 via the gate circuit G ₅ to which the mode designation signal "2" is applied as a gate control signal and the display switching circuit 4, and are digitally displayed. Furthermore, a mode designation signal "3" is given to the memory section 20 as a read command signal, and while this mode designation signal "3" is input, all contents stored in the memory section 20 are The data is read out for each column address and sent to the arithmetic unit 21 via the gate circuit _G6 to which the mode designation signal "3" is applied as a gate control signal, where a predetermined arithmetic operation is performed.

The arithmetic unit 21 adds and outputs the inputted contents of the memory unit 20, that is, the contents stored in each row of column addresses, so this arithmetic result data is sent to the display unit 5 via the display switching control circuit 4. transmitted and displayed digitally.

The pulse signal C and mode designation signal "2" outputted from the decoder 13 are applied to the gate circuit _G4 as gate control signals via the OR gate 22, and are synchronized with the timing when the gate circuit _G4 is opened. The contents of the decimal counter 14 are then output from the gate circuit _G4 . Furthermore, the contents of the decimal counter 14 are transmitted to the display section through the gate circuit G ₇ to which the mode designation signals "1" and "2" are given as gate control signals through the OR gate 23 and the display switching control circuit 4. 5 and digitally displayed.

Note that the mode designation signals "0" to "3" are respectively applied to the display switching control circuit 4 as display switching signals.

Next, the display operation of the electronic clock configured as described above and the operation of inputting game scores for each individual or team, for example, will be explained with reference to FIGS. 3 to 6. When the content of the mode counter 11 is set to "0", the gate circuit
G ₁ is opened, and the time information obtained by the clock counting circuit 3 is sent to the display unit 5, and for example, as shown in FIG.
"Seconds" is displayed.

In this normal time display mode, switch S ₁
When is operated once, the content of the mode counter 11 is incremented from "0" to "1" and the mode is switched to the game score display mode. That is, mode counter 1
Since the mode designation signal “1” is output from 1,
Gate circuits G ₂ and G ₇ are opened, and the contents of each up-down counter 15 to 18 and decimal counter 14 are
For example, as shown in FIG. 4, the score of the A team, "-3 points", the score of the B team, "-4 points", the score of the C team, "- 16
"1 point", the score of the D team, "23 points", and the number of games played "1" are displayed. This display allows each team to know the score results of other teams.

Then, in the game score display mode, when the switch _S5 is operated after checking the score result of the first game, the one-shot pulse signal C is output from the decoder 13, so that the gate circuit _G3 and
_G4 is opened and the memory section 20 receives writing designation. Therefore, the memory unit 20 is provided with the contents of each up-down counter 15 to 18 and the contents of the decimal counter 14, so the memory unit 20 stores the row address corresponding to the contents of the decimal counter 14, that is, the row address "1". " is specified, and the contents of the corresponding up-down counters 15 to 18 are written in each column of this row address "1". Therefore, the memory unit 20 stores the scores for each team in the first game, as shown in FIG.

Thereafter, the contents of each up-down counter 15-18 are cleared by outputting a one-shot pulse signal from the delay circuit 19. Further, the contents of the decimal counter 14 are incremented by 1 in synchronization with the falling edge of the pulse signal output from the one-shot circuit 10, and become "2". The result display state is as shown in FIG. 6, and the result of the second game can be entered.

However, in the score display mode of the game,
When inputting the score results of the second game, first operate switch _S2 to set the contents of the selection counter 12 to "0", then the corresponding up-down counter 15 is selectively designated, and the A-team The score can be set in the up-down counter 15. That is, for example, if the score of team A in the second game is "-2 points", switch _S3 is operated twice. As a result, the decoder 13
From then on, each time the switch _S3 is operated, a one-shot pulse signal _b0 is output and sequentially applied to the -1 input terminal of the up-down counter 15. A certain value "-2" is set. On the other hand, if the score of team A is not a negative value, but is, for example, "+2 points," switch _S4 is operated twice. As a result, a one-shot pulse signal _a0 is output from the decoder 3 every time the switch _S4 is operated, and is given to the +1 input terminal of the up-down counter 15, so "2" is set in the up-down counter 15. be done. Similarly, when the contents of the selection counter ₁₂ are sequentially set to "1", "2", and "3" by operating the switch S2, the corresponding up-down counter 1
6 to 18 are selectively designated in sequence. By operating the switch _S3 or _S4 the number of times corresponding to the team's score, the score results of teams B to D can be set in the corresponding up-down counters 16-18. Incidentally, as described above, the score result of the second game is displayed on the display section 5, and is also stored in the memory section 20 according to the operation of the switch _S5 .

By performing such an operation every time each game ends, the score results of each game are stored in the memory unit 20 for each individual or team.

When the contents of the mode counter 11 are set to "2" by operating the switch _S1 , the score results of each game stored in the memory section 20 can be sequentially displayed. That is, when the content of the mode counter 11 is set to "2", the gate circuits G ₄ and G ₅ are opened and the content of the decimal counter 14 is provided to the memory section 20 . At this time, when the row address corresponding to the contents of the decimal counter 14 is specified, the memory section 20 receiving the read instruction reads the contents stored in each column of the specified row address in parallel. Output, gate circuit G ₅
is sent to the display unit 5 via the display unit 5 and displayed. Therefore, each time the switch _S5 is operated to increment the contents of the decimal counter 14, the row addresses of the memory section 20 are sequentially changed, so that the stored contents are read out and displayed for each row address. . This allows the player to know the results of each game up to that point during the game.

When the final game is finished, by operating the switch _S1 once to set the content of the mode counter 11 to "3", the total score for each individual or team can be displayed. That is, when the mode designation signal "3" is output from the mode counter 11, all the contents stored in the memory section 20 are sequentially read out for each column address, and the contents are read out sequentially for each column address. The signal is sent to the arithmetic unit 21 via the gate circuit _G6 which is opened.
Then, in the calculating section 21, the total score for each individual or team is calculated, and the total score is sent to the display section 5 and sequentially displayed.

In this way, each up/down counter 15 to 1
The contents of 8 are stored in the memory unit 20 each time each game ends, so during the game, the results of each game up to that point can be read out and displayed, and after the final game is over, the results of each game up to that point can be read out and displayed. It is possible to read the score results of each game for each individual or team from the memory section 20, and calculate and display the total score for each individual or team in the calculation section 21. Also, updown counter 1
5 to 18, each time switch _S3 is operated, the contents are subtracted by "-1", so in addition to being able to set negative values to up-down counters 15 to 18,
When correcting the values set in the up-down counters 15 to 18, the correction operation can be easily performed.

FIG. 7 shows the configuration of a display unit according to another embodiment of the present invention. In this embodiment, seven dots displaying the days of the week are used together to display the number of games played. This is what I did. With this configuration, it is possible to easily distinguish between the score display and the game count display.

If the game time is limited, a second display or a day of the week display may be used to display the elapsed time or remaining time of the game _. Although the up-down counter is selectively designated by operation, a switch corresponding to each up-down counter may be provided. Further, the number of up-down counters is not particularly limited.

Furthermore, the present invention can be used as a score display function for games such as baseball, playing cards, golf, and marziyan, and can also be incorporated into electronic devices other than electronic watches, such as small electronic calculators. .

As explained in detail above, the present invention includes a plurality of counter means 15, 16, 17, 18, and numerical data input means _S2 , _S3 , _S4 for inputting numerical data to each of the plurality of counter means. , a display means 5 for displaying numerical data from the plurality of counter means, a memory means 20 having a storage area capable of storing a plurality of numerical data of the plurality of counter means, and a display means 5 for displaying the numerical data from the plurality of counter means. switch means S5 for outputting a signal for storing the numerical data in the memory means 20 and clearing the numerical data of the plurality of counters; and a switch means _S5 for calculating the plurality of numerical data for each of the counter means stored in the memory means, It is equipped with a calculation means 21 for obtaining total numerical data for each means, and display control means 11 and 4 for displaying the total numerical data obtained by this calculation means. Even if you clear the contents of each counter and set a new value to each counter, you can read out the contents stored in the memory and display it, for example. You can know the contents of each counter up to. Further, by reading out the contents stored in the memory section, performing a predetermined calculation, and displaying the result of the calculation, for example, it is possible to know the total by type. Therefore, when used as a game score display function, it is extremely convenient.

[Brief explanation of drawings]

1 to 6 show an embodiment of the present invention, in which FIG. 1 is a circuit diagram of an electronic timepiece to which this invention is applied, FIG. 2 is a diagram of a display section, and FIG.
Figures 4 and 6 are diagrams showing display states, and Figure 5.
The figure shows the contents of the memory section, and FIG. 7 is a configuration diagram showing the display section of an electronic timepiece according to another embodiment of the present invention. 12...Selection counter, 3...Decoder, 15
~18...up/down counter, 20...memory section, _S2 ~ _S5 ...external operation switch.

Claims (1)

[Claims] 1. A plurality of counter means, a numerical data input means for inputting numerical data into each of the plurality of counter means, a display means for displaying numerical data from the plurality of counter means, and a display means for displaying numerical data from the plurality of counter means. a memory means each having a storage area capable of storing a plurality of storage areas; a switch means for outputting a signal for causing the numerical data of the plurality of counters to be stored in the memory means and for clearing the numerical data of the plurality of counters; a calculation means for calculating a plurality of stored numerical data for each counter means to obtain total numerical data for each counter means; and a display control means for displaying the total numerical data obtained by the calculation means. An electronic device with a counter function.