JPS6347926A - Exposing method of semiconductor - Google Patents

Abstract

PURPOSE:To enable the attainment of a high pattern resolution even in the exposure of a memory element having large difference in steps by a method wherein a memory element part pattern and a peripheral circuit part pattern are subjected separately to focus alignment and exposure by using the same wafer alignment pattern and the same reducing lens and by varying a shielding region for an exposure light. CONSTITUTION:A memory element part pattern 10a which is drawn on a photomask 1 and has a stepped part and a peripheral circuit part pattern 11a which consists of an address selecting circuit and others are exposed on a chip 5 on a wafer 4 through a reducing lens 3 by using a light beam from an exposure optical system 6. In such an exposing method of a semiconductor, the memory element part pattern 10a on the photomask 1 and the peripheral circuit part pattern 11a are subjected separately to focus alignment and exposure by using a single alignment pattern 24 of a wafer 4 and the single reducing lens 3 and by varying a shielding region of exposure light from the exposure optical system 6. For the aforesaid photomask 1, a photomask 1a for the memory element part pattern and a photomask 1b for the peripheral circuit part pattern are used, for instance, and these photomasks are switched over for exposure.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor exposure method performed in the manufacture of semiconductor integrated circuits, and in particular, to a method for realizing a high pattern resolution over the entire area of a chip. The present invention relates to a semiconductor exposure method suitable for.

[Conventional technology]

Conventionally, for highly integrated semiconductors with a pattern width of 1.5 μm or less, a reduction projection exposure apparatus or stepper that can achieve high resolution and alignment accuracy has been used.This reduction projection exposure apparatus is shown in FIG. 5, for example. A circuit pattern 2 drawn on a photomask (or reticle) is exposed onto a wafer 4 every one to several chips 5 through a reduction lens 3. Note that 6 shown in FIG. 5 is an exposure optical system.

The reduction lens 3 has a depth of focus, similar to an objective lens used in a microscope. In general, the depth of focus is determined by the contrast [or modulation transfer function] for the desired fine repeating pattern.
Transfer Function)
(MTF) ) indicates a region of 60% or more, and by approximating this, a relationship such as the following equation (1) is obtained.

However, ΔZ is the depth of focus, λ is the wavelength, and NA is the numerical aperture (numerical aperture).
perture)).

For example, in an i-line (λ=ρ, 365 μm) stepper used in 0.8 μm process manufacturing, the NA is 0.
If it is about 42, ΔZ will be only about 1 μm.

An automatic focus function is provided for this purpose, but when considering error factors such as the field curvature of the reduction lens, wafer warpage and tilt, and the correction accuracy of the automatic focus function, it is possible to It is necessary to suppress the steps as much as possible.

Therefore, a multilayer resist method is often used to expose patterns with large step differences. In this method, as shown in FIG. 6, a thick flattening resist layer 8 is first applied to a base layer 7 having a high level difference, and a thin resist layer 9 contributing to exposure is provided thereon.

The problem of depth of focus can be solved by exposing only the exposed resist layer 9 after planarization.

Note that after exposure and development, the flattened resist N8 is removed by a method such as reactive etching.

[Problem that the invention seeks to solve]

Among semiconductor integrated circuits, dynamic RAM (RAM)
In a so-called one-chip microprocessor having a built-in memory such as a static RAM and a memory, as shown in FIG. The peripheral circuit section 11 is clearly separated from the peripheral circuit section 11 because the memory element section 10 includes a capacitor for storing charge and an mFM for separating adjacent elements.
A pattern with high steps having a height of 1 to 2 μm is formed.

Therefore, as shown in FIG. 8, the base layer 7 is formed between the memory element section 10 at the high step portion and the peripheral circuit section 11 at the low step section.
Because the flattening resist 8 cannot obtain a sufficient effect, it is difficult to obtain sufficient effects from the flattening resist 8. Therefore, if the step is as large as 1 to 2 μm, exposure within the depth of focus becomes impossible and the pattern is not sufficiently formed. Couldn't get resolution.

Furthermore, conventionally, in addition to the multilayer resist method, an electron beam direct writing method and a method of increasing the pattern size of the peripheral circuit section 11 have been used.

However, the electron beam direct writing method has a problem in that the throughput decreases significantly, and in the method of making the pattern of the peripheral circuit section 11 thicker, in order to focus on the memory element section 10, the peripheral circuit section 11 side may be out of focus. There is a problem that it is difficult to obtain stable performance.

In order to further reduce the level difference, as shown in FIG. 8, polysilicon (P) is
oly-St) and phospho-silica tit glass (
A method of providing a flattening layer 12 made of Phospho 5-Ilicate Glass) or the like may also be considered.

However, this method has the problem of increasing the number of steps and manufacturing costs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor exposure method that solves the above-mentioned conventional problems and enables high pattern resolution even when exposing a memory element having a high level difference.

Means for Solving Problem C] The above purpose is to improve the alignment pattern of the same wafer,
This is accomplished by separately focusing and exposing the memory element pattern and the peripheral circuit pattern on the photomask using the same reduction lens and changing the shielding area of the exposure light from the exposure optical system.

[For production]

The present invention provides a memory element portion 10 in a high step portion as shown in FIG.
For exposure, the wafer (not shown) is moved up and down to focus on the area 12 on which the thin resist layer 9 is provided on the high-step area, and the peripheral circuit area on the low-step area is exposed. Since exposure is performed by moving the wafer up and down and focusing on the area 13 where the thin resist layer 9 is provided on the step part, high pattern resolution can be achieved over the entire area of the chip (not shown). Obtainable.

In this case, the present invention is characterized by the following points. That is, (11 single reduction lenses are used.

(2) Alignment marks on a single wafer are used.

(3) The area where the exposure light from the exposure optical system is blocked can be changed. The reason for this is: (4) Regarding (1) above, since the distortion is actually different for each reduction lens, using different reduction lenses will result in a finer pattern, which will cause non-negligible distortion in the overlapping part. be.

(5) Regarding (2) above, this is because the alignment pattern on the wafer actually has a slightly different shape and dimension for each alignment pattern, and it is impossible to manufacture them in the same way.

(6) Regarding (3) above, when exposing the memory element pattern and the peripheral circuit pattern on the photomask separately, since the exposure optical system of the vehicle body is used, the irradiation area is divided into the memory element pattern and the peripheral circuit pattern. This is for alignment with the partial pattern. That is, if exposure light is irradiated onto a light-shielding pattern other than the memory element pattern and peripheral circuit pattern on the photomask, defects such as pinholes existing in the light-shielding pattern will be affected.

Therefore, the present invention can also solve the above-mentioned problems, thereby making it possible to obtain high pattern resolution over the entire area of the chip.

〔Example〕

Hereinafter, FIGS. 1(a) to 1(C) showing one embodiment of the present invention will be described. FIG. 1(a) is an explanatory diagram of the main parts of a semiconductor exposure apparatus which is an embodiment of the present invention, FIG. 1(b) is a front view of the photomask on the memory element side directly shown in FIG. C) is a front view of the photomask on the peripheral circuit side shown in FIG. 1 (al), and FIG. 1 (61 is a front view of the chip shown in FIG. 1 (al). to 8th
Illustrated with the same reference numerals as in the figure.

In the figure, la and lb are two photomasks (or reticles), and a pattern 10a of the memory element section 10 is drawn on one photomask 1a, and this pattern 10a
A light shielding pattern 20a is formed in the other parts, and two alignment patterns 23a are formed at orthogonal positions around the periphery.
23b is provided. Further, the other photomask 1b draws the pattern lla of the peripheral circuit section 11, forms a light-shielding pattern 20b in a portion other than this pattern 10a, and draws the two alignment patterns 23 that are perpendicular to each other in the periphery.
Two alignment patterns 23c and 23d are provided at the same positions as a and 23b. 21a and 21b are two light shielding plates called masking blades,
It is provided to be movable in mutually opposite horizontal directions between the exposure optical system 6 and the two photomasks la and lb, and when the exposure light 6a from the exposure optical system 6 irradiates the photomask 1a or 1b. , the light shielding pattern 20a,
In order to prevent the shadow U of defects such as pinholes existing in the light shielding patterns 20a and 20b by irradiating the light shielding patterns 20b, the distance between the two light shielding plates 21a and 21b is adjusted to 9.1 to form a 93-light optical system. Control the mask of the exposure light 6a from 6; 1(l
I'm doing it like I'm doing it. 22 is an alignment optical system,
Alignment marks 23a, 23b, 23 on the photomask 1a or lb through the reduction lens 3
The positions of the photomask 1a or 1b and each chip 5 of the wafer 4 are detected by the alignment light irradiated onto the photomask 23d and the alignment lights 24a and 24b provided on each chip 5 of the wafer 4, and the two are aligned. It's like that. 26 has a Z8IJ structure, and the wafer stage 27 moves on the slope 27a in a corresponding manner (when moved horizontally via the formed slope 26a, the height direction position of the wafer 4 placed on the upper surface is 28 is an automatic focusing mechanism, and an air micro 25 provided at the tip of the reduction lens 3 and the Z mechanism 26 are used.
The automatic focus offset is changed depending on the photomask 1a or 1b to control the movement of the Z mechanism 26.

Since the semiconductor exposure apparatus, which is one embodiment of the present invention, is constructed as described above, its operation will be explained next.

First, the photomask 1a or 1b to be exposed is placed at the position of the exposure light 6a of the exposure optical system 6, and then the alignment optical system 22 aligns the photomask la or 1b with alignment marks 23a, 23b, 23c, 23d.
and the alignment mark 24a of each chip 5 on the wafer 4,
24b and align the two, and the automatic focus mechanism 28 aligns the focal position of the photomask 1a or lc. In addition, two light shielding plates 21a,
21b in opposite directions to adjust the distance between them, and the exposure light 6a is directed from the exposure optical system 6 to the photomask 1.
The pattern 10a or Ila of a or 1b is irradiated.

In this way, the photomask 1a or 1b and the wafer 4
Once the position of each chip 5 is determined, the exposure optical system 6
The pattern 10a or lla of the photomask 1a or 1b is exposed onto each chip 5 of the wafer 4 through the reduction lens 3 by the exposure light 6a from the photomask 1a or 1b.

Then, when exposing another photomask 1b or 1a, the pattern 11. of the other photomask 1b or 1a is exposed using the same method as described above. a or 10a can be exposed onto each chip 5 of the wafer 4.

In this case, in the present invention, two photomasks fat1b
Since the same reduction lens 3 is used when exposing the memory element section 10 and the peripheral circuit section 1, distortion can be prevented from occurring at the boundary between the memory element section 10 and the peripheral circuit section 1.

Furthermore, when positioning the alignment patterns 23a and 23b of the two photomasks la and lb with the alignment patterns 24a and 24b of the wafer 4, since the alignment pattern 24a of the same wafer 4 is used, the alignment patterns 23a and 23b of the two photomasks la and lb are used. , lb can be positioned at the same position.

Furthermore, since the two photomasks la and Ib are positioned separately, even if there is a step between the two photomasks la and lb, the automatic focusing mechanism 28 allows the memory element portion of the high step to be moved as shown in FIG. By focusing on the uppermost portion 12 of the chip 10 and the uppermost portion 13 of the peripheral circuit section 11 in the low step portion, a high pattern resolution can be obtained over the entire area of the chip 5.

Next, FIG. 2 (aL (bl) shows a semiconductor exposure apparatus which is another embodiment of the present invention.

The figure shows a case where a pair of light shielding plates 21a, 21b called masking blades are provided at a position optically conjugate with the position of the photomask in the exposure optical system 6. The specific structure is, for example, the patent application No. 137702 filed earlier by the applicant of the present application.
No. (Japanese Unexamined Patent Publication No. 60-30132), the main part of which is shown in Fig. 2 (Cl+fd), has four blades 2101.2102.2103.2104,
The direction mask 2105 and the Y direction mask 2106 are identically constructed with the same elements, and the X frame 2107. which is the base of each mask 2105.2106. A Y frame 2108 is fixed to the frame 601 of the exposure light source 6. The X-tolem 210 has a hollow structure, and the X-blade 2101 and the X-blade 2102 slide on the hollow portion. The curfew of the X Twolem 2107 is the X blade drive wheel 2109.2110.211L
2112 is provided, and each drive wheel 2109, 2110 is driven by an independent drive motor 2113, 21M, respectively. Further, the X-blade drive wheel 2109 has an X-blade drive roller 2115 fixed to the drive shaft of the X-blade drive morph 2113, and an X-blade drive motor 2116 that freely rotates around the motor shaft. The X-blade drive wheel 2110 has an X-blade drive roller 2118 fixed to the motor shaft of an X-blade drive motor 2117, and an X-blade drive roller 2119 that freely rotates around the motor shaft. Each of the motors 2116.2
The shaft of 117 has a step (not shown), and the X-blade drive roller 2115 in the case of the X-blade drive wheel 2109 and the X-blade drive roller 2119 in the case of the X-blade drive wheel 2110 hit this step, respectively. X blade drive roller 2116. An X-blade drive roller 2118 is attached and the lowest end is stopped by a collar 2120. Further, the X rolling wheels 2111 and 2112 each consist of two freely rotating transfer rollers, upper and lower. Endless X blade drive wires 2121 and 2122 are fitted into the upper and lower two rollers at the four corners of the X tool 2107, and the X blade drive wire 2122 is an The rotation of the motor is transmitted by an X-blade drive roller 2115 screwed to the motor shaft of the blade drive motor 2113, so that the X-blade 2101 slides within the hollow portion of the X-tool 210. Similarly to the X-field movable wire 2121, the X-flade movable wire 2122 is adapted to cause the X-blade 2102 to slide within the hollow portion of the X-blade 2101.

As described above, by controlling the rotation of the X blade drive motor 2113, it becomes possible to control the opening and closing of the X blades 2101 and 2102.

The Y-direction mask 2106 is also exactly the same as the X-direction mask 2105, and with these, a desired portion of the wafer 4 can be freely marked.
Can be masked from any direction.

Although the method of opening and closing the four blades 2101, 2102, 2103, and 2104 is shown in FIG. 2 (C1, (d)), the method is not limited to this.
, for example, as shown in FIG. 3 (2 glass plates 29a).

Transmissive portions 30a, 30b and light shielding portions 31a are provided on 29b.
31b is provided, and this is inserted through the holder 32 in FIG.
The same effect can be obtained by switching at the position 21 shown in FIG.

Next, FIGS. 4(a) and 4(bl) are explanatory diagrams showing essential parts of a semiconductor exposure apparatus which is still another embodiment of the present invention.

This figure basically has the same configuration as FIGS. 10a and lla, and four alignment marks 23a, 23b, 23c, and 23d are provided, and by moving this one photomask 1 in the direction of the arrow and interlocking the light-shielding plates 21a and 21b, the photomask is drawn on the wafer 4. The desired slope is exposed.

In this case, the size of one photomask 1 is the same as that of the first photomask 1.
Although the size is larger than that shown in the figure, on the other hand, the switching time can be shortened compared to switching between two photomasks la and lb.

Furthermore, in each of the embodiments described above, an automatic focusing mechanism 28 is shown in which the reduction lens 3 is provided with an air micro 25, but the present invention is not limited to this, and for example, an optical automatic focusing mechanism may also be used. be.

〔Effect of the invention〕

According to the present invention, even if there is a large step difference between the memory element part and the peripheral part as in highly integrated semiconductor memory, exposure can be performed within the depth of focus over the entire area, achieving high pattern resolution. Therefore, it is possible to contribute to improving the yield of semiconductor manufacturing and improving the margin in mechanical control.

[Brief explanation of the drawing]

FIG. 1(a) is an explanatory diagram of the main parts of a semiconductor exposure apparatus which is an embodiment of the present invention, and FIG. 1(b) is a front view of the photomask on the memory element side shown in FIG. Figure (C) is the first
A front view of the photomask on the peripheral circuit side shown in Figure (a), Figure 1 (dl is a front view of the chip shown in Figure 1(a),
FIG. 2(a) is an explanatory diagram of the main parts of a semiconductor exposure apparatus which is another embodiment of the present invention, FIG. 2('b) is a front view of the photomask shown in FIG. 2(a), and FIG. ) is a perspective view of the light-shielding plate shown in FIG. 2(a), FIG. 2(dl is a detailed perspective view of a portion of FIG. 2(C)), and FIG. FIG. 4(a) is a front view of one example, and FIG.
) is a front view of the photomask shown in FIG. 4 (51), FIG. 5 is an explanatory diagram of the main parts of the reduction exposure device, FIG. Fig. 8 is a cross-sectional view of the chip. 1... Photomask, 2... Circuit pattern, 3...
Reduction lens, 4... wafer, 5... chip, 6...
- Exposure optical system, 10... Memory element section, 11... Peripheral circuit section, 20... Light shielding pattern, 21... Light shielding plate, 23.24... Alignment mark, 25... Air micro , 26...Z mechanism, 27...wafer stage, 28...automatic focus mechanism, 29...glass plate,
30... Transmissive part, 31... Light shielding part, 32... Holder. Agent Patent Attorney Tadashi Akimoto Figure 1 Figure 2 (a) 21. 4 ”118 11.Wlj21 Enchincho'-2
8M movement, Ri5 5 Nuppu 20Jfi4/Matern 25: rγ Micro Fig. 2 (C) (d) Fig. 3 2101-2104 9-Re 32 Hoffrek... Fig. 4 (a) 5 + Tour 20" 1 roll 262 patterns (Lecture 5)

Claims (1)

[Claims] 1. A memory element pattern with steps drawn on a photomask using a light beam from an exposure optical system and a peripheral circuit pattern consisting of an address selection circuit, etc. are transferred to a wafer through a reduction lens. In a semiconductor exposure method for exposing a chip on a photomask, an alignment pattern of a single wafer and a single reduction lens are used to change a light shielding area of exposure light from the exposure optical system to expose the memory element portion on the photomask. A semiconductor exposure method comprising separately focusing and exposing a pattern and the peripheral circuit pattern. 2. The semiconductor exposure method according to claim 1, wherein the photomask is a photomask for the memory element pattern and a photomask for the peripheral circuit pattern, and exposure is performed by switching between them. 3. The semiconductor exposure method according to claim 1, wherein the photomask draws the memory element pattern and the peripheral circuit pattern at intervals. 4. Changing the shielding area of the light beam from the exposure optical system and moving the photomask to position the memory element pattern and the peripheral circuit pattern on the photomask, respectively, near the center of the optical axis of the light beam; A semiconductor exposure method according to claim 1, characterized in that: