JPS6347843A - Interrupting system for processing in execution - Google Patents

Interrupting system for processing in execution

Info

Publication number
JPS6347843A
JPS6347843A JP19135786A JP19135786A JPS6347843A JP S6347843 A JPS6347843 A JP S6347843A JP 19135786 A JP19135786 A JP 19135786A JP 19135786 A JP19135786 A JP 19135786A JP S6347843 A JPS6347843 A JP S6347843A
Authority
JP
Japan
Prior art keywords
interrupt
interruption
processing
asynchronous
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19135786A
Other languages
Japanese (ja)
Inventor
Mika Yanaihara
矢内原 美香
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19135786A priority Critical patent/JPS6347843A/en
Publication of JPS6347843A publication Critical patent/JPS6347843A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4812Task transfer initiation or dispatching by interrupt, e.g. masked

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To limit an interruption module even by a condition other than an execution key, by searching the stack of a processing in execution after applying interruption on the processing by an asynchronous indexing, and performing the interruption designation of a specific stack frame. CONSTITUTION:An asynchronous indexing receiving means 14 delivers control to an interrupting position selection means 15 in a case to limit the interruption module by the condition other than the execution key, and decides the condition of the interruption module based on the cause of the generation of an interruption request, and searches the stack frame of a module which satisfies the condition. An interrupting position designating means 16 turns ON an interruption designating flag for a selected stack frame, and stores a bit of information regarding a processing performed at time of interruption, in a processing control structure 19. Hereafter, the ordinary processing of an interruption object processing 12 is performed, however, when the interruption designating flag is set at an ON-state, the control is delivered to an interruption receiving means 17, and the processing control structure 19 is referred, and the processing to be performed at time of the interruption is executed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は実行中プロセスに対する割り込み方式に関し、
特に情報処理タスク管理における実行中プロセスに対す
る割り込み方式に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an interrupt method for a running process;
In particular, it relates to interrupt methods for running processes in information processing task management.

〔従来の技術〕[Conventional technology]

従来の実行中プロセスに対する割り込み方式においては
、プロセス制御構造体中の非同期割り出しビット及び非
同期割り出し実行キ一番号をセットし、実行モジュール
の実行キーが前記非同期割り出し実行キ一番号と、同じ
かより大きくなったときに非同期割り出し例外を発生さ
せる方式がとられていた。
In the conventional method of interrupting a running process, an asynchronous interrupt bit and an asynchronous interrupt execution key number in the process control structure are set, and the execution key of the execution module is the same as or larger than the asynchronous interrupt execution key number. The method used was to generate an asynchronous index exception when the error occurred.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の実行プロセスに対する割り込み方式にお
いては、割り込むモジュールを実行キーでしか区別でき
ないという欠点がある。
The above-described conventional method of interrupting an execution process has a drawback in that the interrupting module can only be distinguished by the execution key.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の実行中のプロセスに対する割り込み方式は、割
り込み対象プロセスに非同期割り出し例外を発生させる
非同期割り出し指定手段と、非同期割り出し指定手段に
より指定した例外発生時に制御をうけとる非同期割り出
し受け取り手段と、割り込み条件を決定し、条件に合致
したモジュールをサーチする割り込み箇所選択手段と、
割り込み箇所選択手段により選択したモジュールで例外
を発生させる割り込み箇所指定手段と、割り込み箇所指
定手段により指定した例外発生時に制御が渡される割り
込み受け取り手段とを有している。
The method of interrupting a running process according to the present invention includes an asynchronous interrupt specifying means for generating an asynchronous interrupt exception in an interrupt target process, an asynchronous interrupt receiving means for receiving control when an exception specified by the asynchronous interrupt specifying means occurs, and an asynchronous interrupt receiving means for determining an interrupt condition. an interrupt location selection means for determining and searching for a module that meets the conditions;
It has interrupt point specifying means for generating an exception in the module selected by the interrupt point selecting means, and interrupt receiving means to which control is passed when the exception specified by the interrupt point specifying means occurs.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示す。第1図において、本
実施例は割り込み要求プロセス11と、割り込み対象プ
ロセス12とを有し、割り込み要求プロセス11側には
非同期割り出し指定手段13を設け、割り込み対象プロ
セス12側には非同期割り出し受けとり手段14、割り
込み箇所選択手段15、割り込み箇所指定手段16、割
り込み受けとり手段17、スタック18およびプロセス
制御構造体19を設けて構成されている。
FIG. 1 shows an embodiment of the invention. In FIG. 1, this embodiment has an interrupt request process 11 and an interrupt target process 12, an asynchronous interrupt specifying means 13 is provided on the interrupt request process 11 side, and an asynchronous interrupt receiving means is provided on the interrupt target process 12 side. 14, interrupt point selection means 15, interrupt point specifying means 16, interrupt receiving means 17, stack 18, and process control structure 19.

第2図は本実施例におけるスタック構造を示す。第2図
において、第1図に示す割り込み対象プロセス12のス
タック18はスタックフレーム81〜83を含み、これ
らのスタックフレーム81〜83はそれぞれモジュール
84〜86に対応するものである。
FIG. 2 shows the stack structure in this embodiment. In FIG. 2, the stack 18 of the interrupt target process 12 shown in FIG. 1 includes stack frames 81-83, and these stack frames 81-83 correspond to modules 84-86, respectively.

第3図乃至第7図は本実施例における各手段の流れを示
す。
3 to 7 show the flow of each means in this embodiment.

次に、本実施例の動作について説明する。本実施例は割
り込み要求プロセス11により実行中プロセス12に対
して割り込み要求が発生した場合、割り込み要求プロセ
ス11の非同期割り出し指定手段13がステップ31(
第3図)の割り込み要求が発生した原因に基づいて非同
期割り出し実行キ一番号の値を決定し、ステップ32で
割り込み対象プロセス12のプロセス制御構造体19中
の非同期割り出しビットをONにし、さらにステップ3
3の非同期割り出し実行キ一番号格納領域にこの非同期
割り出し実行キ一番号の値を格納する。
Next, the operation of this embodiment will be explained. In this embodiment, when an interrupt request is generated by the interrupt request process 11 to the executing process 12, the asynchronous interrupt specifying means 13 of the interrupt request process 11 is executed in step 31 (
The value of the asynchronous interrupt execution key number is determined based on the cause of the occurrence of the interrupt request in FIG. 3
The value of this asynchronous index execution key number is stored in the asynchronous index execution key number storage area 3.

割り込み対象プロセス12の制御は、非同期割り出しビ
ット及び非同期割り出し実行キ一番号がセットされた後
、割り込み対象プロセス12の実行モジュールの実行キ
ーが非同期割り出し実行キ一番号と同じかより大きくな
り、非同期割り出し例外が発生すると、非同期割り出し
受け取り手段14に渡される。
The control of the interrupt target process 12 is such that after the asynchronous interrupt bit and the asynchronous interrupt execution key number are set, the execution key of the execution module of the interrupt target process 12 becomes equal to or greater than the asynchronous index execution key number, and the asynchronous interrupt is executed. When an exception occurs, it is passed to the asynchronous index receiving means 14.

非同期割り出し受け取り手段14は、判断ステップ41
(第4図)においてモジュールの実行キー以外で割り込
みモジュールを、さらに限定しなければならないか判断
し限定すべき場合にはステップ42において割り込み箇
所選択手段15へ制御を渡す。限定しない場合はステッ
プ43において割り込み時に行うべき処理を実行する。
The asynchronous index receiving means 14 performs the judgment step 41.
(FIG. 4), it is determined whether the interrupt module needs to be further limited using a method other than the module execution key, and if it is necessary to limit the interrupt module, control is passed to the interrupt location selection means 15 in step 42. If there is no limitation, the processing to be performed at the time of an interrupt is executed in step 43.

割り込み箇所選択手段15は、ステップ51(第5図)
において割り込み要求の発生原因に基づいて割り込みモ
ジュールの条件を決定し、判断ステップ52およびステ
ップ53においてスタックのホストを順次参照して条件
に合致したモジュールのスタックフレームをサーチする
The interrupt point selection means 15 performs step 51 (FIG. 5).
In step 52, conditions for the interrupt module are determined based on the cause of the interrupt request, and in decision step 52 and step 53, the hosts in the stack are sequentially referred to to search for a stack frame of a module that meets the conditions.

割り込み箇所指定手段16は、ステップ61(第6図)
において選択手段15で選択したスタックフレームに対
し、割り込み指定フラグをONにし、同時にステップ6
2においてプロセス制御構造体中に割り込み時に行う処
理についての情報を格納する。ここで割り込み指定フラ
グとして使用するビットは本来Oでなければならないビ
ットである。
The interrupt point specifying means 16 performs step 61 (FIG. 6).
At step 6, the interrupt designation flag is turned ON for the stack frame selected by the selection means 15, and at the same time, step 6
In step 2, information about processing to be performed at the time of an interrupt is stored in the process control structure. The bit used as the interrupt designation flag here should originally be O.

割り込み箇所指定後は割り込み対象プロセス12の通常
の処理が行われるが、リターン(RE TURN)命令
によりホストの浅いモジュールに制御が戻るとき、この
モジュールに対応するスタックフレームの割り込み指定
フラグがONであれば例外が発生し、割り込み受け取り
手段17に制御が渡される。この例外発生について第2
図を参照しながら説明するとモジュール85が割り込み
条件に合致したモジュールであるとき、スタックフレー
ム82の割り込み指定フラグをONにする。
After specifying the interrupt location, normal processing of the interrupt target process 12 is performed, but when control is returned to a shallow module of the host by a return (RE TURN) instruction, even if the interrupt specification flag of the stack frame corresponding to this module is ON. If an exception occurs, control is passed to the interrupt receiving means 17. Regarding this exception occurrence, the second
To explain with reference to the figure, when the module 85 is a module that meets the interrupt condition, the interrupt designation flag of the stack frame 82 is turned ON.

プロセスの通常処理中モジュール86のRETURN命
令実行時、スタックフレーム82の割り込み指定フラグ
がONであることが検出され例外が発生する。
When the RETURN instruction of the module 86 is executed during normal processing of the process, it is detected that the interrupt designation flag of the stack frame 82 is ON, and an exception occurs.

割り込み受けとり手段17は、ステップ71(第7図)
においてプロセス制御構造体1つを参照し、ステップ7
2において割り込み時に行うべき処理を実行する。
The interrupt receiving means 17 performs step 71 (FIG. 7).
refer to one process control structure in step 7
In step 2, the processing to be performed at the time of an interrupt is executed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、非同期割り出しによって
実行中プロセスに割り込んだ後、そのプロセスのスタッ
クをサーチし特定のスタックフレームに対して割り込み
指定を行うことにより、モジュールの実行キー以外の条
件によっても割り込みモジュール分限定できる効果があ
る。
As explained above, the present invention interrupts a running process by asynchronous allocation, searches the stack of that process, and specifies an interrupt for a specific stack frame. This has the effect of limiting the number of interrupt modules.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す図、第2図は割り込み
モジュールでの割り込みのための例外発生について説明
するための図、第3図乃至第7図は処理の流れを示す図
である。 11・・・割り込み要求プロセス、12・・・割り込み
対象プロ・セス、13・・・非同期割り出し指定手段、
14・・・非同期割り出し受け取り手段、15・・・割
り込み箇所選択手段、16・・・割り込み箇所指定手段
、17・・・割り込み受けとり手段、18・・・スタッ
ク、19・・・プロセス制御構造体。 、′
FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining the occurrence of an exception due to an interrupt in an interrupt module, and FIGS. 3 to 7 are diagrams showing the flow of processing. be. 11... Interrupt request process, 12... Interrupt target process, 13... Asynchronous interrupt specification means,
14... Asynchronous interrupt receiving means, 15... Interrupt point selecting means, 16... Interrupt point specifying means, 17... Interrupt receiving means, 18... Stack, 19... Process control structure. ,′

Claims (1)

【特許請求の範囲】[Claims] 割り込み要求プロセスから実行中の割り込み対象プロセ
スに対し割り込み要求する割り込み方式において、割り
込み対象プロセスに非同期割り出し例外を発生させる非
同期割り出し指定手段と、該非同期割り出し指定手段に
より指定した例外発生時に制御が渡される非同期割り出
し受け取り手段と、割り込み条件を決定し、条件に合致
したモジュールをサーチする割り込み箇所選択手段と、
該割り込み箇所選択手段により選択したモジュールで例
外を発生させる割り込み箇所指定手段と、該割り込み箇
所指定手段により指定した例外発生時に制御が渡される
割り込み受け取り手段とを設けたことを特徴とする実行
プロセスに対する割り込み方式。
In an interrupt method in which an interrupt requesting process requests an interrupt from an executing interrupt target process, an asynchronous interrupt specifying means generates an asynchronous interrupt exception in the interrupt target process, and control is transferred when an exception specified by the asynchronous interrupt specifying means occurs. an asynchronous interrupt receiving means; an interrupt location selecting means for determining an interrupt condition and searching for a module matching the condition;
An execution process characterized by comprising an interrupt point specifying means for generating an exception in a module selected by the interrupt point selecting means, and an interrupt receiving means to which control is transferred when the exception specified by the interrupt point specifying means occurs. Interrupt method.
JP19135786A 1986-08-15 1986-08-15 Interrupting system for processing in execution Pending JPS6347843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19135786A JPS6347843A (en) 1986-08-15 1986-08-15 Interrupting system for processing in execution

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19135786A JPS6347843A (en) 1986-08-15 1986-08-15 Interrupting system for processing in execution

Publications (1)

Publication Number Publication Date
JPS6347843A true JPS6347843A (en) 1988-02-29

Family

ID=16273229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19135786A Pending JPS6347843A (en) 1986-08-15 1986-08-15 Interrupting system for processing in execution

Country Status (1)

Country Link
JP (1) JPS6347843A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5960651A (en) * 1982-09-30 1984-04-06 Fujitsu Ltd System for managing control transition between modules

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5960651A (en) * 1982-09-30 1984-04-06 Fujitsu Ltd System for managing control transition between modules

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