JPS634732A - Decentralizing processing type private branch exchange system - Google Patents

Abstract

PURPOSE:To contrive to evade the function stop of the entire system due to a fault of an equipment while making the best use of the advantages of the decentralizing processing by collecting the master clock of each node through other line and deciding the master clock for the entire system as the method synchronizing among nodes. CONSTITUTION:A trunk line synchronization display bit SCD is provided between a frame check sequence FCS and an end delimiter ED. A network clock 9 coming from a token ring 4 passes through a digital phase synchronizing circuit 13 and is fed to transmission interfaces 170, 171, 172 so long as a trunk line clock 14 is not selected by a master clock selection circuit 11 depending on the relation between a communication trunk line display circuit 8 of a token control section 6 and a clock master decision circuit 7. The communication trunk line display circuit 8 checks whether or not a trunk line clock 14 is outputted from a communication state trunk line retrieval section 12 and display '1' (at the presence of a busy trunk line) and '0' (in the absence of the busy trunk line) to a bit assigned to its own node of a trunk line synchronization display bit SCD of a circulated token frame to apply relaying.

Description

DETAILED DESCRIPTION OF THE INVENTION (+FFI Field of Application) The present invention relates to a private branch exchange system, and particularly to a distributed processing type private branch exchange system that controls transmission rights between nodes by token passing.

(Prior Art) Conventionally, private branch exchange systems to which digital subscriber lines are connected have only had central processing units. FIG. 4 is a block diagram of the synchronous clock selection circuit in this case. In order for the exchange to perform normal office line communication, signal transmission to the office line and extension lines must be performed using a clock synchronized with the network clock. Furthermore, it is advantageous to use the master clock for internal communication in terms of simplifying the circuit configuration. - On the other hand, since peer communication is established for each call in central office line communication,
Since it is impossible to extract the network clock from a specific office line, the communicating office line cable section 30 automatically hunts the communicating office line and extracts the network clock from it. The master clock 31 is connected to the central office line search unit 30 by the digital phase synchronization circuit 28 provided in the basic unit (tl:CLI) 27.
This occurs when there is a station line in communication, and the transmission interface circuit 33°, 3:] of the station line interface section 32
, :]3. It is supplied to various circuits in the device through.

(Problems to be Solved by the Invention) When the conventional synchronous clock selection circuit described above is applied to a distributed processing type private branch exchange system, synchronization is achieved between each node and the network clock, but synchronization between nodes is achieved. It's out of sync. Therefore, in order to synchronize nodes, the master clocks of each node must be collected on separate lines to determine the master clock for the entire system.

However, this method has the disadvantage that it cannot take advantage of the characteristics of molecular li processing because it is connected to each node via a separate line other than the token ring. Additionally, a device is required that selects the master clock for the entire system from among the master clocks of each node and supplies it to the system. Furthermore, if this device fails, clocks will no longer be supplied to all nodes and the entire system will stop functioning.

(Means for Solving the Problems) The distributed processing type private branch exchange system of the present invention has a central office line synchronization display bit or a token frame that indicates the presence or absence of a central office line in communication in each node constituting the switching system. It determines whether or not there is a station line in use based on the output of the communication middle cable cable section, and sends the result to the bit assigned to its own node in the station line synchronization display bit of the circulating token frame. A communication station line display circuit to display, a master clock selection circuit which selects the station line clock or network clock selected in the communication middle line cable section and outputs it to a digital phase synchronization circuit which extracts the master clock, and When the local node synchronization display bit of the token frame is checked and it is determined that the local node is the node with the highest priority that has the station line in communication, the clock master determination circuit selects the station line clock using the master clock selection circuit. Each node is characterized by having:

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the distributed processing type private branch exchange system of the present invention.

The distributed processing type horizontal switching system 5 is connected to the digital subscriber line 2.
゜、2. ．． 22 to the public network 1. The distributed processing type private branch exchange system 5 includes nodes 3°, 31, 32, . . . each having a central processing unit. It is configured by being connected to the node 33 or the token ring 4. Physically, the connection between the public network 1 and the local system 5 is as follows: Node 3° has 0 digital subscriber lines 2, Node 31 has 0 digital subscriber lines 21, and Node 32 has 0 digital subscriber lines 2. It is held on the public line 22.

FIG. 3 is a configuration diagram of a token frame used in this embodiment. The difference from the conventional token frame is that a station line synchronization indicating bit SCD is provided between the frame check sequence FC5 and the end delimiter ED. The office line synchronization display bit SCO is composed of the same number of bits (in this case, 4 bits long) as the number of nodes making up the premises system 5, and indicates the presence or absence of the office line in communication at each node 3° to 33. do. Specifically, if there is a station line in use, it will be "1",
If not, "0" is displayed in the station line synchronization display bit SCD. Note that the priorities of nodes 3 to 33 are set in advance, and bits m0 to m3 are assigned to each node according to the priority. In this case, the node assigned to bit m0 has the highest priority. High rank, below, bit mI
,"2 + m3, the priority order becomes lower.

FIG. 1 is a block diagram of a synchronous clock selection circuit included in each node 3Q to 33. The digital subscriber lines 2° to 22 enter from the office line interface section 16, and one of them is selected by the communication midline cable section 12 of the clock selection section 10. - On the other hand, the network clock 9 that comes in from the token link 4 will be used unless the station line clock 14 is selected by the master clock selection circuit 11 due to the relationship between the communication station line display circuit 8 of the token control unit 6 and the clock master determination circuit 7. It passes through the digital phase synchronization circuit 13 and is connected to the transmission interface 1.
7°, +7. , +72. The communication station line display circuit 8 receives the station line clock 1 from the station line cable section 12 during communication.
Check if 4 is being output and if there is a station line in use.
If there is no "1", "0" is displayed on the bit assigned to the own node of the station line synchronization display bit SCD of the token frame that has been circulating, and the clock master If the decision circuit 7 detects the station line synchronization display bit SCD and determines that the own node is the node with the highest priority that has the station line in communication, the master clock selection circuit 11 selects the station line clock 14. Select digital phase synchronization circuit I3
Extract the clock using the master clock 15 of the own node.
The entire campus system 5 is synchronized. However, node 3
A node that is not connected to the public network 1 through a digital subscriber line, such as No. 3, can become a clock master, but always operates as a slave.

〔Effect of the invention〕

As explained above, the present invention has the advantage of being able to take advantage of the characteristics of distributed processing by collecting the master clocks of each node on separate lines and determining the master clock of the entire system as a method for synchronizing nodes. Furthermore, the method described above eliminates the need for a device that selects the master clock for the entire system from among the master clocks of each node and supplies it to the system, resulting in an increase in the amount of hardware.
This has the effect of reducing the amount of electricity and preventing the entire system from stopping due to failure of this device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the synchronous clock selection circuit in each node 3 to 33 in FIG. 2, FIG. 2 is a block diagram of an embodiment of the distributed processing type private branch exchange system of the present invention, and FIG. FIG. 4, which is a block diagram of a token frame used in the embodiment, is a circuit diagram of a conventional example of a synchronous clock selection circuit. 1...Public network, 2°, 21, 23...Digital subscriber line, 3°, 3
．． ．． 32.33...Node, 4...Token ring, 5...Distributed processing private branch exchange system, 6...Token control unit, 7...Clock master determination circuit, 8...Communication station line Display circuit, 9...Network clock, 10...Clock selection section, 11...Master clock selection circuit, 12...Communication station line cable section, +3...Digital phase synchronization circuit, ■... - Office line clock, 15... Master clock, 16... Office line interface section, 17°, +7. , +72...transmission interface circuit, PA--preamble, SD...start delimiter, FC...frame control, OA--destination address, SA...destination address, FC5...frame inspection Sequence, SCD...Station line synchronization display, ED...End delimiter. Fig. 2 Fig. 3 32 station Kito interface Tan β Fig. 4

Claims (1)

[Claims] In a distributed processing type private branch exchange system forming a token ring, a central office line synchronization display bit that indicates the presence or absence of a central office line in communication in each node forming the switching system is a token frame. It is provided in The communication station line display circuit that displays the communication station line, and the master clock selection circuit that selects the station line clock or network clock selected by the station line cable section during communication and outputs it to the digital phase synchronization circuit that extracts the master clock. When the local node synchronization display bit of the token frame is checked and it is determined that the local node is the node with the highest priority that has the station line in communication, the clock master determination circuit selects the station line clock using the master clock selection circuit. A distributed processing private branch exchange system characterized in that each node has one.