JPS6346853B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a numerical input device and a numerical input device using a through-entry method.

In the case of a numerical input device using the through-entry method, as shown in Fig. 1, the start key S,
A keyboard 1 including a counting up key K1 and a counting down key K2, and a display section 2 for displaying numerical values input using these keys are provided. To do this, first press the start key S to set the display to zero, then press the up key K1.
The display changes from "0" to "1", and then the numerical value increases at a predetermined period, for example, a 0.5 second period, and stops at a maximum of "9". When the displayed numerical value is in the process of increasing, if you release your finger from the up key K1, the displayed numerical value is fixed at that time. Also, when a number other than "0" is displayed, if you press the down key K2, "1" will be subtracted from this number every 0.5 seconds, and the displayed number will become smaller until it reaches "0". Stop. In this way, in the case shown in the figure, it is possible to set numerical information in 10 steps from "0" to "9", and this has already been proposed for use in, for example, an output control circuit in an electromagnetic cooker. ing.

In the case of such a control system, when the display is "0", only the up key K1 is allowed to be operated next, and input by operating the down key K2 is not accepted. That is, in the initial state, the display is "0", so even if the down key K2 is pressed at this point, the count cannot be decreased any further. Therefore, in the conventional configuration, first press the UP key K1 to input "0".
Input by operating the down key K2 is not possible until the count has been increased from 1 to an appropriate value.

On the other hand, in the case of an electromagnetic cooker, etc., heating operation is often started at the maximum output, and in such a case, if an input device with the above configuration is used, the output must first be increased from "0" to the maximum value. If the output setting is a one-digit value as in the example above, it is fine, but if it becomes a two-digit value, it will take several tens of seconds to reach the maximum output, which is an advantage of applying electrical control to this type of equipment. This has the disadvantage that the performance, ease of operation, etc. are impaired.

The present invention has been made in view of the above circumstances, and allows input using the down key when the display is "0", and at this time, the display is set to the maximum value and the count is sequentially decreased from there, thereby achieving the above-mentioned. This eliminates the shortcomings. Examples will be described below based on the figures. In Figure 1, K1 and K2 are the above-mentioned up key and down key, KD1 and KD2
are the up key K1 and down key K, respectively.
A key debounce circuit that inputs the operation signals A and A' of No. 2 and removes the chattering part, A1 and A2.
are the outputs B of the key debounce circuits KD1 and KD2,
The AND gate, CNT, which inputs B' and pulse signal C with a period of 0.5 seconds is connected to these AND gates A.
This counter inputs the respective outputs D and D' of 1 and A2 to the count up signal input terminal and the count down signal input terminal, respectively, and the contents are sent to the display unit 2 (Fig. 1) as set data and displayed. On the other hand, it is added to various control circuits. This counter
In this embodiment, a decimal counter is used as the CNT. This counter CNT is set to H when the count up clock content reaches the maximum value (“9” in this example).
It outputs a (high) level signal E, and also outputs an H level signal E' when the count down count reaches the minimum value ("0" in this example). FF1, FF
2 is a flip-flop that inputs signals D and D' to its set signal input terminals, and is reset by the inverted output of the other signals B and B'; NA1 is a flip-flop that connects the set output F of flip-flop FF1 and
The NAND gate NA2 which has two inputs is the maximum value output signal E of CNT, and the set output F' of the flip-flop FF2 and the maximum value output signal of the counter CNT.
This is a NAND gate with E' as two inputs, and the outputs of each NAND gate NA1 and NA2 are applied to the inputs of AND gates A1 and A2, respectively, to open and close them.

Next, the operation will be explained using FIG. 3. In Figure A, the contents of counter CNT are “0” and “9”.
The operation waveforms when the value is other than the above are shown, and as an example, the case where the content of the counter CNT is "2" and the up key K1 is pressed will be explained. When the up key K1 is pressed, the signal A becomes H level, and the signal B whose waveform is shaped by the key debounce circuit KD1 is obtained. Now, flip-flop FF1 is in the reset state, so the set output F is L (low).
level, and the other counter CNT maximum value output E
is also at the L level, so the NAND gate NA1 output G is at the H level. Therefore, the pulse signal C passes through and appears at the output of the AND gate A1, and a signal D is obtained. Pulse signal D
is counted by counter CNT, and its content increases. If you keep pressing the UP key K1, this counting operation will continue and the count will reach the maximum value "9".
At the point in time, the maximum value output signal E changes to H level, and the output G of NAND gate NA1 changes to L level. This signal G blocks AND gate A1, and no pulse is generated in signal D. That is, the contents of the counter CNT are fixed at "9". In addition,
If the up key K1 is released during the increment, the contents of the counter CNT at that point are fixed. The same applies to the case where the down key K2 is operated, and if this key is kept pressed, the contents of the counter CNT become "0" and are fixed. This signal system
Although the diagram is represented by a symbol with a dash, its operation is the same as the waveform shown in FIG. 3A, so a description thereof will be omitted.

Next, with reference to FIG. 3B, a case will be described in which a key is operated when the contents of the counter CNT are at the minimum value "0" or the maximum value "9". First, if the content of the counter CNT is "0" and you press the down key K2 at this time, the signal
A′ and B′ are obtained. At this time, the output E' of the counter CNT is at H level and the set output F' of flip-flop FF2 is at L level, so the NAND gate
The output of NA2 is at H level, and AND gate A2 is established to obtain signal D'. That is,
The contents of counter CNT will change from "0" to "9" after 0.5 seconds, and if you continue to press key K2,
The contents of the count are "9" → "8" → "7" →... in a cycle of 0.5 seconds, and the count is down and stops at "0". From now on, if you press the down key K2 while "0" is displayed on the display section 2, the maximum value will appear first,
It can be seen that the count is sequentially decreased after that.

Also, when the contents of counter CNT are “0”,
When the UP key K1 is pressed, the waveform signal shown in FIG. 3B appears in the signal system indicated by the symbol without a dash in FIG. 2, and the same processing is performed. In this case, the contents of the counter CNT increase and stop when it reaches the maximum value "9".

Next, when the up key K1 is pressed while the counter CNT is counting the maximum value "9", the waveform signal shown in FIG. After 0.5 seconds, the count becomes "0", and then the count increases in the same cycle as "1" → "2" →... and stops counting at the maximum value "9".

On the other hand, if you operate the down key K2 while the counter CNT is counting the maximum value "9", this is a normal operation, and the signal is processed as shown in Figure 3 (b), and the count contents are " 9”→“8”→
It decreases from "7" to... and stops at "0".

As described above, in the present invention, the contents of the counter can be quickly changed from zero to the maximum value, and
When lowering the counter contents by continuous operation of the down key, the counter contents will no longer pass through zero and reach the maximum value.
This makes it easier to set the output near zero (weak output).

[Brief explanation of the drawing]

Fig. 1 is a front view showing the keyboard and display section of an input device using the through-entry method, Fig. 2 is a circuit diagram of an embodiment of the present invention, and Fig. 3 A and B are signal waveform diagrams explaining the operation of the same example. It is. S...Start key, K1...Up key, K
2...Down key, 2...Display, KD1, KD
2...Key debounce circuit, CNT...Counter,
FF1, FF2...flipflop.

Claims (1)

[Claims] 1. In a numerical input device having a pair of counting up/down keys and a counter that inputs a predetermined pulse by operating the keys and counts up or down by the number of pulses input during the key operation period, A determining means for determining whether or not the contents of the counter are zero; a stopping means for temporarily stopping the down-count when the determining means determines that the counter contents are zero; A numerical input device characterized by comprising a setting means for setting the contents of the counter to the highest level when the counting down key is operated again at a time when the counting down key is operated again.