JPS6346695A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce a noise and to prevent the generation of a malfunction or the like by using a half precharge system in the semiconductor memory of two node constitution. CONSTITUTION:Before a signal is read from a memory cell, single MOS transistors (MOST), Q0, the inverse of Q0 are turned on, and a precharge signal P is initially held to a high level 12(V), so that data lines d0, the inverse of d0 are charged to 4(V) by MOSTQP, the inverse of QP. At the same time, by this precharge signal P, MOSTQ7, the inverse of Q7 are turned on, so that the nodes n, the inverse of n are precharged to a power source potential VDD, thereafter, a signal, the inverse of phi0 is held to the high level and the precharge signal P is lowered to 0(V). Accordingly, the precharge of the data lines d0, the inverse of d0 is completed, the precharge of the nodes n, the inverse of n is also completed when the MOSTQ7, the inverse of Q7 are turned off. Thereafter, a word line W connected to the memory cell MC is activated to read the memory cell MC.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a half-precharge type semiconductor memory with two intersections (folded data line configuration).

[Conventional technology]

The half precharge method is used in semiconductor memory.
Write to memory cells at a voltage between high voltage and low potential.
In this method, the data line is charged in advance and then the word line is driven to read information from the memory cell. , No. 3131.

Furthermore, a two-intersection memory is one in which two data lines to be read out differentially are arranged close to each other and parallel to each other, and a memory cell is placed at only one of the two intersections between a word line and the two data lines. For example, it is a memory provided with
It is disclosed in Japanese Patent No. 535.

Conventional memories include one-cross point memory (a type in which data lines are provided on the left and right sides of a sense amplifier, such as the one described in Japanese Patent Laid-Open No. 52-11
3131 publication) which adopts the full precharge method (a method in which the data line is charged in advance to a high voltage for writing to the memory cell), one which adopts the full precharge method for the two-intersection memory, and 1. Three types of memories are known that employ a half precharge method for the intersection point memory.

[Problem that the invention seeks to solve]

Since the one-cross point cell full precharge type memory is not related to the present invention, problems with the remaining two will be explained.

The configuration of the two-point memory full precharge method is shown in FIG. 1A. D (Do, D., and Dl) for the data line pair to be differentially amplified by the preamplifier PA.

Dl) are provided close to and parallel to each other. The data line pair D intersects with the word line w (wo9w1), but a memory cell M C (M Co 2M CH-) is provided at only one of the two intersections.

The memory cell MC is a single MOS transistor (hereinafter referred to as M
OST) and a capacitor connected in series with it.

Figure 1B shows data line pairs. , Do. Data line pair. r D O is charged in advance to a high potential (power supply voltage V.C) for writing into the memory cell. After that, at time to, the word line W is connected to read out the information stored in the memory cell MCo. selectively excites. It is assumed that 0'' is stored in memory cell MCo.

Data line. The potential is determined by the distribution ratio of the data line capacitance and the memory cell capacitance. When the preamplifier PA is driven at time t1, the change in potential of the data line is amplified, and the information stored in the memory cell MC is read out.

FIG. 1C shows the word line W. It shows the potential change (corresponding to noise) of the unselected word line W□ when is selected.

For two-intersection memory, data line pairs. , Do are discharged to a low potential. This is the same for other data line pairs, such as Dl, and the data line on one side is always discharged to a low potential.

When the preamplifier PA is driven at time t1, each data line pair. , Do, D□, Dl, etc. are simultaneously discharged to a low potential. Then, the potential of the unselected word line W1 decreases due to capacitive coupling with each data line. This drop in potential becomes very large because there are many data lines that have a low potential, and causes malfunction of the memory. This makes design difficult and results in a memory with a small noise margin.

Note that the potential of this unselected word line is due to parasitic resistance or
If a word latch circuit is attached.

The resistance of the word latch circuit transistor (for example, the 8th
It is discharged through the source/drain resistance of transistor T1 in the figure, and then returns to zero level. put it here,
A word latch circuit is a circuit that lowers the impedance of an unselected word line in order to suppress a change in the potential of the unselected word line. For example, WL in FIG. 8 is this circuit.

■The configuration of the intersection memory half precharge method is the 1st D.
As shown in the figure. The data line pair D to be differentially amplified by the preamplifier PA is provided on both sides of the preamplifier PA.

The word line W is connected to the left set of the preamplifier PA (word VI
cWo, W1), right set (word lines W 2 , W 3
). The left set of word lines is data line D
(D o "D)), the word lines of the right set intersect with the data lines D (Do to D3), and memory cells MC are provided at each intersection.

Figure 1E shows data line pairs. A diagram showing potential changes of IDO,
FIG. 1F shows data line pairs, Dl and D2. D2・D3.
It is a figure which shows the potential change of D3. Note that here, the word line W. The memory cell MCo connected to II OI
Information on word line W is stored. It is assumed that information of 11117 is stored in all other memories MC1 to MC3 connected to .

Data line pair. , Do-D3. D3 is precharged to a potential half of the high potential (power supply voltage V..) written into the memory cell. After that, time t. In order to read the storage information of the memory cell MCo, the word line WO is
selectively excites.

Data line. The potential is determined by the distribution ratio of data line capacitance and memory cell capacitance. Word line W.

Other memory cells MC, -MC3 connected to the memory cells MC, -MC3 are also read out at the same time, and the potentials of the data lines D1 - D3 are changed.

When the preamplifier PA is driven at time t1, the change in potential of each data line is amplified, and the information stored in the memory cell MC is read out.

Figure 1G shows word line W. It shows the potential change of an unselected word line, for example, Wl when is selected. In the above example, one of the data lines Do-D3 on the left side is the data line. Only the data line has a low potential, but the other data lines, ~D
3 all have a high potential, so the potential of the unselected word line W1 increases due to the sum of capacitive coupling with the data lines Do-D3. In an actual memory, a large number of data lines are lined up, so the potential change of unselected word lines becomes very large. This is not a fool that causes malfunction of the memory. For example, suppose that information #III is stored in the memory cell MC5 in FIG. 1D.

MO8T in the memory cell due to potential fluctuation of word line W1
turns on, and the information stored in memory cell MC5 becomes the data line.

The data will flow out and ``0'' will be written. In other words, erroneous writing occurs.

The above is the selected word line W. 11011 only for memory cell MCO among memory cells MCO~3 connected to
We have described the extreme case in which i+ 1 is stored only in the memory cell MCO.

The completely opposite situation is also conceivable, where 0'' is stored in the other and 0'' is stored in the other.

In this case, the potential fluctuation of the unselected word line W1 is the first
This will be as shown in Figure H. In other words, the data line. Since the other data lines D1 to D3 are discharged to a low level,
The potential of word line W1 decreases due to capacitive coupling. This case also causes memory malfunction.

Although the case of the two extreme storage states is shown, in the normal case, the potential of the unselected word line W1 is as shown in FIG. It is clear that the first L (changes within the diagonal lines shown in the figure).

The fact that the potential change of the unselected word 1 line differs depending on the information stored in the memory cell causes a problem that makes design difficult.

The potential of the unselected word W1 has since returned to zero potential as shown in Figures 1G and 1H, but this may be due to parasitic resistance or, if a word latch circuit is attached, the word This is due to being discharged or charged through the resistance of the transistor in the latch circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory that reduces potential fluctuations of unselected word lines, prevents malfunctions and erroneous writes in the semiconductor memory, and is easy to design.

Another object of the present invention is to provide a semiconductor memory that can reduce power consumption during preamplifier operation.

Still another object of the present invention is to provide a semiconductor memory capable of high-speed operation.

[Means for solving problems]

The above object is achieved by employing a half precharge method in a semiconductor memory having a two-intersection configuration.

Further, the above object is achieved by providing a charging/discharging means in which a through current does not substantially continue to flow during charging/discharging.

Furthermore, the above-mentioned purpose is to write to the above-mentioned semiconductor memory.

This is achieved by providing a latch circuit.

Furthermore, the above object is achieved by reducing the amplifying load of the preamplifier.

[Effect]

By adopting the half precharge method for the two-intersection sweep semiconductor memory, noise is reduced and malfunctions are less likely to occur.

〔Example〕

The present invention will be explained in detail below.

2 to 7 are diagrams for explaining the circuits used in the embodiment of FIG. 8.

In FIG. 2, data line d. A plurality of memory cells MC are connected to each tdo. data line d. +d
O are made of the same material and have the same geometric dimensions. As the memory cell MC, for example, - MO
In Figure 6, a known memory cell consisting of a series connection of 8T and a capacitor is connected to the data line d. One memory cell is shown connected to. data line d. yd.

A plurality of memory cells and the same number of memory cells are connected to each other. This memory cell has a word line W connected to it.
When selected by , the potential of the data line to which the memory cell is connected is changed by a value corresponding to the signal stored in the capacitor. For example, a value of +7.0 (V) as a high level signal or O(V) as a low level signal is stored in this capacitor. data line d. In response to the precharge signal, before reading out the memory signal of the memory cell,
W, source potential (V Do (= 10) (V)) (
7) Precharging means for precharging to about half the potential (4 (V) to be exact) is connected. This precharge level is determined by the data lines do,
do is selected so that it is located in the middle of the potentials that can be taken after charging or discharging. Specifically, MOS TQ p ,
Qp acts as this precharging means. Therefore, when a storage signal is read out from a memory cell, the potential of the data line connected to that memory cell is
The potential will be a little larger or a little smaller than that.

data line d. A dummy cell DMC is connected to +dO and coupled to a data line by a dummy word line DW.

In the figure, data line d. Only dummy cells and dummy word lines connected to are shown.

data line d. When reading a memory cell connected to +dO, the data line d. Read each dummy cell connected to +dO. The dummy cell serves to set the potential of the data line to an intermediate value between two values that the potential of the data line from which the memory cell is read corresponds to the contents of the memory cell.

The preamplifier PA includes transistors Q1. Q1 is a blip-prop consisting of a cross-coupling of input nodes d1. d1
are the data lines d from the MOS TQ o and Q o respectively. Connected to +dO. This preamplifier PA is
Data line d after reading the storage signal from the memory cell.

It detects which of the +dO potentials is higher and holds the detection result. MOSTQ3 and Q connected in series
6 connects the power supply VDD to the data line d. and data line dO
This is for charging the potential of VDD to a potential close to vDD. MOST Q a similarly connected in series.

Qa connects the power supply vDD to the data line d. and data line d
. This is for charging the potential of VDD to a potential close to vDD. Further, transistors Q4 and Q5 and Q4 and Q5 connected in series are connected to data line d, respectively. Connect +dO to ground and data line d. This is for discharging each ydo to ground potential. MOSTQ4. Q
4 gates are MOSTQ0. It is connected to the gate of Ql and is controlled in response to the detection result by this preamplifier PA. The gates of MOS TQ 3 and Qa are connected to the input node d1. of the preamplifier PA by MOS TQ 2 and Q 2, respectively. They are each connected to d1. This MOS TQ 3. Q 2 and Qa and Q2
MOST
QF1Q7 is connected. This MOSTQ
? , Q 7 are these nodes n, n and MOS TQ
3- Q This is for precharging the gate of 3 to the voltage required to turn on these MO3Ts. That is, MOS TQ? , when a high-level precharge signal P is applied to the gate of Q7,
Nodes n and n are each precharged to the power supply potential vDD.

The operation of the circuit shown in FIG. 2 will be described below using time charts showing various control signals and voltages at various points shown in FIG.

Before reading the signal from the memory cell, the signal φ.

is held at a potential of 10 (V). As a result, MOS T
Q o and Q o are in the on state. In this state, the precharge signal P is initially at a high level (12 (V)).
is maintained. As a result, the data line d. +dO is 4(v) due to the M O S T Q PQp connected to them.
is being charged. at the same time.

This precharge signal P turns on MOSTQ7°Q7, so nodes n and n are precharged to the power supply potential vDD. Thereafter, the precharge signal P is lowered to O(V) while the signal φ0 is held at a high level. This completes the precharging of the data lines do and do.

The precharging of nodes n and n also ends with MOSTQ7°Q7 turned off. Thereafter, the word line W connected to the memory cell MC is activated to read the memory cell MC. As an example, data line d.

A case will be described in which a memory cell MC connected to the memory cell MC is read out. When reading this memory cell MC, the data line d. The dummy cell DMC connected to the dummy cell DMC is also read out by the dummy word line DW. This read memory cell MC
data line d in response to a storage signal of. The potential of is changed from the original precharge potential of 4 (V) to 4.1 (V) or 3.9
Changes to (V). At this time, node d1. d changes similarly. As an example, a case where the potential of the data line do and the node d1 changes to 3.9 (V) will be described below. data line d. The potential of will hardly change.

During the above period, MO3TQ□ of preamplifier PA.

A high voltage (φ of 10 (V)) is applied to both sources of Ql, and the voltage between the source and gate of each MOS TQ 1 and Q t is
, is smaller than the threshold value Vt,h (which is approximately 1 (V)). Therefore, MOST Q t , Q i in the preamplifier PA
Both are in the off state. Then the signal φ. When changes to a low level (0 (V)), MOS TQ o,
Q and o are turned off. At this time, the magnitude of the signal read out from the memory cell is determined by the node d1. It is incorporated into d1. signal φ. When MOS TQ ! falls to a low level, the preamplifier PA starts its amplifying action and MOS TQ ! , Q t
One is on and the other is off. In the example we are currently considering, the potential of the node dl is lower than the potential of the node d1.

MOST Q1 is turned off and Ql is turned on. As a result, due to the action of the preamplifier PA, the potential of the node d1 only slightly decreases, and the potential of the node d1 rapidly becomes 0 (
v) Decline. In this way, the preamplifier PA detects and holds the t'tt signal of the memory cell. This preamplifier is connected to node d1. This means that the potential difference of d1 is amplified. This width increase is M O S T Q o
, Q o is turned off, so it is performed at extremely high speed.

Furthermore, when increasing the width using the preamplifier PA, the MOST
Q o = ' Keeping Q o in the off state has the following advantages. That is, the memory using the present invention is provided with many pairs of data lines in addition to the one pair of data lines shown in FIG. 3, and these data lines are also charged and discharged at the same time as described below. be exposed. As a result, through the coupling capacitance between these data lines and a word line provided in common to and crossing these data lines.

The word line potential changes, and this change again causes a voltage change on each data line via this coupling capacitance. This change in voltage on the data line acts as noise and causes the preamplifier PA to
Although it may have a negative effect on the O widening effect, MOS TQ o
, Q o are in the off state, such a problem does not occur.

The detection result of this preamplifier PA is MOSTQ2
.

It is transmitted to the control electrodes Q4-Q2-Q4. That is,
When node d1 is at high level and node d1 is at low level, MOS TQ z -Q 2 is in on and off state respectively, and 1M05TQ4. Q4 is in the on and off states, respectively. As a result, node n is M OS
T Q 2 , Q t lowers Be/L/ (0(V
) ) &: Discharges and MOST Q3 turns off. On the other hand, node n is not discharged and is held at a high level. In this state, signal φ1 is at low level (0 (V))
When changed from to high level (10 (V)), MO8T
Qs, Qey Qs and Qe are turned on. MO8TQ4
is off, the data line d0 is not connected to ground, so the data line do is not discharged, but the MOS
Since TQ 4 and Q s are on, data 11Ad
o is connected to ground, data line do is connected to this MOS T
Discharge through Q a and Q s. On the other hand, MOSTQ
3. Since Qa is on, data line d. is connected to the power supply vDD and charged to a potential close to vDD (approximately 8 (V)').

Note that a signal φ1 is input to the gates of MOST Qs and Qa via a bootstrap capacitor 〇g. This bootstrap capacitor consists of a capacitor using an inversion layer. A capacitor using this inversion layer is known, for example, from the following document.

R.E., Johnson et al.
“E 1iIllinat,ingThreshold
Losses in MOS circuits b
yB ootsttrapping U sing
Varactor Coupling”I E
E E J , of 5 solid
-5tat, e C1rcuitsSC-7, No.
3. p, 217 (1972, 6).

The electrode of this capacitor connected to MO3TQ3 or Qa is connected to the gate electrode on the inversion layer, and the MOS TQ
s = Q s The Ic-connected Wi pole is connected to a diffusion layer provided in connection with this inversion layer. As a result, the bootstrap capacitor CB connected to node n, which is held at a high level, has a relatively large capacitance. Due to the action of this capacitor, the node n is raised from the original precharge level of 10 (V) to a higher level of 12 (V) when the signal φ1 becomes high level.

As a result, the potential of the source of MOST Q3 becomes approximately equal to the power supply voltage VDD (10 (V)) Ic,
data line d. , it is charged to a potential (approximately 8 (V)) lower than the power supply voltage vDD by the voltage drop caused by MO8TQ6. In this way, the bootstrap capacitor CF
3 makes the voltage drop due to MO3TQ3 almost zero when charging the data line, thereby helping to increase the charging potential of the data line.

On the other hand, the bootstrap capacitor C8 connected to the gate of MOST Q3 has its node n at a low potential (
0(V)'), the capacitance of this capacitor is almost equal to zero. Therefore,
The potential of the node n hardly increases even if the signal φ□ is applied.

As described above, the potential of data ado-do is discharged or charged to different levels depending on the read storage signal of the memory cell. Using the potential of the data line after charging or discharging, a signal is rewritten into the original memory cell, and the data line d. The +dO potential can be sent to the outside and used as an amplification signal for the storage signal of the memory cell. In particular, in the present invention, data id.

The data line d is approximately halfway between the potentials after being charged and discharged. +dO is precharged in advance. This data line d. MO3TQ3-Q for charging
The conductance of g and the conductance of MOS TQ 4=Q s for discharging data ado are selected so that charging and discharging of each data line is performed while giving the same potential change over time. Furthermore, the data line d. The conductance of MOS TQ 4-Q s for discharging and the data line d. MO for charging
The conductances of 8TQ3°Q6 are selected so that the respective data lines are discharged and charged while giving the same potential change over time.

As described above, read the signal from the memory cell.

After rewriting this into the memory cell, all control signals are returned to their original precharge levels. In this manner, the memory cell read cycle is completed.

Figure 4 shows data line d. This memory, which shows another example of a circuit in which the charging and discharging speeds of tdO are equal, is MO8TQ4. of the memory shown in FIG. Q5. Q4゜does not have Q5, and MOS TQ o and Q o are shown in FIG. Control signal φ used for memory. A signal φ0' different from that is used. This signal φ0' is the previous signal φ. at the same timing as the high level (10 (V)) to the low level (0 (V)
) changes to ). φ. ' is the signal φ. Unlike, the signal φ
, changes from a low level to a high level, and at the same time changes from this low level to the original high level. A time chart of various signals and voltages at various points related to the memory shown in FIG. 4 is shown in FIG. In the memory of this circuit example, the data line d. TDO charging is performed in exactly the same way as for the memory of FIG. In the memory of this circuit example, the data line d. y
The discharge of do is M OST Q o , Q
x and Q. , Ql is different from the memory shown in FIG.

Data line d from memory cell. The operation is exactly the same as that of the memory shown in FIG. 2, from when a stored signal is read out to the top, this signal is amplified by the preamplifier PA, and node n or n is discharged according to the amplification result. be. After this discharge is performed, when changing the signal φ1 to high level, M O
S T Q o =Qo is turned on by signal φ1. - data line d as an example. A case in which a low level signal is read from a memory cell connected to the memory cell will be described below. In this case, after the signal is amplified by the preamplifier PA, MOS TQ1-Qx are in the on and off states, respectively. Therefore, even if MO3TQo is on, the data line d. does not discharge through MO3TQ1. On the other hand, since MO8TQ1 is on, the data line d0 is M O S T Q o .

Q, through the signal source φ. discharge to.

Therefore, the charging of the data line do by MO5TQ3-Qa and the discharging of the data line do by MOS TQ o and Q t are performed in the first order so that the temporal change in voltage is equal.
．． The conductance of these MO3Ts is selected in consideration of the resistance of the second data line and the coupling capacitance between these lines and the substrate. Furthermore, MOS TQ 3. Data line d by Q e. and the discharge of MOS TQ o , Q
Data line d by 1. The conductances of these MOS:r are chosen so that the discharge and the temporal change in voltage are equal.

As can be seen from the above, this embodiment uses MOST Q 4 , Q s , Q 4 rather than the memory shown in FIG.
, Q s is not required.

Figure 6 shows data line d. An example of another circuit in which the charging and discharging rates of +dO are equal will be shown. This circuit differs from the circuit shown in FIG. 4 in the discharge circuit for nodes n and n.

Nodes n and n are respectively MO3TQ2. It is discharged through Q2 to the signal φ,'. FIG. 7 shows a time chart of control signals and voltages at various points related to this embodiment.
Data fid in figure. +dO, node d1. The voltages of d1 and nodes n and n indicate that a low level signal is read out by the memory cell connected to the data line do.The signal φ1' becomes a high level (10 (V)) to a low level (0(V)'). As a result, only node n is discharged and has a low level voltage. Then φ1. By changing φ0 from low level to high level.

data line d. is discharged to ground potential through MOS TQ o, Q 1 and the data line d. is MO8TQ3゜Q
It is charged to about 8 (V) by the power supply ■DD through s.

Note that, as in the above circuit example, MO8TQ3°Q8 and Q3. A charging circuit consisting of Qll and a power supply vDD is connected to the data line d. , instead of connecting to node d1
．． It is also possible to connect to d1. Similarly in the circuit of FIG. MOSTQ4. A discharge circuit consisting of Q5 and Q4-Qs and a ground source is connected to the data line d. Instead of connecting to +dO, it is also possible to connect to nodes d, d1. In these cases, the signal φ of FIG. When used in the circuits of FIGS. 5 and 7 instead of φ. ′ must be used.

Data line d obtained by the example shown above. .

The present invention is characterized in that a circuit with equal charging and discharging speeds of do is used in a memory having two parallel data line pairs.

FIG. 8 shows an embodiment of the present invention.

FIG. 8 shows a half precharge method used in a two-intersection memory.

In the figure, Cdw is the word line W1 and data line. .

This is the coupling capacity with Do.

FIG. 9A shows a pair of data lines DO and D arranged parallel to each other. FIG.

Data line pair. Andri. is pre-charged to 4V.

At time to, word line W. selectively excites.

Word line W. 11 to the memory cell MCO connected to
Assuming that 011 is stored, the data line. The potential is determined by the distribution ratio of the data line capacitance and the memory cell capacitance. This potential is.

Data line. With the potential of each switch SW.

The signal is taken into the preamplifier PA via SW.

After that, the switches sw and sw are opened, and the preamplifier PA performs an amplification operation. The width amplification result is given to the charging/discharging circuit I. At time t1, the signal φ1 activates the charging/discharging circuit I, and the signal φ1 is applied to the data line. is discharged to a low potential, becoming the data line. is charged and changes to a high potential.

FIG. 9B shows the word line W. FIG. 4 is a diagram showing a potential change of an unselected word line W1 when the word line W1 is selected.

Data line. Assuming that there is no capacitive coupling caused by , the potential of the unselected word line W1 changes as shown by the curve A in the figure. Also, data line. Assuming that there is no capacitive coupling, the curve changes as shown in the middle of Figure 5. Data line. Andri. Since it is determined by the capacitive coupling of , there is almost no change as shown in the figure.

In Figure 8, the data line. Andri. However, since the potential of one of the other data line pairs always increases and the potential of the other decreases, changes in the potential of unselected word lines due to capacitive coupling of other data line pairs also affect the data. Line pair. As with r DO, the result is shown in FIG. 9B.

Therefore, it is clear that according to this embodiment, potential fluctuations of unselected word lines can be suppressed.

In the past, a word latch circuit WL was provided for the purpose of keeping unselected word lines at low impedance and suppressing the voltage coupled to unselected word lines. but,
In this embodiment, since the coupling voltage to the unselected word line is extremely small, the word latch circuit WL is not required or requires a smaller area, and the chip area can be reduced.

Further, in FIG. 8, the memory cell is connected to only one of the two intersections, but the same applies to the case where the memory cell is connected to each of the two intersections.

Furthermore, the memory cell includes the single MO5T and the MOS
It is not limited to a capacitor connected in series with T. In short, it is sufficient that the two data lines are arranged in parallel and close to each other, and that the data line pair is charged to a potential between the high potential and the low potential of the write voltage. No question.

〔Effect of the invention〕

According to the present invention, since a half precharge method is adopted in a memory having two data line pairs arranged in parallel, the combined voltage of an unselected word line due to an increase in the potential of one of the data line pairs and the potential of the other data line pair are The potential change of the unselected word line due to the drop is determined, and it is possible to realize a memory in which the potential change of the unselected word line is small.

[Brief explanation of drawings]

1A to 1H are diagrams illustrating the conventional memory configuration and operation, FIG. 2, and FIG. 4, respectively. FIG. 6 is a diagram showing an example of a circuit used in the present invention, and FIG. 5 and 7 are time charts for explaining the operation of the circuits in FIGS. 2, 4, and 6, respectively, FIG. 8 is a diagram showing a circuit according to an embodiment of the present invention, and FIG. Figure 9B is the 8th
3 is a time chart for explaining the operation of the circuit shown in the figure. PA: preamplifier, do, dos data line, Qo=Qo
: MOS for connection, Qa, Qe, Q3- Qe : MOS for charging, Q4.
Qa, Q4. Qa: MOS for discharge. Dream ID diagram; Broom IH eye: 01--m: Deshini; v, 3'Il! I guess, f again

Claims (1)

[Claims] 1. A pair of data lines arranged in parallel to each other that exchange information with a memory cell, a plurality of word lines arranged to intersect the pair of data lines, and a data line. and a plurality of memory cells connected to the word line, and after a memory cell is selected by the word line, one of the data line pairs is charged to a predetermined high potential based on the information stored in the memory cell, and the other is charged to a predetermined low potential. charging/discharging means for discharging to a potential, the pair of data lines being charged to a first potential between the high potential and the low potential before the word line is selectively excited. In the semiconductor memory, the charging/discharging means has a charging circuit and a discharging circuit, and the charging/discharging means is configured to prevent a through-current from substantially continuing to flow between the two circuits during the operation period of the charging/discharging means. A semiconductor memory characterized by comprising: 2. A pair of data lines arranged parallel to each other that exchange information with the memory cell, a plurality of word lines arranged to intersect the pair of data lines, and a connection between the data line and the word line. After a memory cell is selected by a word line, one of the data line pairs is charged to a predetermined high potential and the other is discharged to a predetermined low potential based on the information stored in the memory cell. means, wherein the pair of data lines are charged to a first potential between the high potential and the low potential before the word line is selectively excited. A semiconductor memory characterized in that the word line is provided with a word latch circuit, and the word latch circuit holds unselected word lines at low impedance. 3. A pair of data lines arranged parallel to each other that exchange information with the memory cell, a plurality of word lines arranged to intersect the pair of data lines, and a switch on the first data line. a second data line electrically connected to each other via means; a plurality of memory cells connected to the first data line and the word line; and after the memory cell is selected by the word line, the memory cell and a preamplifier that charges one of the second data line pair to a predetermined high potential and discharges the other to a predetermined low potential based on stored information, and the word line is selectively connected to the pair of data lines. In the semiconductor memory which is charged to a first potential between the high potential and the low potential before being excited by the semiconductor memory, the switching means transfers the information on the first data line to the second data line.
When the preamplifier amplifies information on the second data line after being electrically connected to the data line, the first data line and the second data line are electrically separated. A semiconductor memory characterized by