JPS6345919A - Error correction method - Google Patents

Abstract

PURPOSE:To reduce the probability of error correction and to improve the correction capability to a burst error by forming a 3rd arranging state comprising plural information words and 1st and 2nd plural check words, recording the signal in the unit of sector and repeating the operation of decoding again to the decoding result in the unit of sector at recovery. CONSTITUTION:A read data is received from a data input/output terminal 62 and stored in a RAM 70. Then C1 decoding is applied. Further, C2 decoding is applied similarly as the C1 decoding. When the C2 decoding is finished, the content of the data of the address of a RAM 71 is checked by an operation circuit 69. The program is branched into a prescribed address according to the result. When the result shows count =n, a signal representing the correction disable is outputted to complete the decoding. With count =n, a decoding number counter 78 receives a number of time signal 83 and the C1 decoding is executed again. Thus, even for a long burst error being disabled of correction by one decoding, the decoding is applied repetitively to the result of decoding, the result is corrected sequentially.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error correction method for encoding and recording information on a recording medium and for decoding the encoded and recorded information.

[Conventional technology]

As such an error correction method, for example, one using a double-encoded error correction code using a Reed-Solomon code has already been put into practical use. A conventional example of double encoding using this Reed-Solomon code will be explained with reference to FIG.

In FIG. 4, 11 is an information word group, 12 is a first check word group, and 13 is a second check word group.

The encoding starts with m information words DI in the vertical direction in the figure.
I+ DZI+ '-'-'+ First test word pHl for DIll+ P21. Generate and add P311 P41. These m information words and the 4 first
A data string consisting of check words of is assumed to be a C2 code sequence.

Similar operations are performed up to column n to complete C2 encoding.

Next, n information words D1.
.

D2□l'-"-'l Second check word Q for onn. 11,1, On+2+2, Qn+3.3, Qn
+i 4 is generated and added. This data string consisting of n information words and four second check words is defined as a C1 code sequence. A similar operation is performed (m+4) times for each diagonal in the lower right direction to complete C1 encoding. However, when exceeding the (m+4)th line in this C1 encoding,
The process returns to the first line and continues. Each word in this C1 code series is a word included in a different C2 code series, and thus an interleave operation is performed between C1 encoding and C2 encoding. The above constitutes one unit of data (hereinafter referred to as a sector) to be recorded on the recording medium. Here, the fourth
Each row in the diagram is called a block. Therefore, in FIG. 4, one sector is composed of axis+4) blocks.

Recording is performed sequentially from l block to (m+4) block. Each word in this one block is
are words included in different C1 code sequences,
and are words included in different C2 code sequences. Therefore, a second interleaving operation is performed between C1 encoding and recording. This situation can be seen in Chapter 5.
As shown in the figure. In FIG. 5, 21 is the C1 encoding direction, 2
2 indicates the C2 encoding direction, and 23 indicates the recording direction.

In decoding, first, de-interleaving corresponding to the second interleaving is performed, error detection and error correction are performed with the C1 code sequence, then de-interleaving corresponding to the first interleaving is performed, and then de-interleaving is performed with the C2 code sequence. Correct errors. Here, since Reed-Solomon codes with a minimum distance of 5 are used for both the C1 code series and the C2 code series, up to two errors whose error positions are unknown (hereinafter referred to as errors) can be corrected independently. In other words, in the decoding of a 3-series CI code system (hereinafter referred to as C1 decoding), if there are up to two errors, error correction is performed, and if there are three or more errors, the (n+4) words included in the C1 code system are corrected. A flag is added. In addition, in decoding a C2 code sequence (hereinafter referred to as C2 decoding), error correction is performed if there are up to two errors, and the C2
If there are three or more errors in (m+4) words in the code sequence and the number of flags added in C1 decoding is four or less, erasure correction is performed.

[Problem that the invention seeks to solve]

According to the above-mentioned error correction method, since an interleave operation is performed between C1 encoding and recording, the probability of erroneous correction for burst errors is lowered compared to the case where the CI encoding direction and the recording direction are made to match. It has the advantage of being possible.

However, if there are three blocks in a sector in which the entire block is erroneous due to loss of synchronization or the like, there is a problem that correction is no longer possible. Figure 6 shows the case where consecutive 3rd and 7th hits are burst errors;
1 indicates the direction of the burst error, 32 indicates the error that could be corrected by C1 decoding, 33 indicates the flag added by C1 decoding, 34 indicates the error that could be corrected by C2 decoding, and 35 indicates the error that could be corrected by C2 decoding even with C1 decoding.
Each error that could not be corrected by decoding is shown.

In such a case, since the number of flags added in C1 decoding is five or more, erasure correction cannot be performed in C2 decoding, and most of these burst errors become uncorrectable.

This invention was made by focusing on these conventional problems, and is an error correction method that can reduce the probability of incorrect correction, improve the correction ability for burst errors, and perform error correction efficiently and in a short time. The purpose is to provide a method.

[Means and operations for solving the problem] In order to achieve the above object, the present invention uses a plurality of information words in a first arrangement state and a first check word generated for these information words to a plurality of information words and a plurality of first test words in a second arrangement state consisting of a plurality of information words and a plurality of first check words included in each different first code sequence; A second code sequence is formed by the word and a second check node generated for the plurality of information notes and the plurality of first check words, and further, the second code sequence is forming a third arrangement state consisting of a plurality of information words, a plurality of first check words and a plurality of second check words included in the second code sequence and each different from the second code sequence;
If the decoding result for each sector contains an uncorrectable word, the decoding result will be recorded in the middle of the sector.
The operation of decoding is repeated up to the maximum number of first code sequences included in l sectors.

〔Example〕

A case will be described in which an embodiment of the present invention is applied to the error correction code shown in No. 4M.

As mentioned above, the error correction code shown in FIG. 4 has the ability to correct up to two errors and correct up to four erasures in both C1 decoding and C2 decoding. shall not be carried out.

FIG. 1 shows a flowchart of decoding in this embodiment. Hereinafter, the sequential steps of de-cooling will be explained with reference to Fig. 1.
This decoding is performed on data stored in a storage location called a sector buffer. Although the two-time interleaving is not particularly explained, C1 decoding and C2 decoding each
It is assumed that this is performed when extracting a C1 code sequence and a C2 code sequence.

(1) Store data read from the recording medium in a sector buffer.

(2) Set the counter to 1 cent. This counter counts the number of times decoding is repeated.

(31C1 decoding is performed. In this C1 decoding, (
m+4) C1 decoded sequences are sequentially extracted from the sector buffer, and if it is determined that there are one or two errors, error correction is performed and the result is returned to the sector buffer. Otherwise, Sakta returns to the sofa without doing anything.

(4) Perform C2 decoding. In the C2 decoding of
Sequentially extract n C2 code sequences from the sector buffer,
If it is determined that there are one or two errors, error correction is performed and the result is returned to the sector buffer.

If there is no error, the data is returned to the sector buffer as is. Further, if it is determined that there are three or more errors, the data is returned to the Sakutaha Sofa and the uncorrectable flag is set to 1.

(5) If the uncorrectable flag is 0, it is determined that the sector has been decoded and the process ends. Also, the uncorrectable flag is set to 1.
If it is determined that there is an uncorrectable error, proceed as follows (6).
Proceed to.

(6) Check whether the counter value is equal to the number n of C2 code sequences. If they are equal, the sector is determined to be uncorrectable and the process ends; if not, proceed to the next step (7).

(7) Increase the counter value by 1, set the uncorrectable flag to 0, and return to (3).

FIGS. 2A, B, and C show the decoding process according to the flowchart of FIG. 1 when four consecutive blocks are burst errors. In FIGS. 2A to C, 51 is the first decoding result, 52 is the second decoding result, and 53 is n
This is the result of the second decryption. Further, 54 is an information word group or a first test word group, 55 is a second test word group, 5
6 indicates an error that could be corrected by C1 decoding, 57 indicates an error that could be corrected by C2 decoding, 58 indicates an uncorrectable error, and 59 indicates a word that could be corrected up to the previous decoding.

As is clear from Figure 2A-C, in the first decoding, 8
Only word errors can be corrected, but in the second and subsequent decodings, 4 words can be corrected per decoding, and by the end of the n-th decoding, all errors in the information word group or the first check word group 54 have been corrected. has been corrected. By repeating decoding in this manner, it is possible to effectively correct burst errors as long as four blocks, which could not be decoded in the past. Furthermore, the upper limit of the number of repetitions is also sufficient to be the number n of C2 code sequences.

FIG. 3 is a block diagram showing the configuration of an example of an error correction circuit that performs the above-described decoding. In FIG. 3, 61 is a control signal input terminal, 62 is a data input/output terminal, and 63 is a control signal input terminal.
is a clock input terminal, 64 is a buffer, 65 is a syndrome generation circuit, 66 and 67 are wires, 68 is a multiplexer, 69 is an arithmetic circuit, 70 and 71 are RAMs,
72 is an address generation circuit, 73 is an adder circuit, 74 is a program ROM, 75 is a program counter, 76 is an internal data bus, and 77 is an external data bus.

78 indicates a decoding number counter.

The control signal input terminal 61 is connected to a multiplexer 68, the data input/output terminal 62 is connected to an external data bus 77 via a buffer 64, and the clock input terminal 63 is connected to a program counter 75.

A program ROM 74 stores a program for controlling each circuit and executing decoding, stores a branch address 79 for branching the program in a program counter 75, and stores a condition selection for selecting conditions for branching the program. signal 80 to multiplexer 68, data output signal 81 to internal data bus 76, RAM 7
Address generation signal 8 for generating address signal 1
2 to the adder circuit 73 and a number signal 83 for counting the number of decoding repetitions to the decoding number counter 78. Latches 66 and 67
, arithmetic circuit 69. A control signal 84 for controlling the address generation circuit 72 and the like is output.

Syndrome generation circuit 65. The latches 66 and 67 are connected between the internal data bus 76 and the external data bus 77, and the launches 66 and 67 control the movement of data between the internal data bus 76 and the external data bus 77. A syndrome is generated from the data on the external data bus and output onto the internal data bus 76.

Arithmetic circuit 69 is connected to internal data bus 76 . This arithmetic circuit 69 has various arithmetic functions necessary for decoding, that is, a function to perform addition and subtraction, a function to obtain i from element d′ on GF(2′), a function to obtain d” from i, and In addition to outputting the calculation result to the internal data bus 76, various flags (zero detection, overflow, etc.) 85 according to the calculation result are output.
is generated and output to the multiplexer 68.

The multiplexer 68 converts the control signal from the control signal input terminal 61, various flags 85 from the arithmetic circuit 69, and one of the outputs of the decoding counter 78 into a program l? The selection is made in response to the condition selection signal 80 from the OM 74 and output to the program counter 75.

The program counter 75 controls the address of the program, and normally advances the address of the program ROM 74 in response to a clock signal from the clock input terminal 63 to execute the program.

Further, the program is branched by loading the branch address 79 into the program counter 75 in response to a signal from the multiplexer 67.

Adder circuit 73 adds address generation signal 82 from program ROM 74 and data on internal data bus 76 to generate an address signal for RAM 71.

The RAM 70 corresponds to the aforementioned sector buffer, is connected to the internal data bus 76, and stores l sectors worth of decoded data. The decoded data stored in this RAM 70 is read out in accordance with address signals corresponding to the C1 code series, C2 code series, etc. generated from the address generation circuit 72 in response to control signals from the program ROM 74, and is read out on the internal data bus 76. is output to. RAM 7
1 is connected to the internal data bus 76 and temporarily stores the calculation results in the calculation circuit 69 and the data for one code sequence from the RAM 70. In this RAM 71, when data indicating an error position is output on the internal data bus 76 as a calculation result, that data and the program ROM 7
Correcting the data corresponding to the above-mentioned error position in the RAM 71 is executed in accordance with the address signal from the adder circuit 73 based on the address generation signal 82 from the address generating signal 82 from the RAM 70. Transfer to.

The composite number counter 84 counts the decoding repetition number signal 83 from the program ROM 74, compares the count value, that is, the number of repetitions, with a preset number n of C2 code sequences, and outputs the result to the multiplexer 68. do.

In the decoding operation, first, read data is received from the data input/output terminal 62 and stored in the RAM 70. Next, C1 decoding is performed. In this C1 decoding, the address generation circuit 72 sequentially generates address signals in the RAM 70 corresponding to the CI code series to read out the data of the C1 code series, and the syndrome generation circuit 65 generates a syndrome while at the same time reading out the data of the CI code series. ll
The data is transferred to the RAM 71, and if there is an error due to syndrome, the error is corrected and the data is transferred to the RAM 70 again. Next, C
2. Perform decoding. This C2 decoding is also performed in the same manner as the C1 decoding, or if it is uncorrectable, data indicating that it is uncorrectable is stored at a predetermined address in the RAM 71. When the C2 decoding is completed, the arithmetic circuit 69 performs a 911 check on the contents of the data at the address where the data indicating uncorrectability is written in the RAM 71, outputs the result to the multiplexer 68, and executes the program accordingly. Branch to a predetermined address. If the result is uncorrectable, decoding ends.

If the correction is not possible, the program selects the output from the decoding counter 78 as the output of the multiplexer 68;
Depending on the result, the program is branched to a predetermined address. If the result is count -n, a signal indicating correction 11-impossibility is output and the decoding is terminated.

If the count is f-n, the decoding number counter 78 shows the number of times 1.
．． 1 83 is output and -C is executed again from C1 decoding.

Although erasure correction is not performed in the above embodiment, it is of course possible to perform erasure correction.

〔Effect of the invention〕

As mentioned above, according to the present invention, since double interleaving is performed, the probability of error correction can be lowered, and even if a long burst error that cannot be corrected by one decoding, the decoding result is Since the decoding is performed repeatedly, corrections can be made sequentially. Therefore, the ability to correct burst errors can be improved, and since the upper limit of the number of repetitions is set to the number of first code sequences, decoding can be performed efficiently in a short time.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing the sequential steps of decoding according to an embodiment of the present invention; FIGS. 2A, B, and C are diagrams showing an example of the decoding process according to the flowchart of FIG. 1; The figure shows a block H1 showing the configuration of an example of an error correction circuit that performs the decoding shown in FIG. 1. FIGS. 4, 5, and 6 are diagrams for explaining the conventional technology. 11... Information word group 12... First check word group 13... Second check word group 21... C1 encoding direction 22... C2 encoding direction 23... Recording direction 61 ...Control signal input terminal 62...Data input/output terminal 63...Clock input terminal 64...Buffer 65...Syndrome generation circuit 66, 67...Latch 68...Multiplexer 69... Arithmetic circuit 70.71...R
A? 172...Address generation circuit 73...Addition circuit 74...Program ROM 15...Pl'
1 gram counter 76...internal data bus 77.
・・External data no.＼fu) (・・・decode same number counter

Claims (1)

[Claims] 1. A first code sequence is formed by a plurality of information words in a first arrangement state and a first check word generated for these information words, and A plurality of information words and a plurality of first check words in a second arrangement state consisting of a plurality of information words and a plurality of first check words included in a code sequence; A second code sequence is formed by a second check word generated for the check word, and a plurality of code sequences included in the first code sequence, which are different from each other, and included in the second code sequence, which are different from each other. A third arrangement state consisting of an information word, a plurality of first check words, and a plurality of second check words is formed, and this third arrangement state is recorded in units of sectors, and during reproduction, in units of sectors. An error correction method characterized by repeating an operation of decoding the decoding result again if an uncorrectable word is included in the decoding result up to the maximum number of the first code sequences included in one sector. .