JPS6345686A - Reducing device for pseudo half tone image - Google Patents

Abstract

PURPOSE:To reduce an image without deteriorating gradation width expressed by an original image and the finess of the gradation by evenly selecting the thresholds by dithers and thinning picture elements. CONSTITUTION:An in-matrix main scan position counter 7, a main scan matrix counter 8, an in-matrix subscan position counter 9 and a subscan matrix counter 10 specify picture elements. Judging from the readings of the counters, a thinning decision circuit 11 decides which picture elements that said counters specify are thinned or not. The thinning decision circuit 11 evenly selects the thresholds of dithers corresponding to picture elements comprising the original image, and is constituted of memories that decide selected picture elements so that distances between said elements can be roughly constant. Thus a dither image can be reduced with the gradation width and the finess of the gradation unchanged.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a pseudo-halftone image reduction method that reduces a digital image displayed in pseudo-halftones using a dither method without impairing the expressed gradation and resolution. Regarding equipment.

(Prior Art) FIG. 3 shows the configuration of a conventional pseudo halftone image reduction device of this type. In FIG. 3, 1 is a reduction rate setting circuit, 2 is a main scanning position counter, 3 is a sub-scanning position counter,
4 is a thinning circuit. The main scanning position counter 2 and the sub-scanning position counter 3 each operate as an M-ary counter when the reduction rate set by the reduction rate setting circuit 1 is 1/M, and each operates as an M-ary counter for each M pixel in the main scanning direction and the sub-scanning direction. The thinning circuit 4 outputs the input pixel at that time together with the dot clock only when the outputs of the main scanning position counter 2 and the sub-scanning position counter 3 both become 1''. In this way, the conventional pseudo-halftone image reduction device described above can also reduce an image.

On the other hand, there is a dither method as a method of representing apparent halftones using binary levels of black and white. The dithering method involves comparing a multivalued halftone image with a matrix that has several different predetermined thresholds and then converting it into a binary image.
This is a method of pseudo-expressing halftones using only binary values by using the density of black and white points.

(Problems to be Solved by the Invention) However, when expressing halftones using the conventional dither method described above, Bayer's dither matrix (4×4), which is considered to be relatively good based on the results of visual experiments as shown in FIG. 4, is used.
However, since such a conventional W-like halftone image reduction apparatus performs image reduction by systematic dithering, only pixels with close threshold values are selected based on the regularity of the threshold value arrangement of the dither matrix. Therefore, in the reduced image, there is a problem that the range of gradations that can be expressed becomes narrow and the fineness of the gradation is lost.

In addition, the conventional reduction apparatus using the dither method is not economical because processing time and cost increase to improve gradation, and resolution problems also occur depending on the degree of reduction.

The present invention solves such conventional problems, and aims to provide a pseudo halftone image a reduction device that does not impair the gradation width and gradation fineness even when reduction processing is performed. This is the purpose.

Furthermore, depending on the purpose of the target image, if the gradation or resolution is not necessarily a problem, the gradation or reduction ratio can be appropriately selected, and the pseudo It is an object of the present invention to provide a halftone image reduction device.

(Means for Solving the Problems) In order to achieve the above object, the pseudo halftone image reduction device of the present invention includes a dither matrix size setting means, a dither matrix size setting means, and a means for instructing the position of the dither matrix to be processed by the size setting means; means for setting a reduction ratio; and means for reducing the pixel being processed in the dither matrix by the means for setting the reduction ratio;
A thinning determining means for determining whether or not to select a pixel indicated by the respective values of the position indicating means and the one pixel reducing means; and means for thinning out predetermined pixels from the pixel.

(Function) Therefore, according to the present invention, by thinning out the original image by uniformly selecting the threshold values when dithering the original image while indicating the position on the dither matrix for each pixel of the original image. This has the effect that a dithered image can be reduced without changing the gradation width and gradation fineness.

Another advantage of the present invention is that the gradation or reduction ratio can be appropriately selected depending on the purpose of the target image.

Furthermore, the present invention has the advantage that the gradation or reduction ratio can be appropriately selected in consideration of the purpose of the target image, resulting in a short processing time and an inexpensive apparatus.

(Example) FIG. 1 shows the configuration of an embodiment of the present invention.

In FIG. 1, 5 is a dither matrix size setting circuit, and 6 is a reduction rate setting circuit. The intra-matrix main scanning position counter 7 and the main scanning matrix counter 8 are connected in series and indicate the position of the pixel in the main scanning direction. Further, the intra-matrix sub-scanning position counter 9 and the sub-scanning matrix counter 10 are connected in series and indicate the position of the pixel in the sub-scanning direction. 11 is a thinning determination circuit, and 12 is a thinning circuit that reduces the original image based on the output of the thinning determination circuit 11.

Next, the operation of the above embodiment will be explained.

The size of the dither matrix when dithering is NXN
In this case, the dither matrix size setting circuit 5 sets the intra-matrix main scanning position counter 7 and the intra-matrix sub-scanning position counter 9 so that they both operate as N-ary counters.

Therefore, the positions of the dither matrix are sequentially designated by the dot clock and the line clock.

Further, when the reduction rate is 1/M, the reduction rate setting circuit 6 sets the main scanning matrix counter 8 and the sub-scanning matrix counter 10 so that both operate as M-ary counters. Therefore, the positions of pixels to be thinned out from within the dither matrix are sequentially designated.

Note that in the initial state, each counter is
Cleared to OIt.

The original image is sequentially supplied to the thinning circuit 12 one pixel at a time, and at the same time, an in-matrix main scanning position counter 7 indicating the position in the main scanning direction within the dither matrix is counted up using a dot clock.

Further, as the in-matrix main scanning position counter 7 carries up, a main scanning matrix counter 8 indicating the number of the matrix in the main scanning direction is incremented.

Every time one line is completed, the line clock clears the in-matrix main scanning position counter 7 and the main scanning matrix counter 8 to it OIt, and clears the in-matrix sub-scanning position counter 9 indicating the position in the sub-scanning direction in the dither matrix. Count up. Further, as the in-matrix sub-scanning position counter 9 carries up, a sub-scanning matrix counter 10 indicating the number of the matrix in the sub-scanning direction is incremented.

The thinning determination circuit 11 includes an in-matrix main scanning position counter 7, a main scanning matrix counter 8. Matrix sub-scanning position counter9. From each value of the sub-scanning matrix counter 10, it is determined whether the pixel pointed to by these is to be selected for thinning processing. The thinning determination circuit 11 includes a memory that uniformly selects dither threshold values corresponding to pixels of the original image and determines selected pixels so that the distance between the selected pixels is approximately constant. FIG. 2 shows an example of a case in which a dither having a matrix size of 4×4 is reduced to 1/2.

The thinning circuit 12 selects necessary pixels according to the judgment result of the thinning judgment circuit 11, and outputs a dot clock of the reduced image.

As described above, according to the above embodiment, (dither matrix size) 2/(reduction ratio) 2 = (MXN) of the original image
The dithered image can be reduced without changing the two-tone width and the fineness of the gradation by thinning out the area surrounded by the square `` so that the threshold values for dithering are evenly selected.

(Effects of the Invention) As is clear from the above embodiments, the present invention thins out pixels by uniformly selecting dither thresholds for an image expressed in pseudo-halftone by the dither method, and thins out the pixels expressed in the original image. This method has the advantage that images can be reduced without losing the gradation width and gradation fineness.

Furthermore, the present invention allows the gradation or reduction ratio to be selected as appropriate depending on the purpose of the target image using the respective setting means, and can be realized with a simple device and can be processed in real time. It has the advantage of

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram illustrating a case where a dithered image with a dither matrix size of 4×4 is reduced to 172, and FIG. 3 is a diagram illustrating a conventional method of this type. Block diagram of the pseudo halftone image reduction device of
The figure shows a threshold array of a 3ayer dither matrix (4×4).
... Main scanning position counter, 3... Sub-scanning position counter, 4... Thinning circuit, 5... Dither matrix size setting circuit, 6... Reduction rate setting circuit, 7
... Main scanning position counter in matrix, 8... Main scanning matrix counter, 9... Sub-scanning position counter in matrix, 10... Sub-scanning matrix counter, 11... Thinning-out determination circuit, 12...・Thinning circuit. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] In an image expressed in halftone by the dither method, a dither matrix size setting means, a means for instructing the position of the dither matrix to be processed by the dither matrix size setting means, a means for setting a reduction ratio, and a means for setting the reduction ratio. A means for reducing the pixel being processed in the dither matrix by means for setting a rate, and selecting from the respective values of the means for indicating the position and the means for reducing the pixel when thinning out the pixel pointed by these means. 1. A pseudo-halftone image reduction device comprising: a thinning determining means for determining whether or not a pixel is present; and a means for thinning out predetermined pixels from an original image signal by the thinning determining means.