JP2601156B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus for performing dither binarization processing.

[0002]

2. Description of the Related Art Conventionally, in image processing for inputting a multi-level image signal and comparing it with a dither pattern threshold value to binarize,
In particular, when the threshold pattern is a centralized type such as a halftone dot pattern shown in FIG. 2A, binarization is performed after sufficiently reducing the noise component of the input multilevel image signal. This is a general configuration. Conventionally, a low-pass filter has been used to reduce this noise component. If the noise component is not reduced by this low-pass filter, FIG.
This causes the dot shape to deteriorate as shown in FIG.

[0003]

In this conventional configuration, the output of the low-pass filter is binarized by dithering.
Although the noise component is generally reduced, there is a problem that the sharpness of the image after dither binarization is reduced.

[0004]

According to the present invention, extracting means for extracting a signal of each pixel of a dither pattern size having a predetermined number of pixels in the main scanning and sub-scanning directions from a multi-valued image signal, and an extracting means Averaging means for outputting an average value of a multi-valued image signal corresponding to a pixel around the pixel of interest from the multi-valued image signal extracted by the above, and calculating a difference between the multi-valued image signal corresponding to the pixel of interest and the average value Subtracting means, selecting means for selecting one of the multi-valued image signal and the average value corresponding to the pixel of interest according to the magnitude of the difference, and outputting the output of the selecting means using the dither matrix of the dither pattern size. An image processing apparatus including dither binarizing means for binarizing by the dither method is obtained.

According to the present invention, there is provided an extracting means for extracting a signal of each pixel of a dither pattern size having a predetermined number of pixels in the main scanning and sub-scanning directions from a multi-valued image signal,
An averaging circuit for calculating an average value of a multi-valued image signal having the same pixel array as the dither pattern size from an output of the extracting means by an averaging coefficient set from the outside, A selection circuit and a subtraction circuit having one input of the multi-level image signal and the output of the averaging circuit as the other input, a comparison circuit for comparing the output of the subtraction circuit with a threshold value set from the outside, And a dither binarizing circuit for binarizing the output based on a dither method, wherein an output of the comparison circuit is connected and configured as a selection signal of a selection circuit.

[0006]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In this embodiment, the dither pattern size is 4 pixels in the main scan × 4 pixels in the sub-scan.

[0008] Multi-level image signal ID input from terminal T1
Consists of 8-bit parallel digital data representing 256 gradations per pixel. The multilevel image signal ID input from the terminal T1 is connected to the line memories 1A and 1
B, 1C, and the multi-valued image signal ID that does not pass through the line memory is further input to the one-pixel delay registers 2A, 2B,
2C, 2D, the output of the line memory 1A is sent to the one-pixel delay registers 2E, 2F, 2G, 2H, and the output of the line memory 1B is sent to the one-pixel delay registers 2I, 2J, 2K,
2L and the output of the line memory 1C are supplied to one-pixel delay registers 2M, 2N, 2O, and 2P. Each line memory and one-pixel delay register has an 8-bit parallel input / output terminal, and other circuits also process in 8-bit units. With the above configuration, the multi-valued image signal ID is expanded into 4 pixels in main scanning and 4 pixels in sub-scanning, and the output of each one-pixel delay register is supplied to the averaging circuit 3. Therefore, the line memories 1A to 1C and the registers 2A to 2P constitute extraction means for extracting a signal of each pixel having a dither pattern size.

The averaging circuit 3 is supplied with an averaging coefficient N from a terminal T4 in advance. The averaging circuit 3 performs the averaging of the multivalued image signals of 4 × 4 = 16 pixels supplied from each one-pixel delay register.

[0010]

The pixel to be averaged may or may not include the target pixel. At this time, the averaging coefficient N
Controls the magnitude of the output value. The output of the averaging circuit 3 is supplied to a selection circuit 4 and a subtraction circuit 5.

The output of the one-pixel delay register 2J is connected to the other input terminals of the selection circuit 4 and the subtraction circuit 5, respectively. The one-pixel delay register 2J is a pixel of interest of the dither pattern in the dither binarization circuit 7, that is, a pixel at a position where binarization is output.

The subtraction circuit 5 calculates the difference between the output of the averaging circuit 3 and the pixel of interest, and the comparison circuit 6 compares the calculated difference with the threshold value TH input from the terminal T3.
The comparison result becomes a selection control signal of the selection circuit 4. Here, when the output of the subtraction circuit 5 is larger than the threshold value TH, that is, the difference between the value of the target pixel and the average value of the peripheral pixels is equal to the threshold value T.
If a comparison result that is larger than H occurs, the selection circuit 4 is controlled to select the average value of the peripheral pixels. In the opposite case, the value of the target pixel is selected. Selection circuit 4
Is binarized by a dither binarization circuit 7 and output from a terminal T2 as an output image signal OD. The dither pattern pixel array of the dither binarization circuit 7 is 4 pixels in the main scan ×
The number of pixels in the sub-scanning direction is 4 pixels, and is made to match the pixel arrangement input to the averaging circuit 3.

With the above-described configuration, as a pre-process for dither binarization, when there is a difference between the value of the pixel around the target pixel and the value of the target pixel, the average value of the peripheral pixel signals is used as the target pixel. And performs an operation of performing dither binarization processing.

The replacement of the pixel of interest with the average value of the pixels around it is controlled by the value of the threshold value TH input from the terminal T3. The average of the values of the peripheral pixels is controlled by the averaging coefficient N input from the terminal T4. The threshold value TH and the averaging coefficient N are determined by the "picture" of the input multivalued image. The threshold value TH has the same range as the number of gradations of the input multi-valued image. In this embodiment, since the 16-pixel array of 4 pixels in the main scanning and 4 pixels in the sub-scanning is targeted, the averaging coefficient N is set to 16 as a reference. If the averaging coefficient N is set to be larger than 16, it becomes possible to obtain a smaller average value of the peripheral pixels. If the averaging coefficient N is set smaller than 16, it is possible to obtain a larger average value of the peripheral pixels.

If the "picture" of the input multivalued image has a gradual gradation change or uniform gradation, the threshold value TH is set close to "1" (8-bit data of "0000001"). . That is, when the value of the target pixel is slightly protruded from the average value of the peripheral pixels, the value is replaced with the average value of the peripheral pixels. Conversely, if “picture” has a sharp gradation change in the 16-pixel array, the threshold value TH is set to “1”.
, The replacement of the peripheral pixels with the average value is reduced, and a fine gradation change is prioritized.

[0017]

As described above, according to the present invention, any one of them is input to the dither binarization circuit at the preceding stage of the dither binarization circuit in accordance with the difference between the average value of the pixel of interest and its surrounding pixels. In addition, since a threshold value for controlling the degree of the difference can be set, it is possible to reduce the noise image after dither binarization corresponding to "picture".

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a plan view showing an example of a dither pattern.

[Explanation of symbols]

1A, 1B, 1C Line memories 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2
I, 2J, 2K, 2L, 2M, 2N, 2O, 2P 1
Pixel delay register 3 Averaging circuit 4 Selection circuit 5 Subtraction circuit 6 Comparison circuit 7 Dither binarization circuit

Claims (5)

(57) [Claims] An extracting means for extracting a signal of each pixel of a dither pattern size having a predetermined number of pixels in a main scanning direction and a sub-scanning direction from a multi-valued image signal; and a multi-valued image signal extracted by the extracting means. Averaging means for outputting an average value of a multi-level image signal corresponding to pixels around the pixel of interest;
Subtraction means for calculating a difference between the multi-valued image signal corresponding to the pixel of interest and the average value, and selecting one of the multi-valued image signal corresponding to the pixel of interest and the average value according to the magnitude of the difference An image processing apparatus comprising: a selection unit that performs binarization; and a dither binarization unit that binarizes an output of the selection unit by a dither method using a dither matrix having the dither pattern size. 2. The image processing apparatus according to claim 1, wherein the extracting unit is configured to extract a line memory arranged in accordance with a number of pixels to be extracted in a sub-scanning direction, the multi-level image signal, and an output of the line memory in a main scanning direction. 2. The image processing apparatus according to claim 1, further comprising one-pixel delay means for delaying one picture at a time. 3. The apparatus according to claim 1, wherein the averaging means outputs an average value obtained by dividing a sum of multi-valued image signals for pixels around the pixel of interest by an averaging coefficient set from outside. The described image processing device. 4. A comparison circuit for comparing the magnitude of the difference with an externally set threshold value, and a multi-valued image signal corresponding to the pixel of interest according to an output of the comparison circuit. 2. The image processing apparatus according to claim 1, further comprising a selection circuit that selects one of the average values. 5. Extraction means for extracting a signal of each pixel of a dither pattern size having a predetermined number of pixels in the main scanning and sub-scanning directions from a multi-valued image signal, and extracting from the output of the extraction means the same as the dither pattern size. An averaging circuit that calculates the average value of the multi-valued image signal of the pixel array by an averaging coefficient set from the outside, and one of the multi-valued image signals corresponding to the target pixel of the pixel array having the same dither pattern size as the input. A selection circuit and a subtraction circuit having the output of the averaging circuit as the other input, a comparison circuit for comparing the output of the subtraction circuit with an externally set threshold value, and an output of the selection circuit based on a dither method. An image processing apparatus comprising: a dither binarization circuit for performing binarization by means of a comparator; and connecting the output of the comparison circuit as a selection signal of the selection circuit.