JPH07115539A - Image processor - Google Patents

Abstract

PURPOSE:To reduce deterioration in a shape of a dither pattern after binarization when a multi-valued image signal is subject to dither binarization processing. CONSTITUTION:The processor has a dither binarization circuit 7 and line memories 1A-1C arranging the same picture elements as those of a dither pattern size, 1-picture element delay registers 2A-2P, an averaging circuit 3, a selection circuit 4, a subtractor circuit 5 and a comparator circuit 6 are provided in the pre-stage of the circuit 7. The subtractor circuit 5 is used to obtain a difference between a picture element of interest and a mean value of surrounding picture elements and allows the selection circuit 4 to select the notice picture element or the mean value of the surrounding picture elements depending on the difference to reduce deterioration in a dither pattern shape after binarization. Furthermore, a threshold level is set depending on the image pattern to optimize the image after the binarization.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus for performing dither binarization processing.

[0002]

2. Description of the Related Art Conventionally, in image processing in which a multi-valued image signal is input and compared with a dither pattern threshold value to be binarized,
Particularly, when the threshold pattern is a centralized type such as the halftone dot pattern shown in FIG. 2A, it is preferable to sufficiently reduce the noise component of the input multi-valued image signal and then binarize it. This is a general configuration. Conventionally, a low pass filter is used to reduce this noise component. If the noise component is not reduced by this low-pass filter, FIG.
This is because it causes deterioration of the dot shape as shown in.

[0003]

In this conventional configuration, since the output of the low pass filter is dither binarized,
Although the noise component is generally reduced, there is a problem that the sharpness of the image after dither binarization is lowered.

[0004]

According to the present invention, an extracting means for extracting a signal of each pixel of a dither pattern size having a predetermined number of pixels in the main scanning and sub-scanning directions from a multi-valued image signal, and an extracting means. Averaging means for outputting the average value of the multi-valued image signals corresponding to the pixels around the target pixel from the multi-valued image signal extracted by, and the difference between the multi-valued image signal corresponding to the target pixel and the average value. Subtracting means, selecting means for selecting one of the multivalued image signal and the average value corresponding to the pixel of interest according to the magnitude of the difference, and the output of the selecting means using the dither matrix of the dither pattern size. An image processing apparatus including a dither binarization unit that binarizes by the dither method is obtained.

Further, according to the present invention, extracting means for extracting a signal of each pixel having a dither pattern size having a predetermined number of pixels in the main scanning and sub-scanning directions from the multi-valued image signal,
An averaging circuit that calculates an average value of a multi-valued image signal having the same pixel array as the dither pattern size from the output of the extraction unit with an averaging coefficient set from the outside, and an averaging circuit that corresponds to a target pixel having the same pixel array as the dither pattern size A selection circuit and a subtraction circuit having one input of the multi-valued image signal and the output of the averaging circuit as the other input, a comparison circuit for comparing the output of the subtraction circuit and a threshold value set from the outside, and a selection circuit An image processing apparatus is provided which includes a dither binarization circuit that binarizes an output based on a dither method, and is configured to connect an output of a comparison circuit as a selection signal of a selection circuit.

[0006]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In this embodiment, the dither pattern size is 4 pixels in the main scanning × 4 pixels in the sub scanning.

Multivalued image signal ID input from the terminal T1
Consists of 8-bit parallel digital data representing 256 gradations per pixel. The multi-valued image signal ID input from the terminal T1 is the line memories 1A, 1 that are serial to each other.
The multi-valued image signal ID, which is sequentially input to B and 1C and does not pass through the line memory, is added to the 1-pixel delay registers 2A, 2B,
2C, 2D, the output of the line memory 1A to the 1-pixel delay registers 2E, 2F, 2G, 2H, and the output of the line memory 1B for the 1-pixel delay registers 2I, 2J, 2K,
2L, and the output of the line memory 1C is supplied to the 1-pixel delay registers 2M, 2N, 2O, 2P. Each line memory and 1-pixel delay register have 8-bit parallel input / output terminals, and other circuits are also processed in 8-bit units. With the above configuration, the multi-valued image signal ID is expanded into 4 pixels in the main scanning × 4 pixels in the sub scanning, and the output of each 1-pixel delay register is supplied to the averaging circuit 3. Therefore, the line memories 1A to 1C and the registers 2A to 2P constitute extraction means for extracting the signal of each pixel having the dither pattern size.

The averaging circuit 3 is previously supplied with the averaging coefficient N from the terminal T4. The averaging circuit 3 averages the multi-valued image signals of 4 × 4 = 16 pixels supplied from each 1-pixel delay register.

[0010]

The pixel to be averaged may or may not include the target pixel. At this time, the averaging coefficient N
Controls the magnitude of the output value. The output of the averaging circuit 3 is supplied to the selecting circuit 4 and the subtracting circuit 5.

The output of the one-pixel delay register 2J is connected to the other input terminals of the selection circuit 4 and the subtraction circuit 5, respectively. The one-pixel delay register 2J is a pixel of interest in the dither pattern in the dither binarization circuit 7, that is, a pixel at a position for binarization output.

The subtraction circuit 5 calculates the difference between the output of the averaging circuit 3 and the pixel of interest, and the comparison circuit 6 compares the calculated difference with the threshold value TH input from the terminal T3.
The comparison result becomes the selection control signal of the selection circuit 4. Here, when the output of the subtraction circuit 5 is larger than the threshold value TH, that is, the difference between the value of the target pixel and the average value of the peripheral pixels is the threshold value T.
When the comparison result of being larger than H occurs, the selection circuit 4 is controlled to select the average value of the peripheral pixels. In the opposite case, the value of the pixel of interest is selected. Selection circuit 4
Is binarized by the dither binarization circuit 7 and output as an output image signal OD from the terminal T2. The dither pattern pixel array of the dither binarization circuit 7 is 4 pixels in the main scan.
The number of pixels in the sub-scan is set to 4 and is made to match the pixel array input to the averaging circuit 3.

With the above configuration, as a preprocessing for dither binarization, when there is a difference between the value of the pixel around the pixel of interest and the value of the pixel of interest, the average value of the pixel signals of the surrounding pixels is used. The value is replaced with the value of and the dither binarization process is performed.

The replacement of the target pixel with the average value of the values of the pixels around it is controlled by the value of the threshold value TH input from the terminal T3. The average value of the peripheral pixel values is controlled by the averaging coefficient N input from the terminal T4. The threshold value TH and the averaging coefficient N are determined by the "picture" of the input multivalued image. The threshold value TH has the same range as the number of gradations of the input multi-valued image. In this embodiment, a 16-pixel array of 4 pixels in the main scanning and 4 pixels in the sub-scanning is targeted, and therefore the averaging coefficient N is set to 16 as a reference. If the averaging coefficient N is set to be larger than 16, it is possible to obtain a smaller average value of the peripheral pixels. Further, if the averaging coefficient N is set to be smaller than 16, it becomes possible to obtain a larger average value of the peripheral pixels.

When the "picture" of the input multi-valued image has a smooth gradation change or a uniform gradation, the threshold value TH is set close to "1" (8-bit data of "0000001"). . That is, when the value of the pixel of interest is slightly protruded from the average value of the peripheral pixels, it is replaced with the average value of the peripheral pixels. On the contrary, when the “picture” has a sudden gradation change in the 16-pixel array, the threshold value TH is set to “1”.
Is set far away from the pixel, replacement of surrounding pixels with the average value is reduced, and fine gradation change is prioritized.

[0017]

As described above, according to the present invention, one of the two is input to the dither binarization circuit before the dither binarization circuit, depending on the difference between the average value of the pixel of interest and its peripheral pixels. In addition to the above configuration, the threshold value for controlling the degree of the difference can be set, so that it is possible to reduce the noise image after the dither binarization corresponding to "pictures".

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a plan view showing an example of a dither pattern.

[Explanation of symbols]

1A, 1B, 1C line memory 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2
I, 2J, 2K, 2L, 2M, 2N, 2O, 2P 1
Pixel delay register 3 Averaging circuit 4 Selection circuit 5 Subtraction circuit 6 Comparison circuit 7 Dither binarization circuit

Claims (5)

[Claims] 1. Extraction means for extracting a signal of each pixel of a dither pattern size having a predetermined number of pixels in the main scanning and sub-scanning directions from the multi-valued image signal, and from the multi-valued image signal extracted by the extraction means. Averaging means for outputting an average value of multi-valued image signals corresponding to pixels around the pixel of interest,
Subtracting means for calculating the difference between the multi-valued image signal corresponding to the target pixel and the average value, and selecting one of the multi-valued image signal corresponding to the target pixel and the average value according to the magnitude of the difference. And a dither binarization unit that binarizes the output of the selection unit by a dither method using a dither matrix of the dither pattern size. 2. The extracting means according to the number of pixels for extracting the line memory arranged according to the number of pixels to be extracted in the sub-scanning direction, the multi-valued image signal and the output of the line memory in the main scanning direction. The image processing apparatus according to claim 1, further comprising a one-pixel delay unit that delays one image at a time. 3. The averaging means outputs an average value obtained by dividing a total sum of multi-valued image signals with respect to pixels around the target pixel by an averaging coefficient set from the outside. The described image processing device. 4. The selection means compares the magnitude of the difference with a threshold value set from the outside, a multi-valued image signal corresponding to the pixel of interest according to the output of the comparison circuit, and the comparison circuit. The image processing apparatus according to claim 1, further comprising a selection circuit that selects one of the average values. 5. Extraction means for extracting a signal of each pixel having a dither pattern size having a predetermined number of pixels in the main scanning and sub-scanning directions from the multi-valued image signal, and the same dither pattern size as the output from the extraction means. An averaging circuit that calculates the average value of the multi-valued image signal of the pixel array with an averaging coefficient set from the outside, and one input of the multi-valued image signal corresponding to the pixel of interest having the same pixel array as the dither pattern size. A selection circuit and a subtraction circuit that use the output of the averaging circuit as the other input, a comparison circuit that compares the output of the subtraction circuit with a threshold value set from the outside, and the output of the selection circuit based on the dither method. And a dither binarization circuit for binarizing the image data, and connecting the output of the comparison circuit as a selection signal of the selection circuit.