JPS6345663A - Input/output interface - Google Patents

Abstract

PURPOSE:To obviate an exclusive external bus type mode signal line connected to a CPU by providing a means which detects the presence of an address latch enable signal to a conventional input/output interface that can correspond to two types of CPU. CONSTITUTION:In case an input/output interface 20 is used as an input/output port of a multiplex CPU, an address latch enable signal ALE C is detected by a flip-flop circuit 21. The circuit 21 supplies continuously a level signal B indicating a multiplex bus type to a type indicating signal terminal 3-1. While the signal ALE C is not delivered from the CPU as long as a non-multiplex CPU is connected to a read/write control circuit 10. Therefore a level signal '0' is supplied to the terminal 3-1 from the circuit 21. As a result, an address control circuit 9 can select an internal bus in response to the type of the CPU.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multiplex type processing unit (CPU) that multiplexes and transmits data and addresses, and a non-multiplex type CPU that transmits data and addresses separately.
The present invention relates to an input/output interface that can support both CPUs of a PU.

[Prior Art] As input/output interfaces for -S, a processing unit (CPtl) in which data and addresses are multiplexed, and a non-multiplexed (non-multiplexed) CPU, There is an input/output interface that corresponds to each bus type.

An input/output interface that realizes these two types of input/output interfaces as one interface is being considered.

FIG. 3 shows an example of a conventional configuration of an input/output interface.

In FIG. 3, 15 is a block showing an input/output interface that can support a multiplex type CPU and a non-multiplex type CPU.

Here, 1 transfers data when the input/output interface 15 is connected to a non-multiplex type CPU, and the input/output interface 15 connects to a multiplex type CPU.
When connected to the PU, it is a bus that transfers addresses and data. This bus 1 is connected to the address control circuit 9
It is connected to terminal 1-1 of.

2 is a latch signal line (^LE), and when the input/output interface 15 is connected to the multiplex type CPU, the address latch enable signal C for latching the address signal shown in FIG. 4 is sent to the address control circuit. This is a signal line that is transmitted to terminal 3-1 of 9.

Reference numeral 3 denotes a CPU mode signal line that transmits a pasta live signal sent from CPt1 connected to the input/output interface. This mode signal line 3 is connected to the input/output interface 1
5 is under the control of the multiplex type CPU, an external mode signal A of "1" as shown in FIG. 4, for example, is transmitted to the terminal 2-1 of the address control circuit 9.

A reset signal line 4 is a signal line that is sent from the CPU to the input/output interface 15 and transmits a reset signal for resetting the interface 15 to the terminal 4-1 of the address control circuit 9.

5 is an address signal line from the non-multiplex type CPU.

Reference numeral 6 denotes a write signal line that transmits a write signal from the CPU that instructs to write data into a random access memory (not shown) or the like.

A signal line 7 transfers a read signal from CP[] that gives an instruction to read data from the random access memory.

Reference numeral 8 denotes a data bus buffer for temporarily storing data when transferring the data to the above-mentioned random access memory or other input/output devices.

Reference numeral 9 denotes an address control circuit that receives addresses and data depending on the type of CPII, ie, multiplex type or non-multiplex type.

The input/output interface 15 also includes a read/write control circuit 10 that reads and writes data to and from a random access memory, and an input/output port control circuit 12 that transfers input data to a random access memory or a board such as a CPU.

However, conventionally, this type of input/output interface has two
A level signal (CPU mode signal) indicating the type of bus is required in order to select the appropriate type of bus type from among various types of CPU bus types (multiplex type/non-multiplex type). Therefore, a circuit system is adopted in which this level signal sent from the CPU is detected by the address control circuit 9, and the address control circuit controls the path line connecting the internal circuits of the input/output interface 15 according to the detection signal. Ta.

Therefore, the CPU sends out the CPU as shown in Figure 4.
There is a problem in that a dedicated CPU bus type designation signal line 3 for transferring the Pu bus type signal A must be provided.

Another problem is that each CPU must send a level signal indicating the type of bus to the input/output interface 15.

[Problems to be solved by the invention] Therefore, the purpose of the present invention is to solve such problems,
To provide an input/output interface that can determine the type of bus with a simple configuration without requiring a signal from a CPU to indicate the type of bus.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a first oil processing device that multiplexes data and addresses and sends out the multiplexed signal together with an address latch enable signal; and means for detecting the presence or absence of an address latch enable signal; The present invention is characterized by comprising means for specifying a bus within the input/output interface as a bus that accepts signals from either the first or second arithmetic processing unit in response to a detection output from the input/output interface.

[Function] The present invention uses a detection means to detect the presence or absence of an address latch enable signal that a multiplex type CPU sends out prior to data and address, and in response to this detection output, connects a bus according to the type of CPU. Since the designated internal bus type designation signal is outputted by the bus designation means, the bus type designation signal from the CPU is not required, and the number of signal lines of external path lines can be reduced.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a circuit configuration in an embodiment of the present invention.

Note that in FIG. 1, the same parts as in FIG. 3 are given the same reference numerals.

In FIG. 1, when the input/output interface 20 is used as an input/output port of a multiplex type CPU,
For example, the address latch enable signal (ALE) C as shown in FIG. To detect. Next, the flip-flop circuit 21 continues to input a level signal B as shown in FIG. 2, which instructs the multiplex type bus type, to the type instructing signal terminal 3-1. Moreover, this level signal B itself is generated when the flip-flop circuit 21 manually inputs the reset signal from CPt1.
The flip-flop circuit 21 sets the initial state.

When the non-multiplex type CPU and the input/output interface 20 are connected, the address latch enable signal is not output from this CPLI, so the type instruction signal terminal 3-1 is output from the flip-flop circuit 21.
A level signal "0" is input to the input terminal. Furthermore, at this time,
The signal level input to the address latch enable signal terminal 2-1 may be set to a level that does not cause the flip-flop circuit 21 to operate.

Therefore, the address control circuit can select an internal bus depending on the type of CPU.

In addition, the address and address used when the input/output interface 20 of a non-multiplexed CPU
Line (multiple bits) 4 is input/output interface 2
Not used when G corresponds to a multiplexed CPU.

Therefore, it is also possible to use the vacant address line 4 and its terminal 4-1 for other purposes.

[Effects of the Invention] As described above, according to the present invention, the means for detecting the presence or absence of an address latch enable signal is provided by 2f!
By simply installing it in a conventional input/output interface that is compatible with the CPU, there is no need for a dedicated external bus-tied mode signal line to connect to the CPU, which has the effect of reducing the number of external path line signal lines. can get.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a circuit configuration in an embodiment of the present invention, and FIG. 2 is a multiplex type CPU in an embodiment of the present invention.
3 is a block diagram showing an example of a conventional circuit configuration. FIG. 4 is a timing chart showing an example of an input signal waveform from a multiplex type CPU in a conventional example. be. 1...CPU bus, 1-1.2-1.3-1.4-1.4-1.5-1...
・Input terminal, 2...Address latch enable signal line, 3...CPU bus type designation signal line for internal input/output interface, 4...Address line, 5...Reset signal line, 6...Write Command signal line, 7... Read command signal line, 8... Data bus buffer, 9... Address control circuit, lO... Read/write control circuit, 11... Boat control circuit, 12... Input/output boat control circuit, 15, 20...input/output interface. G ward unreleased B and successful color Iku 11 timed reference completion chart 2nd figure Ib

Claims (1)

[Claims] A first arithmetic processing device that multiplexes data and addresses and sends out the multiplexed signal together with an address latch enable signal, and a second arithmetic processing device that sends out data and addresses without multiplexing them. An input/output interface capable of processing signals sent from either of the input/output interfaces, comprising means for detecting the presence or absence of the address latch enable signal, and a bus in the input/output interface in response to a detection output from the detection means. an input/output interface, comprising means for specifying a bus to receive a signal from either of the first and second arithmetic processing units.