JPS6345128B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to an A/D converter.

The A/D converter converts the input analog quantity into a digital quantity by comparing the analog input current and the reference current using an integral method, or by combining the reference current with multiple weighted current sources and comparing it in a direct current manner. It is common to do so. In such an A/D converter, the reference current source is usually obtained by voltage/current exchange with a voltage from an external stable reference voltage source. Further, in such an A/D converter, especially in the latter case, the initial reference voltage value or its divided voltage is adjusted to set the reference current value, and thus the scale is adjusted. FIG. 1 shows a general A/D conversion method using an integral method. The integrator 10 is constituted by an operational amplifier 3 having an integrating capacitor Co connected between its input and output. There is a switch at the input C of this integrator 10.
By selectively connecting the point a with So, the reference current I _ref from the reference current source 1 is applied, and by selectively connecting the point b, the unknown voltage _V
A current I _X corresponding to each is applied. These reference current source 1 and current source 2 convert reference voltage V _ref and unknown voltage V _X into reference current I _ref and unknown current I _X , respectively.
is being converted to . In this _method , the current _I
By inversely integrating the subsequent period until the integral value reaches the initial value, the current _I Since it is known from US Pat. No. 3,316,547, it will not be described in detail here. Here, prior to the conversion operation, the reference voltage V _ref is adjusted to adjust the reference current I _ref , and generally this reference current I _ref is the full scale of the converter, that is, the maximum value of the current _I It is mapped to I _X (max). however,
Although such scale adjustment is initially effective, it is not always effective due to temperature changes, long-term changes in device characteristics, and the like. Errors in such scale adjustment can be broadly classified into fluctuations in the external reference voltage value V _ref itself and errors due to fluctuations in the A/D converter itself (generally referred to as gain errors among those in the industry). In particular, in A/D converters constructed with C-MOS monolithic integrated circuits, the A/D
The gain error of the converter itself is relatively large, and there has been an increasing need to develop a circuit that automatically corrects this error. Such a gain error occurs, for example, when the potential of the input terminal C of the amplifier 3 fluctuates during operation, and therefore the offset value between it and the biased terminal d of the integrator 10 fluctuates. do. In addition, when converting voltage and current from a temperature sensor using a thermistor, etc., the ratio to the voltage applied to the sensor section is detected, and in this type of application, essentially the reference voltage By using the voltage applied to the sensor as the source, fluctuations in the reference voltage source will not cause a scale error, and only the gain error of the A/D converter itself will cause a scale error. There was an increasing need to develop automatic correction circuits.

The purpose of the present invention is to have an automatic scale adjustment function that can be configured by appropriately using a current source circuit,
In particular, the object is to provide an A/D converter that is suitable for construction as a monolithic integrated circuit.

A current source circuit according to the present invention includes a first current control means capable of generating a predetermined current value, a second current control means whose current value is controlled by the output of an amplifier, and a first current control means. It is characterized by comprising means for detecting a difference current between the controlled current value and a predetermined current value, and using this difference current to control the output of the amplifier so that the current value becomes the predetermined current value. .

The current source circuit according to the present invention described above has a function of automatically correcting the current value to a predetermined value, and this current value can be automatically corrected by using it as a reference current in various types of A/D converters. Accordingly, it is possible to easily realize an A/D conversion device that allows scale adjustment.

Next, a current source circuit according to the present invention will be explained with reference to FIG. The normal input terminal (+) of the differential amplifier 20 is connected to a predetermined potential V _b , and its output is
It is applied to the base of the NPN transistor T _r1 , and is connected from the collector of the transistor T _r1 to the inverting input terminal (-) of the amplifier ₂₀ via the capacitor C1. The collector of this transistor T _r1 is connected to the emitter of a PNP transistor T _r2 whose collector is connected to the power supply +Vc and _whose base and exit are commonly connected.
is grounded through. transistor here
T _r1 and the resistor R constitute a first current source 22 . On the other hand, the collector of the PNP transistor T _{r3 whose base is connected to the power supply +Vc collector and the base of the transistor T r2 is} connected to the first terminal whose one end is grounded.
The current source 21 is connected to the other end of the current source 21 . Further, this collector is connected to the inverting input terminal (-) of the amplifier 20 via the analog switch _SW1 .
Here, the first current source 21 is used as a reference current source,
The difference current detection circuit 23 composed of transistors T _r2 and T _r3 is used to
By connecting the emitter of T _r3 and the inverting input terminal (-) of the amplifier 20 via the switch SW ₁ , a difference is created between the current I ₂ and the current I ₁ of the second current source 22, and this causes the current This is to adjust I ₂ to the value of current I ₁ .

The operation will be explained below.

That is, the current I ₂ in the second current source 22, which converts the voltage applied to the emitter resistance (R) of the transistor T _r1 into a current and takes out from the collector of the transistor T _r1 , is equal to the voltage applied to the emitter resistor (R) of the transistor T r1. _I1 ) is obtained by the current detection circuit 22 and applied to the inverting input terminal (-) of the differential amplifier 20 via the closed analog switch _SW1 , and the capacitor _C1 is This charging is applied to the amplifier 20 so as to control the transistor T _r1 and stops when the difference current becomes 0, and in this state, an equilibrium state is achieved. This circuit 23 generates a current of the same value as the current I ₂ through the transistor T _r3 .
I ₂ is passed and the switch of the difference between this current and the current I ₁
This is applied to capacitor C via _SW1 .

Next, the operation of this circuit will be explained in more detail.

Error voltage across the resistor at time to (−ΔV _io )
If the differential flow at time to due to is Io(to),
It is possible to exchange votes as Io(to)=-ΔV _io /R. The difference current Io (t ₁ ) at any time t ₁ after the switch SW ₁ closes is Io (t _{1 )} = -ΔV _io /R-1/C
By R ∫ ^t ₁ ^/to Io(t)αt, the difference current at time t ₁ is Io
(t)=ΔV _io /RE−t ₁ /CR. Here C is the capacity C
The capacitance value is ₁ . The noise error voltage component (Ve) of C ₁ at time t ₁ is V _E =−ΔV _io e−t ₁ /CR. This residual error voltage component attenuates over time.
This time change or response characteristic is shown in FIG.

Now, a specific example will be considered in which the first and second current source currents are automatically corrected to an error within 0.01% when Vb=10V ΔV _io =100mV.

The conditions are V _E /ΔV _io ·ΔV _io /V _b <0.01% to V _E /ΔV _io <1%.

If R=50kΩ and C=0.02μF, then CR=
1.10 ^-3 sec=1ms According to Figure 2, after the time to,
Automatic correction will be completed after approximately 5msec. That is,
When the analog switch (SW ₁ ) is opened after 5 msec, the equicurrent properties of the first and second current sources 21 and 22 are maintained. Furthermore, a MOR FET or a junction FET (Field Effect Trausistor) is effective as a component of the analog switch (SW ₁ ). The opening and closing of an analog switch using these elements is controlled by a control voltage applied to the gate terminal. However, in a FET, there is a parasitic capacitance between the channel region and the gate, and due to the amplitude of the control voltage (ΔVs) during switching, charge transfer occurs through the parasitic capacitance (Cg) to the capacitor _C1 , resulting in additional charge. generates an error voltage (ΔV _E ).

This error voltage can be expressed as ΔV _E =Cg/C·ΔVs. For example, Cg=2pF C=0.02μF ΔVs=
At 10V, ΔV _E =1mV.

Next, another current source circuit according to the present invention will be explained with reference to FIG.

Here, the normal input terminal (+) of the differential amplifier 20
is passed through the second capacitor C ₂ to a constant bias potential V _b
A second analog switch SW 2 is connected to the capacitor C ₂ to selectively shunt the second capacitor C ₂ .
Connected in parallel to C ₂ . The second current source 22' is composed of an n-channel FET _Q6 and a resistor R, and the differential current detection circuit 23' is composed of a transistor.
A current inversion circuit is formed using n-channel FETs _Q4 and _Q5 instead of _Tr2 and _Tr3 . This circuit performs an automatic correction operation during a first period when analog switches SW ₁ and SW ₂ are both closed, and a second period when analog switches SW ₁ and SW ₂ are both open. maintains isocurrent property of the current source.

Next, in this example, capacitance C ₂ and switch
The effect of adding SW ₂ will be explained. Here, we will consider again the case where a field effect transistor is used as an analog switch. Let ΔVe 1 and ΔVe ₂ be the error voltages due to charges transferred to capacitances C ₁ and C ₂ (transfer charge) during switching, respectively. _{ΔVe 1 =} Cg ₁ /C ₁ ΔVs, ΔVe ₂ = Cg ₂ /C ₂ ΔVs. ΔVs is the amplitude of the common control voltage of switches SW ₁ and SW ₂ , and Cg ₁ and Cg ₂ are the channel-to-gate capacitances of SW ₁ and SW ₂ , respectively. In the case of C ₁ = C ₂ Cg ₁ = Cg ₂ , ∆Ve ₁ = ∆Ve ₂ , and ideally the error voltage due to the charge transfer associated with the opening and closing of the switch is complementarily canceled and applied to the output of the amplifier 20. produces an output that is not affected by error voltage.

By the way, if the FET and capacitor are manufactured using a monolithic integrated circuit, a good value of relative accuracy of 0.1% order can be obtained. This is largely due to the recent progress in monolithic integrated circuit manufacturing technology, and using this technology it is actually possible to make the second embodiment of the present invention monolithic. That is,
From a relative accuracy of 0.1%, in this second embodiment, the element conditions (R=
50kΩ C=0.02μF), C ₁ =C ₂ =20pF=
The same performance can be obtained with 0.02μf/1000. That is, the word difference voltage due to charge transfer can be set to a desired small value. As an additional effect, the time constant becomes CR=1 μS, and the automatic correction operation is completed approximately 5 μsec after the above-mentioned time point to.
Further, the second embodiment of the present invention described above will be shown in more detail using FIG. Here, the first and second
C-MOS as analog switches SW ₁ and SW ₂
(complementary field effect transistor) is used,
This is a circuit in which all elements, including differential amplifiers and other circuit configurations, can be made monolithic using C-MOS integrated circuit technology. Switch _SW1 is a P channel type with source and drain connected in parallel.
Consisting of FET Q ₉ and N-channel FET Q ₁₀ , control signal φA is applied to the gate of FET Q ₉ , an inverted signal of control signal φA is applied to the gate of FET Q ₁₀ , and FET Q ₉ and _Q10 are controlled to be conductive or non-conductive at the same time. Similarly, switch SW ₂ has the control signal φA applied to the gate of P channel FET Q ₇ and the signal applied to the gate.
Consists of FET Q ₈ connected in parallel, switch
Conduction and non-conduction are controlled in synchronization with SW ₁ . Here, current extraction analog switches SW ₅ and SW ₆ are provided between the first current source 21 and the differential current detection circuit 23'. These switches SW ₅ and SW ₆ are used to output the same current value to the outside after the currents of the two current sources are corrected to _the same current value.
By connecting to the B ₅ side, a current equal to the current value I ₂ of the second current source 22' is output to the terminal Io ₂ , and by connecting the switch SW ₆ to the B ₆ side, the first current source 21
The current I ₁ is output from terminal Io ₁ . The current output from this terminal Io ₁ is the current source 21 after correcting the current I ₂
can be used as a current source that can take any value to output a current of any value.

In this example, analog switch SW ₁ is C-
By adopting a MOS switch, it is possible to significantly reduce the transfer charge that occurs in such a switch as the switch changes from closing to opening.

Referring to FIG. 6, transfer charge accompanying the closing and opening of this switch will be explained.

Curves 5P and 5N in Figure 6 switch P-channel MOS and N-channel MOS, respectively.
The graph shows the relationship between the source voltage V _B and the step error voltage caused by transfer charge when the gate voltage is +5 V when changing from the conductive state to the non-conductive state when used as SW ₁ . From this, P channel MOS is positive N channel
It can be seen that MOS produces a negative step error. The curve 5m is the P channel shown in Figure 4.
It shows the step error voltage when a MOS and an N-channel MOS are connected in parallel, and it can be seen that a positive step error voltage occurs in a high V _B region, and a negative step error voltage occurs in a low V _B region. Curve 5S switch
It shows a negative step error voltage at an offset value between the two input terminals of the amplifier (A ₁ ) 20 when operated simultaneously on SW ₁ and SW ₂ , and the effect of the very step error voltage is particularly reduced. I can understand that there are. That is, at the time of transition from the analog switch "ON" state to the "OFF" state, specifically, from the first period in which automatic correction is performed to the second period of the holding period, P ch and N ch Both MOS FETs transition from the “ON” state to the “OFF” state. At this time, P
Part or all of the remaining holes in the ch FET and the remaining electrons in the N ch FET recombine, and the remaining charge is transferred to the capacitor. Therefore, C ₁ ,
The amount of charge transferred to C ₂ decreases, the error voltage decreases, and the error voltage decreases.

In curve 5S showing the actual experimental results, V _B 1/2 V ⁺ , and when the FET control signal has an amplitude of approximately 0 to V ⁺ , almost all of the remaining holes and electrons recombine and become capacitance. The amount of charge transfer is minute,
The step error voltage became almost zero. Further V _B
Even in the range of ≠1/2V ⁺ , very good characteristics are obtained as shown in 5. In other words, as shown by curve 5S, V ⁺ = 5V due to simultaneous operation of SW ₁ and SW ₂ .
It was observed that the negative step error voltage was within ±0.5 mV in the range of 0.25 V < V _B < 4 V.

Next, an embodiment of an A/D converter using a current source circuit according to the present invention will be described with reference to FIG.

In this embodiment, the first current source circuit 21'' is an N-channel FET Q ₁₀ whose gate is controlled by the power of a differential amplifier (A ₂ ) 30, and whose drain is a resistor.
Differential amplifier (A ₂ ) as well as grounded through R ₂
30 is connected to the inverting input (-) to form a feedback path. The normal input (+) 30a of the differential amplifier (A ₂ ) 30 is selectively supplied with a correction reference voltage V _ref and an unknown potential V _io to be measured via switches SW ₃ and SW ₄ , respectively. It's like getting.
The output 30d of the first current source circuit 21'' is configured to be connectable to the terminal 23b of the differential current detection circuit 23' via switches SW ₆ and SW ₅ .
Differential current detection circuit 23', first current source circuit 23', second current source circuit 22', and differential amplifier (A ₁ ) 2
The structure of the portion containing 0 is the same as that shown in FIG. 4 described above, so the details will not be described. Integral comparison circuit 1
00 includes an operational amplifier 101 with an integral capacitor C100 connected to input/output 100C to 100d, and an integral value comparison circuit 102 connected to the output 100d from the amplifier 101, and a switch connected to the input 100C of the amplifier 101. 7, so that a current can be inputted thereto. Control circuit (CNTL)
120 is an integral comparison circuit 100 and a switch SW ₁
~SW ₇ is controlled, a digital value is calculated, and the result is output from the terminal 115.

Next, the operation of this A/D converter will be explained.

During the first period during which automatic scale adjustment is performed, analog switches SW ₁ , SW ₂ , and SW ₃ are closed, and SW ₇ is opened to configure a circuit similar to that shown in FIG. 3. At this time, a reference voltage V _ref, which is used as a reference for correction, is applied to the second current source circuit 22'', and the current value at this time is
I ₁ has a value proportional to the reference voltage V _ref . That is, it can be expressed as I ₁ =K V _ref (K is a constant). The reference voltage V _ref at this time is preferably selected to a value corresponding to the current I ₁ with the current I ₁ being the maximum value that can be measured by this A/D converter, that is, a full-scale value. The current I ₁ from the current source circuit 21'' set in this manner is made equal to the current I ₂ by the action of the differential current detection circuit ₂₃ ' and the capacitor C ₁ . This has been explained in Figure 3. In this way, the current _I2 is corrected so that it can be used as a reference current in the integral method.Next, an A/D conversion operation is performed.This period is defined as the second period, Furthermore, the following explanation will be made by defining this second period as a period 2-1 in which the measurement current is integrated and a period 2-2 in which inverse integration is performed using the reference current.First, in the period 2-1, switch
SW ₄ is closed and the first current source circuit 21'' generates a current I _1io =KV _ref that is proportional to the measured voltage V _io .
In the local integral comparison circuit 100, switch SW ₅
is open, switches SW ₆ and SW ₇ are closed, and this current I _1io is continuously integrated by the integrator 110 during this 2-1 period. Next, during the period 2-2, switch SW ₅ is closed, switch SW ₆ is opened (switch SW ₇ remains closed), and the current I ₂ as a reference current is applied to the integrator 110 with the opposite polarity to the current I _1io . Then, the integrated value at the end of the 2-1 period is inversely integrated to the initial value at the beginning of the 2-1 period, and this is detected by the comparator (COM) 102. here,
If the length of this 2-2 period is T _C2 and the length of 2-1 is T _C1 , it can be expressed as I ₂ (V _ref )/T _C1 = I _1io (V _io )/T _C2 It is clear that this T _C2 and the known T _C1 and I ₂ (V _ref ) can be used to display I _1io or V _io , and these T _C1 and T _C2 are generally the number of pulses of the same period. Count and define T _C2
It is sufficient to express this in terms of the number of pulses and compare this with a digital quantity. Next, another embodiment of an A/D device using a current source circuit according to the present invention will be described with reference to FIG. The A/D conversion device in this embodiment is an example of a sequential comparison method in which A/D conversion is performed by comparing the measured current with a reference current value or a branch value thereof. In this embodiment, the circuit block 200 including the integral comparison circuit 100 and the current inversion circuit 23' shown in FIG. 7 is replaced with the circuit block 2 shown in FIG.
00'.

The source of the P-channel FET Q ₂₀ is connected to the positive potential +Vc at the connection point 23e via a resistor R with a predetermined resistance value, and the gate and drain are connected in common and connected to the terminal 23a of the second current source circuit 22'. be done. The source is connected from the connection 23e through a resistor 2R with a resistance value twice that of the resistor R, and the gate is connected to the FET.
A FET Q ₂₁ is provided connected to the gate of Q ₂₀ , and its drain is led to the terminal 121 of the switch SW ₈ . In addition, the source was connected to the connection point 23e through the resistors R and 2R connected in series at the connection point 23f, and the gate was connected to the gate of FET Q _20.
A FET Q ₂₂ is provided, the drain of which is led to terminal 122 _of switch SW ₉ . The drain is connected to this connection point 23f via resistors R and 2R connected in series at the connection point 23g.
It is led to the terminal 123 of SW ₁₀ , and the gate is FET Q ₂₀
The source of FET Q ₂₂ is connected to the gate of. Furthermore, the sources are connected to the connection point 23g via a resistor R, and the FETs Q ₂₄ and Q ₂₅ whose gates are both connected to the gate of the FET Q ₂₀ are connected to the connection point 23h via a resistor 2R.
The drain of Q ₂₄ is led to terminal 124 of switch SW ₁₁ , and the drain of FET Q ₂₅ is connected to common line 200.
directly connected to a. In this way,
From the drain of FET Q ₂₁ , a current equal to 1/2 of the current I ₂ flowing through FET Q ₂₀ is applied to terminal 121, and to the drain of FET Q ₂₂ , a current equal to 1/4 of the current I 2 is supplied to the terminal 121. is applied to the terminal 122, and a current with a value of 1/8 is applied to the drain of the FET Q ₂₃ at the terminal 122.
3, FETs Q ₂₄ and Q ₂₅ each have a current of 1/16 magnitude applied to terminal 124 and line 200a. Switch SW ₈ ~
The SW ₁₁ is controlled by the control signals D ₁ to _{D 4} to selectively connect the terminals 121 to 124 to the common line 200a side or the connection line 20c side, respectively. This connection line 20c is connected to an output line 30d from the first current source 21'' and is also input to the comparator 102'.The operation will now be described.

Prior to A/D conversion operation, switch SW ₁ ,
While closing SW ₃ , all switches SW ₈ to _{SW 10} are connected to the line 200a side, and switch SW ₁₂ is connected to the connection line 20c. A current corresponding to the sum of FETs Q ₂₁ to _{Q 25} , that is, a current corresponding to the current I ₂ of FET Q ₂₀ flows through the switch SW ₁₂ and the output line 30d. This current is the reference current I ₁ generated in the first current source circuit 21''.Here, the current I ₁ and
The difference current between I ₂ and capacitor through switch SW ₁
By charging C ₁ , the current I ₂ and the reference current
Correct to the same value as I ₁ . The current I ₂ flowing through FET Q ₂₀ is thus corrected to be equal to the current I ₁ and therefore
Adjustments are made so that currents of I ₂ /2 to _{I 2} /16 can flow through Q ₂₁ to Q ₂₄ , respectively. Next, switch SW ₁ ,
Open SW ₁₂ and switch SW ₈ to SW ₁₁ to line 20
0a side and connect the switch SW ₁₂ to another current absorbing source to enter the conversion operation state. First, switch SW ₄ is closed and the current based on the potential V _io to be measured is
I _1io is generated on the output line 30d, and the other switch
SW ₈ to SW ₁₁ are selectively connected to the connection line 20c side, and this selected total current value and current I _1io
The comparator 102' detects the difference current between the two. When the difference current disappears, the selected current sum of FETs Q ₂₁ to _{Q 24} becomes equal to the current I _1io , and the control circuit 12
0' is the digital value corresponding to this current sum at terminal 1.
15' and the operation ends.

Note that the present invention is not limited to the above-described embodiments and applied examples, and any circuit constituent elements may be used.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the principle of a general A/D conversion device, Fig. 2 is a block diagram showing a current source circuit according to the first embodiment of the present invention, and Fig. 3 is a block diagram showing the current source circuit according to the first embodiment of the present invention. A diagram showing the response characteristics of the current source circuit, FIG. 4 is a block diagram showing another embodiment of the current source circuit according to the present invention, and FIG. 5 is a specific configuration of the current source circuit according to the present invention shown in FIG. 4. FIG. 6 is a diagram showing the step error voltage when FET is used as a switch in the current source circuit according to the present invention, and FIG. 7 is a configuration diagram of an A/D converter with automatic scale adjustment function according to the present invention. 8 are block diagrams of another embodiment of an A/D converter having an automatic scale adjustment function according to the present invention. Codes in the figure: 1; reference current source; 2; current source; 1
0,110; Integrator, 3,101; Operational amplifier,
20, 30; differential amplifier; 21; first current source;
22, 22'; second current source; 23, 23'; differential current detection circuit.

Claims (1)

[Claims] 1. A first current control means that converts an input signal into a current, a second current control means whose current value is controlled by the output of an amplifier, and a current controlled by the second current control means and the first current control means. means for detecting a difference current between the current generated by the current control means 1 and the current generated by the current control means 1; means for negative feedback of the difference current signal to the amplifier;
means for selectively applying an analog input signal and a reference signal to the current control means; a current generated by the first current control means to which the analog input signal is applied; and a current generated by the second current control means. and a system control circuit and digital output means for all the circuits, and applies a reference signal to the first current control means under the control of the system control circuit at an initial point of analog-to-digital conversion; Therefore, the amplifier is controlled so that the current generated by the first current control means and the current controlled by the second current control means are made substantially equal by the means for detecting the difference current and the negative feedback means. Comparison of the current generated by the second current control means which controls the output and the current generated by the second current control means after the completion of this operation and the current generated by the first current control means controlled by the system control circuit and to which an analog input signal is applied. An A/D converter characterized in that the operation is performed by the comparison means, and the comparison result is taken out as a digital output from the digital output means.