JPS634427B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in digital phase control circuits used in separately excited converters.

FIG. 1 shows an overall configuration diagram of a separately excited converter. In FIG. 1, 1 is an AC bus, 2 is a rectifier transformer, 3 is a transformer, 31 to 36 are control rectifier elements constituting the converter 3, and 31 is U
phase, 32 is V phase, 33 is W phase, 34 is X phase, 35
is called a Y-phase controlled rectifying element, and 36 is called a Z-phase controlled rectifying element. 5 is a load, 6 is a potential transformer PT, 7 is a control device that performs current control, etc., and 8 is a phase control circuit.

In the separately excited converter, the three-phase AC waveform obtained from the instrument transformer 6 and the control amount obtained from the control device 7 are input to the phase control circuit 8, and the firing timing for each control rectifier is determined. ing. Conventionally, various control methods have been used for the phase control circuit 8, but analog methods, such as the AC/DC superposition method, have large firing angle control errors, and when the control device 7 is configured with a computer, etc. However, there are disadvantages such as the need for a digital-to-analog conversion circuit.

Various systems have been proposed for circuits that digitally control the phase. The circuit configuration becomes complicated because it is provided for each. Further, in the system using only one comparator, there were problems such as a complicated firing phase discrimination circuit for determining which phase the firing pulse should be applied to.

The present invention has been made in consideration of the above points, and
A simple and high-performance digital phase control circuit is provided by using one comparator to compare the digital control amount and the phase reference signal and configuring the ignition phase discrimination circuit with one lead-on memory. .

FIG. 2 is a block diagram showing the configuration of a digital phase control circuit according to an embodiment of the present invention. In Figure 2, 9 is a synchronization signal detection circuit that outputs a frequency multiplied signal synchronized with a three-phase AC waveform, and is a phase continuous comparison phase-locked loop or a normal
Consists of a PLL circuit.

Reference numeral 10 designates a frequency dividing circuit for frequency dividing the output of the synchronizing signal detection circuit 9, and reference numeral 11 designates a first n-ary (in this embodiment, hexadecimal) counter which receives the most significant bit of the frequency dividing circuit 10 as an input. Note that the output of the n-ary counter 11 and the output of the frequency dividing circuit 10 are fed back to the synchronization signal detection circuit 9.

Reference numeral 12 denotes a first code conversion circuit that converts the code of a control amount obtained from the control device 7 that performs current control, etc., and 13 a second code conversion circuit that converts the code of the upper few bits of this control amount. 14 is the first
This is a comparator that compares the output of the code conversion circuit 12 and the output of the frequency divider circuit 10, and sends out a logic "1" output when the output of the frequency divider circuit 10 becomes large.

15 is an ignition phase discrimination circuit composed of a read-only memory (ROM), etc., and the first n-ary counter 1
1, the output a of the second n-ary counter 16, which will be described later, and the output of the first code conversion circuit 12,
The output of the comparator 14 is input, and when a condition described later is satisfied, the output signal b is set to logic "1" and the output corresponding to the phase to which the ignition pulse is to be applied is set to logic "1".

16 is a signal a obtained from the ignition phase discrimination circuit 15
The second n-ary counter 17 which receives as input is a one-shot circuit that generates a pulse of a constant width in accordance with the firing command for each phase obtained from the firing phase discrimination circuit 15. Also, among the signal lines in the figure, the band-shaped lines indicate that digital signals of several bits are transmitted.

FIG. 3 is a diagram for explaining the operation of the first and second code conversion circuits, and FIG. 4 is an overall term chart, and the operation of the present invention will be explained using these.

To simplify the explanation, the controlled object is assumed to be a 6-phase bridge externally excited converter, the digital control amount obtained from the control device 7 is 10 bits, the frequency of the 3-phase AC waveform is f ₀ , and the synchronous signal detection circuit 9 obtains the digital control amount of 10 bits. Assume that the multiplied signal is 6×2 ⁸ ×f ₀ [Hz].

The synchronizing signal detection circuit 9 is composed of a PLL circuit, etc., and the multiplied signal is frequency-divided by the frequency dividing circuit 10 into ^1/28 , that is, an 8-bit signal, and the reference θ _L (the 8-bit signal) for the firing angle phase is used. Figure 4 b). The most significant bit of the frequency divider circuit 10 is applied to a first n-ary counter 11 and counted. The output of the first n-ary counter 11 is assumed to be θ _H (FIG. 4c).

As is clear from Fig. 4 b and c, the outputs θ _H and θ _L
Based on the signal, it is possible to determine which phase of the AC waveform (RT line voltage) shown in FIG. 4a. That is, the outputs θ _L and θ _H can be used as phase reference signals.

Next, the control amount sent from the control device 7 will be explained.

Control amount (cosα) corresponding to each firing angle from 0 to 180°
When expressed as a 10-bit binary number, the value is shown in "Binary representation of input" in Figure 3a. However, the range of firing angle α where the output voltage of converter 3 becomes negative is 90°~
For 180°, use two's complement. The first code conversion circuit 12 converts the control amount cosα into α in order to linearize the current control system. At the same time, it is possible to compare 6 phases with one comparator.
60°, 60° to 120°, and 120° to 180° are frequency dividing circuit 1, respectively.
The code is converted to correspond to the output θ _L of 0, that is, as shown in FIG. 3b, and this value is set as α _L. In addition, the second code conversion circuit 13 changes the upper two bits of the control amount (cosα) to "1" for 0° to 60°, "2" for 60° to 120°, and "2" for 120° to 180°, as shown in Table 3. Convert the code so that it becomes "3" at °, and let this value be _αH .

The second code conversion circuit can be easily configured with several AND circuits, OR circuits, and an inversion circuit, and the first code conversion circuit uses a ROM to address the value of the "input binary representation". It can be easily configured by using the contents of each address as the output code.

In the comparator 14, the output θ _L of the frequency dividing circuit 10
The value of is compared with the value of the output α _L of the first code conversion circuit 12, and when θ _L ≧ α _L , a logic “1” is output. The firing phase determination circuit 15 receives the output θ _H of the first n-ary counter 11 , the output α _H of the second code conversion circuit 13 , the output of the comparator 14 , and the output N of the second n-ary counter 16 . If any of the following conditions (1) to (3) are satisfied, b is set to "1", the value of the second n-ary counter is counted, and the second
The phase to be fired is determined by the value N of the n-ary counter 16.

(N=θ _H −α _H )∩(θ _L ≧α _L ) …(1) N=θ _H −α _H −1 …(2) N=θ _H −α _H −2 …(3) Conditional expression ( Case 1) is a case of normal ignition control, and conditional expressions (2) and (3) are a case of compensating ignition control when the ignition angle rapidly advances.

The operation will be explained using the time chart shown in FIG. Figure 4a shows the RT line voltage, Figure 4b
shows the value of θ _L which is the output of the frequency dividing circuit 10 shown in analog form, and FIG. 4c shows the value of the first n-ary counter 1
4d shows the firing angle _α , FIG. 4e shows the output _αH of the second code conversion circuit 13, and FIG. 4f shows the firing angle α. FIG. 4g shows the output N of the n-ary counter 16, and FIG. 4g shows the output a of the firing angle discriminating circuit 15.

First, when the value N of the second n-ary counter 16 is "5", the N phase and the Y phase are fired. α = 45°, and if θ _L ≧ α _L , then θ _H = 0, α _H = 1
Therefore, θ _H −α _H =−1. Here, the counter 16 is controlled in hexadecimal, so if it is negative, 6
Since we consider by adding θ _H −α _H =5=N,
Equation (1) is established, the signal a becomes "1", changes to N=0, a pulse is output to the U phase, and the Y phase and U phase are fired.

Similarly, each time the conditional expression is satisfied, the signal a
becomes "1", and the value of the second n-ary counter 16 increments by 1 to sequentially control the ignition phase.

When the ignition phase detection circuit 15 is configured with ROM, the input signal specifies the address, so it actually uses equations (1) and (2).
There is no need to calculate equation (3); the output bit signal a is set to "1" only at addresses where the condition is satisfied, and the value of N, which is the output of the second hexadecimal counter 16, is indicated. All you have to do is write to the ROM so that the bit corresponding to each phase is set to "1" in the address. In the one-shot circuit 17, the output of the ROM is made into one-shot so as to have a pulse width suitable for the actual ignition pulse.

That is, in the digital phase control circuit of the present invention, the phase reference is divided into θ _H and θ _L and the firing angle control amount is divided into α _H and α _L , only θ _L and α _L are compared, and the current value is determined by θ _H. The area of the firing angle control amount is determined based on the actual value α _H of the phase reference, and the firing timing and firing phase are determined, and this determination is made by a type of pattern recognition using the ROM address. A high-performance digital phase control circuit can be constructed with a very simple configuration.

Also, if you use P-ROM instead of ROM,
You can easily change the conditions, and whether the output pulse is a single pulse method or a double pulse method is determined by the bit corresponding to the Z phase in the ROM contents, for example, if the U phase and Z phase are fired. This can be easily changed by setting only "1" to "1" or setting the bits corresponding to the U phase and Z phase to "1".

Furthermore, if θ _L and α _L are set in 30° increments, the first and second n-ary counters 11 and 16 are decimal counters, and a ROM with an output of 13 bits or more is used, 12
Batch control of all phases can also be easily achieved.

In the above explanation, the digital control amount obtained from the control device 7 is expressed in two's complement representation, but even if it is in other codes such as absolute value and sign bit representation, the configuration of the second code conversion circuit 13 to configure the first code conversion circuit 12.
It can be easily configured by rewriting the contents of the ROM.

As explained above, according to the digital phase control circuit of the present invention, the phase reference is divided into θ _L and θ _H ,
By dividing the digital control amount into α _H and α _L and comparing θ _L and α _L with a comparator, and by configuring the ignition phase discrimination circuit with a read-only memory, etc., only one comparator is required. An ignition phase discrimination circuit with a simple configuration is sufficient, and a high-performance digital phase control circuit can be easily obtained no matter what code the digital control amount is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a conventional separately excited converter, FIG. 2 is a block diagram showing the configuration of the digital phase control circuit of the present invention, and FIG. 3 is a block diagram showing the configuration of the first and second code conversion circuits. FIG. 4 is a time chart for explaining the operation of the circuit shown in FIG. 2. DESCRIPTION OF SYMBOLS 1... AC bus, 2... Rectifier transformer, 3... Converter, 31, 32, 33, 34, 35, 36... Control rectifying element, 5... Load, 6... Instrument transformer, 7... Control device, 8 . . . Phase control circuit, 9 . ...Ignition phase discrimination circuit, 16...Second n-ary counter, 17
...One-shot circuit.

Claims (1)

[Scope of Claims] 1. In a digital phase control circuit for controlling a separately excited multiphase AC converter having a plurality of rectifying elements whose firing angles are controlled, a frequency multiplier synchronized with the voltage phase of the multiphase AC. a synchronous signal detection circuit that obtains a signal; a frequency division circuit that divides the output of the synchronous signal detection circuit; a first n-ary counter that increments every counting period of the frequency division circuit; A control device that provides a digital amount corresponding to a controlled amount, a first code conversion circuit that takes the output of the control device as an address and outputs a stored code corresponding to the address, and an output of the first code conversion circuit. A comparator that compares the output of the frequency divider circuit and generates a logic "1" output when the output of the frequency divider circuit is large, and the upper few bits of the output of the control device are input, and the angle of the firing angle is determined by the input. a second code conversion circuit that outputs a code that defines a range; a second n-ary counter; an output N of the second n-ary counter; an output θ _H of the first n-ary counter; Using the output α _H of the code exchange circuit No. 2 and the output of the comparator as input, one of the following equations (1) to (3) was found (N=θ _H −α _H )∩(θ _L ≧ α _L ) …(1) N=θ _H −α _H −1 …(2) N=θ _H −α _H −2 …(3) When the logic “1” is output to the second n-ary counter and the output N of the second n-ary counter
A digital phase detector comprising: an ignition phase discrimination circuit that determines the rectifying element to be ignited and generates an ignition output based on the ignition phase discrimination circuit; and a circuit that shapes the waveform of the ignition output of the ignition phase discrimination circuit. control circuit.