JPS6343995B2 - - Google Patents
Info
- Publication number
- JPS6343995B2 JPS6343995B2 JP510281A JP510281A JPS6343995B2 JP S6343995 B2 JPS6343995 B2 JP S6343995B2 JP 510281 A JP510281 A JP 510281A JP 510281 A JP510281 A JP 510281A JP S6343995 B2 JPS6343995 B2 JP S6343995B2
- Authority
- JP
- Japan
- Prior art keywords
- diode
- voltage
- secondary winding
- rectifier
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004804 winding Methods 0.000 claims description 32
- 238000003079 width control Methods 0.000 claims description 5
- 238000009499 grossing Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/06—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
- H02M7/062—Avoiding or suppressing excessive transient voltages or currents
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Rectifiers (AREA)
- Control Of Electrical Variables (AREA)
Description
【発明の詳細な説明】
本発明はダイオードまたはスイツチングトラン
ジスタなどの整流素子よりなる整流回路と、その
出力に接がるチヨークコイルに設けたバイアス用
２次巻線に、整流素子の導通サイクル時のみ電流
を流すようにした平滑回路とよりなる整流装置に
係り、導通サイクルのときは直流電流を流してチ
ヨークコイルの磁心の飽和により、低インピーダ
ンスとし、不導通サイクルのときは磁心の不飽和
により高インピーダンスとして、整流素子に逆電
流が流れないようにするにある。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a rectifier circuit consisting of a rectifier element such as a diode or a switching transistor, and a bias secondary winding provided in a choke coil connected to the output thereof. This is a rectifier device consisting of a smoothing circuit that allows current to flow.During a conduction cycle, DC current is applied to saturate the magnetic core of the chiyoke coil, resulting in a low impedance, and during a non-conducting cycle, the unsaturation of the magnetic core creates a high impedance. The purpose is to prevent reverse current from flowing through the rectifier.
従来通信機や電子機器の電源回路は第１図に示
すようにトランスT1の１次巻線N1に印加したパ
ルス電圧、たは交番電圧により２次巻線N2に生
じた誘起電圧をダイオードD1で整流し、コンデ
ンサC1により平滑し、負荷抵抗RLに直流電圧が
供給される。これらの回路においては、整流され
た電圧はダイオードD1の順方向の抵抗分による
電圧降下分だけ損失として消費される。たとえば
直流出力電圧12Vで、負荷電流が10Aにおいて、
ダイオードD1の電圧降下を1.5Vとしたとき、ダ
イオードD1での損失は電力では10A×1.5V＝
15Wになり、出力電力12V×10A＝120Wに対し
て12.5％にも達する。したがつてこの整流素子ダ
イオードD1における電圧降下を少なくするため、
電圧降下が0.6V程度のダイオードに代るシヨツ
トキーダイオード整流素子として用いられること
もある。 Conventional power supply circuits for communication equipment and electronic equipment, as shown in Figure 1, use a pulse voltage or alternating voltage applied to the primary winding N 1 of a transformer T 1 to generate an induced voltage in the secondary winding N 2 . The DC voltage is rectified by the diode D1 , smoothed by the capacitor C1 , and is supplied to the load resistor R L. In these circuits, the rectified voltage is consumed as a loss by the voltage drop due to the forward resistance of the diode D1 . For example, when the DC output voltage is 12V and the load current is 10A,
When the voltage drop of diode D 1 is 1.5V, the loss in diode D 1 is 10A x 1.5V =
The output power is 15W, which is 12.5% of the output power of 12V x 10A = 120W. Therefore, in order to reduce the voltage drop in this rectifier diode D1 ,
It is sometimes used as a Schottky diode rectifier in place of a diode with a voltage drop of about 0.6V.
また整流素子としてダイオードの代りに第２図
に示すようにトランジスタQ1を直列に接続する
ことによつてコレクタ・エミツタ間の飽和電圧は
負荷電流10Aで0.5V以下の損失の少ないものとす
ることもできる。 In addition, by connecting a transistor Q1 in series as shown in Figure 2 instead of a diode as a rectifying element, the saturation voltage between the collector and emitter can be made low loss to 0.5V or less at a load current of 10A. You can also do it.
しかしダイオードやトランジスタのような整流
素子には素子が導通状態でないときは、巻線N2
に誘起された逆方向の電圧が印加される。すなわ
ち第１図においてはダイオードD1のアノードに
負電位、カソードに正電位が、また第２図におい
てはトランジスタのエミツタに正電位、コレクタ
に負電位が印加される。しかしシヨツトキーダイ
オードでも一般トランジスタでも、この逆電圧が
素子の持つている規定値以上になると、急に逆電
流が流れて不導通でなくなる。たとえば通常シヨ
ツトキーダイオードでは40V、一般のトランジス
タでは10Vであり、また第１図ならびに第２図の
場合はトランスT1の２次巻線N2には直流出力電
圧の数倍の電圧値をもつ逆電圧が誘起されるの
で、シヨツトキーダイオードでは出力電圧5Vに
使えても出力電圧15Vには使えないことにもな
る。またトランジスタではさらに小さい出力電圧
の場合しか使えない欠点がある。 However, for rectifying elements such as diodes and transistors, when the element is not conducting, the winding N 2
A voltage induced in the opposite direction is applied. That is, in FIG. 1, a negative potential is applied to the anode of the diode D1 and a positive potential to the cathode, and in FIG. 2, a positive potential is applied to the emitter of the transistor, and a negative potential is applied to the collector. However, in both Schottky diodes and general transistors, when this reverse voltage exceeds the specified value of the device, a reverse current suddenly flows and the device ceases to be non-conducting. For example, the voltage is usually 40V for a Schottky diode and 10V for a general transistor, and in the case of Figures 1 and 2, the voltage several times the DC output voltage is applied to the secondary winding N2 of the transformer T1 . Since a reverse voltage is induced, a Schottky diode can be used for an output voltage of 5V, but cannot be used for an output voltage of 15V. Another disadvantage of transistors is that they can only be used for smaller output voltages.
本発明は従来のかかる欠点を除き、整流回路の
出力に接続される平滑回路用チヨークコイルに２
次巻線を施し、整流素子の順方向電圧のときはダ
イオードを通じて直流電流を２次巻線に流し、チ
ヨークコイルの磁心を飽和させてインピーダンス
を下げて損失を少くし、逆方向電圧ではダイオー
ドを通じて直流電流の流れないときは磁心の不飽
和によりインピーダンスを高くし、整流素子に高
い逆電圧が印加するのを防止するものである。 The present invention eliminates such drawbacks of the conventional technology and provides two coils for smoothing circuits connected to the output of the rectifier circuit.
A secondary winding is applied, and when the forward voltage of the rectifying element is present, direct current is passed through the diode to the secondary winding, saturating the magnetic core of the chiyoke coil to lower impedance and reduce loss, and when the voltage is in the reverse direction, direct current is passed through the diode to the secondary winding. When no current flows, the impedance is increased due to unsaturation of the magnetic core, thereby preventing high reverse voltage from being applied to the rectifying element.
第３図は本発明の一実施例を示し平滑回路用チ
ヨークコイルL1の１次巻線n1の上にバイアス用２
次巻線n2を施し、ダイオードD1と同方向のダイ
オードD2および抵抗R1を通じてトランスT1の２
次巻線N2に誘起される電圧を加える。いまダイ
オードD1の導通方向にトランスT1の２次巻線N2
に誘起された電圧によつて負荷直流電流Ｉが流れ
ると同時に、バイアス用２次巻線n2に直流電流ｉ
が流れる。チヨークコイルL1の１次巻線n1と２次
巻線n2との間にn2≫n1の関係があると、それぞれ
の巻線に流れる直流電流Ｉ，ｉとの間にｉ≪Ｉの
関係が得られる。したがつて直流電流ｉがチヨー
クコイルL1の磁心を飽和させると、チヨークコ
イルL1のインピーダンスは零に近くなり、巻線n1
の直流抵抗分だけとなり、負荷回路の損失が少な
くなる。 FIG. 3 shows an embodiment of the present invention, and a bias coil 2 is connected to the primary winding n 1 of the smoothing circuit coil L 1 .
The next winding n 2 is applied and the 2 of the transformer T 1 is connected through the diode D 2 and the resistor R 1 in the same direction as the diode D 1.
Apply the voltage induced in the next winding N 2 . Now the secondary winding N 2 of the transformer T 1 is connected in the conduction direction of the diode D 1
At the same time, the load DC current I flows due to the voltage induced in the bias secondary winding n2 .
flows. If there is a relationship n 2 ≫ n 1 between the primary winding n 1 and the secondary winding n 2 of the choke coil L 1 , then i ≪ I between the direct current I, i flowing through each winding. The following relationship is obtained. Therefore, when the DC current i saturates the magnetic core of the chiyoke coil L1 , the impedance of the chiyoke coil L1 becomes close to zero, and the winding n1
This reduces the loss in the load circuit.
また逆電圧が印加されたときはダイオードD1
に不導通であり、２次巻線n2に接がるダイオード
D2も不導通となり、直流電流ｉは２次巻線n2に
流れないので、チヨークコイルL1の磁心は飽和
せず高インピーダンスを持つようになる。したが
つてダイオードD1には直接大きな逆電圧は印加
されないので、逆耐圧の低いダイオードやトラン
ジスタなどを整流素子として使うこともできるよ
うになる。 Also, when a reverse voltage is applied, the diode D1
A diode that is non-conducting and in contact with the secondary winding n 2
D2 also becomes non-conductive, and the direct current i does not flow to the secondary winding n2 , so the magnetic core of the chiyoke coil L1 is not saturated and has a high impedance. Therefore, since a large reverse voltage is not directly applied to the diode D1 , a diode or a transistor with a low reverse withstand voltage can be used as a rectifying element.
第４図は本発明の他の実施例を示し、トランス
T1の１次巻線N1に加えられたパルス信号の２次
巻線N2での出力をスイツチング用トランジスタ
Q1によりスイツチングし、さらに第５図に示す
ようにトランスT1の２次側出力電圧V1のパルス
幅T0とトランジスタQ1の出力電圧V2のパルス幅
τ0との間にT0＞τ0となるようなパルス幅制御駆動
回路Ｐを設け、τ0／T0のデユーテイ率を可変と
する。さらにチヨークコイルL1にはバイアス用
２次巻線n2を施し、トランジスタQ1の出力電圧
によりダイオードD1、抵抗R1を通じて２次巻線
n2に直流電流を流して、前述したと同様に損失の
少い平滑回路ができる。またパルス幅制御駆動回
路Ｐの制御によつてデユーテイ率を可変とすると
ダイオードD1で整流された可変直流電流が２次
巻線n2に流れるので、飽和電流値は変わり、した
がつてインピーダンスも変わる。さらに第４図の
両波整流用ダイオードD2の整流平滑回路につな
がる第２のチヨークコイルL2にも同様に２次巻
線を施して直流電流を流してインピーダンスを小
さくすることもできる。また飽和電流は必ずしも
例示したようにトランスT1と関連して流すこと
もなく、トランジスタQ1の導通時に２次巻線n2
に直流電流が流れるようにトランジスタQ1の導
通サイクルと同期する方法をとればよい。 FIG. 4 shows another embodiment of the present invention, in which a transformer
A switching transistor outputs the pulse signal applied to the primary winding N1 of T1 at the secondary winding N2 .
As shown in FIG . _ _ _ A pulse width control drive circuit P is provided such that >τ 0 and the duty rate of τ 0 /T 0 is made variable. Furthermore, a secondary winding n 2 for bias is applied to the chiyoke coil L 1 , and the output voltage of the transistor Q 1 connects the secondary winding through the diode D 1 and the resistor R 1 .
By passing a direct current through n2 , a smoothing circuit with low loss can be created in the same way as described above. Furthermore, when the duty rate is made variable under the control of the pulse width control drive circuit P, the variable DC current rectified by the diode D1 flows to the secondary winding n2 , so the saturation current value changes and the impedance also changes. change. Further, it is also possible to similarly provide a secondary winding to the second choke coil L 2 connected to the rectifying and smoothing circuit of the double-wave rectifying diode D 2 shown in FIG. 4 to flow a direct current to reduce the impedance. Further, the saturation current does not necessarily flow in connection with the transformer T1 as illustrated, but when the transistor Q1 is conductive, the saturation current flows through the secondary winding n2.
What is necessary is to use a method that synchronizes with the conduction cycle of the transistor Q1 so that a direct current flows through the transistor Q1 .
以上に述べたように本発明は平滑回路のチヨー
クコイルに２次巻線を施し、整流素子の導通サイ
クルに直流電流を流してチヨークコイルの磁心の
飽和値によつてインピーダンスを低くして損失を
少くし、不導通時は直流電流を流さず、インピー
ダンスを高くして、高い逆電圧によつて整流素子
に逆電流が流れないようにすることができる。な
お以上の説明ではトランスT1の１次側にパルス
電圧が入力される場合の例について述べたが、特
にパルス電圧に限らず、正弦波電圧でも同様であ
る。 As described above, the present invention provides a secondary winding to the smoothing circuit's chiyoke coil, passes a direct current during the conduction cycle of the rectifier element, and lowers the impedance and loss by the saturation value of the magnetic core of the chiyoke coil. When non-conducting, direct current does not flow and the impedance is increased to prevent reverse current from flowing through the rectifying element due to a high reverse voltage. In the above description, an example has been described in which a pulse voltage is input to the primary side of the transformer T1 , but the present invention is not limited to a pulse voltage, and the same applies to a sine wave voltage.
第１図は従来のダイオードを用いた基本的整流
回路、第２図は従来のトランジスタを用いた整流
回路、第３図は本発明によるダイオードを整流素
子とした整流回路図、第４図はスイツチングトラ
ンジスタを用いた本発明による整流回路図、第５
図は本発明の整流装置に用いたパルス幅制御駆動
回路により制御される入力および出力の電圧波形
図である。
図において D1，D2：ダイオード、O1：トラ
ンジスタ、L1，L2：チヨークコイル、n1：１次
巻線、n2：バイアス用２次巻線、T1：トランス、
N1：１次巻線、N2：２次巻線、R1：抵抗、C1：
コンデンサ、RL：負荷抵抗、Ｐ：パルス幅制御
駆動回路。
Figure 1 is a basic rectifier circuit using a conventional diode, Figure 2 is a rectifier circuit using a conventional transistor, Figure 3 is a rectifier circuit diagram using a diode according to the present invention as a rectifier, and Figure 4 is a switch. Rectifier circuit diagram according to the present invention using a switching transistor, No. 5
The figure is a diagram of input and output voltage waveforms controlled by the pulse width control drive circuit used in the rectifier of the present invention. In the figure, D 1 , D 2 : diode, O 1 : transistor, L 1 , L 2 : chiyoke coil, n 1 : primary winding, n 2 : secondary winding for bias, T 1 : transformer,
N 1 : Primary winding, N 2 : Secondary winding, R 1 : Resistance, C 1 :
Capacitor, R L : Load resistance, P: Pulse width control drive circuit.
Claims (1)
て、ダイオードまたはトランジスタの整流素子、
またはパルス幅制御により断続させるスイツチン
グ用トランジスタ素子の導通時にのみ直流電流が
流れるバイアス用２次巻線を施したチヨークコイ
ルを前記素子に接続してなり、前記直流電流の可
変により、前記チヨークコイルのインピーダンス
を可変ならしめることを特徴とする整流装置。1 In a rectifier that obtains a DC output from an AC input, a diode or transistor rectifier,
Alternatively, a chiyoke coil having a bias secondary winding through which a direct current flows only when a switching transistor element is turned on and off by pulse width control is connected to the element, and by varying the direct current, the impedance of the chiyoke coil can be adjusted. A rectifying device characterized by being variable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP510281A JPS57122671A (en) | 1981-01-19 | 1981-01-19 | Rectifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP510281A JPS57122671A (en) | 1981-01-19 | 1981-01-19 | Rectifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57122671A JPS57122671A (en) | 1982-07-30 |
| JPS6343995B2 true JPS6343995B2 (en) | 1988-09-02 |
Family
ID=11601999
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP510281A Granted JPS57122671A (en) | 1981-01-19 | 1981-01-19 | Rectifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57122671A (en) |
-
1981
- 1981-01-19 JP JP510281A patent/JPS57122671A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57122671A (en) | 1982-07-30 |
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