JPS6343526Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to a phase difference control device that sets and holds the phase difference (analog quantity) between at least two signals in digital form and generates an output signal having a desired phase difference by controlling it with an on/off signal.

[Conventional technology]

When setting and maintaining the phase difference between two signals in digital form, a clock signal is appropriately supplied from a clock signal generator to a pair of digital phase difference holding circuits forming a phase difference holding section. After the predetermined phase difference is set, the same number of clock signals are continuously supplied to both digital phase difference holding circuits,
Although the contents of each digital phase difference holding circuit change from moment to moment, both digital phase difference holding circuits operate in a circular manner, so the difference in content does not change and the phase difference is maintained. .

[Problem that the invention attempts to solve]

The general control of the phase difference, including the setting, maintenance and modification of such phase difference, should be easily operable with on/off signals, i.e. manually or in response to the width of a remote pulse signal. It is desirable to do so.

Therefore, the main purpose of this invention is to set and maintain the phase difference (analog amount) between two signals in digital form, operate it by on/off signals,
That is, the present invention provides a phase difference control device with a simple configuration that can be easily operated manually or by a remote pulse signal, and is particularly useful when extracting at least two signals having the same period and different phases. An object of the present invention is to provide a phase difference control device that can mutually adjust phase differences.

Another object of the present invention is to provide a phase difference control device with a simple configuration that allows the speed of the control operation to be easily selected and adjusted when performing the phase difference control.

[Means for solving problems]

In order to achieve the above object, the phase difference control device of the present invention connects a clock signal generator via an input logic gate to a pair of digital phase difference holding circuits having a frequency division function and forming a phase difference holding section. The outputs from the portions of the digital phase difference holding circuits having equal frequency division ratios, that is, the first outputs, are respectively coupled to a pair of output terminals of the phase difference control device itself, and the first output of one digital phase difference holding circuit A phase difference holding circuit is provided between the output and the input logic gate,
The phase difference holding circuit is provided with an impulse generation circuit, a control logic gate, and a manual or remote control switch, and the control logic gate is controlled by the manual or remote switch to supply a clock stop signal from the impulse generation circuit to the input logic gate. and correspondingly stop the supply of the clock signal from the clock signal generator to one of the digital phase difference holding circuits, thereby controlling the phase difference between the output signals generated at the pair of output terminals. It is characterized by having been configured.

Furthermore, in order to achieve the above object, the phase difference control device of the present invention controls the phase difference at various control speeds by selecting the number of times per unit time or the duration of supply of the clock stop signal supplied from the impulse generating circuit. It is characterized by being configured so that it can be adjusted.

〔Example〕

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

In the embodiment of the phase difference control device of the present invention shown in FIG. 12 is connected to the output terminal of the control logic gate 18, and the input logic gate 14 is connected to the output terminal of the control logic gate 18.
is connected to the output terminal of control logic gate 16, and the output terminals of input logic gates 12 and 14 are connected to the input terminals of digital phase difference holding circuits or frequency divider circuits 20 and 22, respectively. The two phase difference holding circuits 20 and 22 form a phase difference holding section. Phase difference holding circuit 20
and 22 where the frequency division ratio is equal, for example, the location where the frequency division ratio is maximum, are coupled to the output terminals 24 and 26 of the phase difference control device, respectively, and the output signals e ₁ and e are sent to these output terminals 24 and 26. ₂ occur respectively. Further, the output of the phase difference holding circuit 22 is coupled to an input terminal of an impulse generating circuit 28, whose output terminal is connected to the control logic gates 16 and 1.
8 and control logic gate 1.
The other input terminal of control logic gate 18 is connected to switch 32, and the other input terminal of control logic gate 18 is connected to switch 32.
Connect to 0. These switches 30 and 32
can be operated manually or by a remote signal to switch to a position that provides a logic 0'' signal or a logic 1'' signal. In the first embodiment, NAND gates are used as the logic gates 12 to 18, and the phase difference holding circuit (or frequency dividing circuit) 20
It is preferable to use a counter circuit for and 22, and use a differential circuit for the impulse circuit 28.

The operation of the embodiment shown in FIG. 1 will be explained below.

Clock pulses from clock generator 10 reach phase difference holding circuits 20 and 22 via input logic gates 12 and 14. In this case, switches 30 and 32, which can be operated manually or by remote signals, will have logic 0'' signal side contacts 30a and 32a if no phase difference control is provided.
They are located in contact with each other. Therefore, since the clock stop signal from the impulse generating circuit 28 operated by the output signal _e2 of the phase difference holding circuit 22 is blocked by the control logic gates 16 and 18, the clock stop signal from the impulse generating circuit 28 operated by the output signal e2 of the phase difference holding circuit 22 is blocked by the control logic gates 16 and 18. On the other hand, the clock pulses are simultaneously supplied from the clock generator 10, the contents of the phase difference holding circuits 20 and 22 do not change relatively, and the difference is constant. In this case, the phase difference controller periodically or cyclically maintains a certain phase difference between the output signals e ₁ and e ₂ corresponding to a certain difference between the contents of the phase difference holding circuits 20 and 22. Works in format.

Next, when controlling the phase difference, one of the switches 30 and 32, which can be operated manually or by a remote signal, is connected to the logic 1'' signal side contact 30.
b or 32b. In this case, either one of the control logic gates 16 and 18 passes the clock stop signal from the impulse generation circuit 28, so the clock stop signal reaches the input logic gate 12 or 14, and the phase difference holding circuit 20 receives the clock stop signal.
Alternatively, the supply of clock pulses to clock 22 is prevented only during the connection time of the clock stop signal. Correspondingly, the content of only one of the phase difference holding circuits 20 and 22 changes, and the content of the other remains fixed and does not change, so the relative difference between the contents of the two changes,
The phase difference between the output signals e ₁ and e ₂ will change. In that case switch 30 or 32 is set to logic again.
0'' signal side contacts 30a or 32a, the clock stop signal from the impulse generating circuit 28 is output to the control logic gates 16 and 1.
8. Therefore, since the clock pulses are simultaneously supplied to the phase difference holding circuits 20 and 22 via the input logic gates 12 and 14, the newly set phase difference is maintained in the same circular manner as previously described for phase difference holding. It is held in phase difference holding circuits 20 and 22.

A desired phase difference can be easily obtained by repeating the above-described operations as necessary.

That is, in the present invention, the phase difference holding circuits 20 and 22 each output signals having the same period but different phases using the clock pulses output from the common clock generator 10, and the phase difference between these signals is converted into the respective phases. Phase difference holding circuit 20
and 22 can be easily realized with a simple circuit configuration. Particularly, in the phase difference control device of the present invention, the output signals of one of the phase difference holding circuits 20 and 22 are used to operate the impulse generation circuit 28, thereby easily synchronizing the signals for controlling the phase difference. Moreover, this impulse generating circuit 2
By selectively supplying the clock stop signal output from the phase difference holding circuit 8 to the phase difference holding circuits 20 and 22, the phase of the output signal of each phase difference holding circuit 20 and 22 can be shifted in a certain direction. Since the configuration is simplified and the phase difference holding circuits 20 and 22 can be controlled mutually, there is an advantage that the lead or lag of the phase difference of the output signal and the adjustment of the magnitude thereof can be easily achieved. can get.

It goes without saying that the phase difference can be controlled by using either of the output signals of the phase difference holding frequency dividing circuits 20 and 22 as input to the impulse generating circuit 28.

In the embodiment shown in FIG. 1, the phase difference is controlled at a single speed, but FIGS. 2 and 3 show embodiments in which the phase difference control speed can be adjusted. Second
In the figure and FIG. 3, the same parts as in FIG. 1 are designated by the same reference numerals.

FIG. 2 shows an embodiment in which the control speed of the phase difference is adjusted by selecting the input to the impulse generating circuit 28, and by selecting the frequency division ratio of the phase difference holding circuit via the selection switch 34. By adjusting the number of times the clock stop signal is generated per unit time from the impulse generating circuit 28, the control speed of the phase difference can be adjusted. In this example, in the phase difference holding circuit 22, the output signal taken out from a point with the same large frequency division ratio as the phase difference holding circuit 20 is coupled to the contact 34b, and the output signal is taken out from a point with a smaller frequency division ratio via the conductor 36. Output signal to contact 3
Binds to 4a. Therefore, the selection switch 34
a, a clock stop signal with a small frequency division ratio and therefore a high frequency is supplied from the impulse generating circuit 28 to the logic gate 12 or 14 via the logic gate 16 or 18, and the phase difference holding circuit 20 The phase difference held at and 22 changes rapidly. Similarly, select switch 34 is connected to contact 34.
b, the division ratio is large and therefore a clock stop signal is provided to the input logic gate 12 or 14 at a low frequency and the phase difference changes slowly. In addition, if a larger frequency division ratio at the contact 34b is required, a frequency division circuit (for example, a flip-flop circuit) is installed immediately after the phase difference holding circuit 22.
and connect its output terminal to contact 34b. Generally speaking, if outputs are extracted from other m-1 locations with different frequency division ratios for the phase difference holding circuit 22 and coupled to the input terminal of the impulse generation circuit 28 via the selection switch 34, ,
A total of m types of phase difference control speeds can be obtained.

In FIG. 3, two impulse generation circuits 28 and 38 having different clock stop signal sending times are provided, two types of clock stop signal sending times are set, and the clock stop signal sending times are selected via a selection switch 40. An embodiment will be described in which the phase difference control can be adjusted at two types of speeds by selecting . Note that by providing n-1 other impulse generating circuits having different clock stop signal sending times in parallel, a total of n types of phase difference control speeds can be selected.

[Effect of idea]

As is clear from the foregoing, the present invention provides a simple phase difference control device that can be operated manually or by remote signals. Further, according to the present invention, a phase difference control device having a simple configuration can be obtained, which allows the speed of the control operation to be easily selected and adjusted when controlling the phase difference.

Although the preferred embodiments of the present invention have been described above, it goes without saying that various design changes can be made without departing from the spirit of the present invention.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the phase difference control device according to the present invention, and FIGS. 2 and 3 are circuit diagrams showing two other embodiments of the phase difference control device according to the present invention. 10... Clock generator, 12, 14... Input logic gate, 16, 18... Control logic gate, 2
0, 22... Phase difference holding circuit, 30, 32... Manual or remote control switch, 28, 38... Impulse generation circuit, 24, 26... Output terminal, 3
4, 40... Control speed selection switch.

Claims (1)

[Claims for Utility Model Registration] (1) A clock signal generator is coupled via an input logic gate to a pair of digital phase difference holding circuits having a frequency division function and forming a phase difference holding section, and these digital Outputs from points of the phase difference holding circuit having equal frequency division ratios, that is, first outputs, are respectively coupled to a pair of output terminals of the phase difference control device itself, and the first output and the input of one digital phase difference holding circuit are coupled to a pair of output terminals of the phase difference control device itself. A phase difference control circuit is provided between the logic gates, and the phase difference control circuit is provided with an impulse generation circuit, a control logic gate, and a manual or remote control switch, and the control logic gate is controlled by the manual or remote control switch to control the control logic. By controlling the supply of a clock stop signal from the impulse generation circuit to the input logic gate, and correspondingly stopping the supply of the clock signal from the clock signal generator to one of the digital phase difference holding circuits, 1. A phase difference control device configured to control a phase difference between output signals generated at an output terminal of the device. (2) Utility model registration In the phase difference control device according to claim 1, the phase difference is controlled by selecting the number of times per unit time or the duration of supply of the clock stop signal supplied from the impulse generating circuit. A phase difference control device characterized in that it is configured to be adjustable at various control speeds. (3) Utility model registration In the phase difference control device according to claim 2, the input terminals of the impulse generation circuit are separated from each other in addition to the first output of the one digital phase difference holding circuit via a selection switch. A phase difference control device characterized in that it is configured to be able to couple to outputs from (m-1) locations having different circumferential ratios, and to be able to select a total of m types of phase difference control speeds. (4) Utility model registration In the phase difference control device as set forth in claim 2, (n-1) impulse generating circuits having different clock stop signal sending times are connected to the impulse generating circuit via a selection switch. 1. A phase difference control device characterized in that the phase difference control device is additionally connected in parallel and configured so that a total of n types of phase difference control speeds can be selected. (5) In the phase difference control device according to claim 1, 3, or 4 of the utility model registration claim, the input logic gate and the control logic gate are NAND.
A phase difference control device characterized in that a gate is used, a digital phase difference holding circuit is used as a counter, and an impulse generation circuit is used as a differentiating circuit.