JPS6341313B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inverter circuit used in a switching regulator or the like, and more particularly to an inverter circuit that eliminates malfunctions due to variations in storage time of transistors that are switched in parallel.

Conventionally, there is an inverter circuit shown in FIG. 1, for example, used in a stabilized DC power supply device known as a switching regulator.

In the circuit shown in Fig. 1, after rectifying the AC power supply once with a diode bridge 1, a rectangular pulse signal of a predetermined frequency is applied via an input transformer T1 to turn on and off the transistor Q1.
High frequency transformer T ₂ installed as an emitter load of 1
A smoothed direct current is obtained through the rectifier circuit 2 provided on the secondary side of the rectifier, and the pulse width of the rectangular pulse signal applied to the base of the transistor Q1 is controlled by a control circuit (not shown). , producing a highly stable direct current. Incidentally, as such a circuit system, there are several systems other than the one shown in FIG.

By the way, the capacity of the DC stabilized power supply obtained by the above circuit is determined by the capacity of transistor Q1, and since there is a limit to the capacity of transistor Q1, if you want to increase the capacity, use the method shown in Figure 2. , transistors Q1 and Q2 are connected in parallel as switching transistors, and are driven in parallel by a rectangular pulse signal from the input transformer _T1 .

However, in this way, transistors Q1 and Q2
If they are connected in parallel, unless transistors with matching characteristics are used, the current flowing through each transistor will become unbalanced due to the difference in storage time of each transistor, resulting in an unbalanced state of efficiency. I can't get it to work.

In other words, this storage time occurs because the operation of the transistor depends on minority carriers injected from the base, and due to excessive drive to the base, the charge accumulated in the base remains even after the base signal disappears. However, the transistor continues to operate as if the base were driven, and this state continues until the base stored charge is consumed, and the amount of stored charge usually differs from transistor to transistor. To explain the influence of this storage time on the input/output relationship with reference to FIG. 3A, as shown in FIG.
The input waveform to the base is not faithfully output to the collector, and the pulse width becomes wider by the storage time T _S.

Therefore, as shown in Figure 2, transistors Q1 and Q
In a circuit that drives two transistors in parallel, transistors with uniform storage times are used or a current detection circuit with a regulator is installed to balance the current, but transistors with uniform storage times are expensive. Further, there is a problem in that the provision of a current detection circuit complicates the circuit configuration, leading to a decrease in reliability and an increase in cost.

The present invention was made by focusing on such conventional problems, and it applies a pulse signal to the bases of at least two transistors from an independent secondary winding of an input transformer, and attenuates the base of each transistor. It is an object of the present invention to solve the above-mentioned problems by interconnecting the devices through means.

Hereinafter, the present invention will be explained based on the drawings.

FIG. 4 is a circuit diagram showing an embodiment of the present invention.

First, to explain the configuration, 10 is an input transformer,
A rectangular pulse signal of a predetermined frequency, for example, several tens of kilohertz, is input to the primary winding 11a, and the secondary windings 13a and 13b are provided independently. Transistors Q ₁₀ and Q ₁₂ are active elements for switching, and have the same wattage.
3b are connected to the base via resistors R ₁₀ and R ₁₂ , respectively. High-frequency output transformers 12 and 14 are connected to the emitter sides of transistors Q10 and Q12.
is provided, whose primary windings 15a and 15b are connected to the respective emitters of transistors Q10 and Q12, and whose secondary windings 17b and 17b are connected in parallel and smoothed through a rectifier consisting of diodes D1 and D2. It is connected to a filter 16.

Further, the bases of transistors Q10 and Q12 are connected to each other via a resistor R14.

Next, the operation of the above embodiment will be explained.

DC power is supplied from the terminals 18a and 18b to the switching transistors _Q10 and _Q12 , respectively, and the DC power is supplied to the transistors by a rectangular pulse signal applied to the input transformer 10.
Q ₁₀ and Q ₁₂ are switched on and off to provide intermittent DC to the primary windings of each of the output transformers 12 and 14, and a rectifier and smoothing circuit consisting of diodes D1 and D2 are provided on the secondary side. Filter 1
DC output is obtained through 6. That is, the transistors are connected from the secondary windings 13a and 13b of the input transformer 10 through the resistors _R10 and _R12 , respectively.
Rectangular pulse signals are now applied to the bases of Q ₁₀ and Q ₁₂ at the same time, transistors Q ₁₀ and Q ₁₂ are turned on at the same time, and when the signals from resistors R ₁₀ and R ₁₂ disappear at the fall of the rectangular pulse signal. Switch off.

Here, for example, the base accumulation time (storage time) of transistor Q ₁₀ is equal to that of transistor Q ₁₂
If it is smaller than , then the transistor with short base accumulation time after the rectangular pulse signal falls
Q ₁₀ first becomes O state. In this off state, the point b on the emitter side of the transistor _Q10 is connected to -E from the terminal 18b by the back electromotive force of the transformer 12.
biased by volts, so that the charge stored in the base of transistor Q ₁₂ is transferred from point C → resistor R ₁₄ → point a → Q ₁₀ (base-emitter junction acting as a diode) → point b → transformer 12 Primary winding 15a of transformer 14 → Primary winding 15b of transformer 14 →
The emitter of Q ₁₂ is forced to discharge through the path. This makes the transistor
_Q12 is also turned off at the same time as transistor _Q10 is turned off, and no current imbalance occurs due to a delay in turning off transistor _Q12 .

In this way, the inverter circuit of the present invention does not require selecting transistors with the same storage time or using a complicated circuit to detect and balance the currents of individual transistors. With a simple circuit configuration, transistors Q ₁₀ and Q ₁₂ with different storage times can be used.
can be controlled on and off at the same time.

FIG. 5 shows another embodiment of the present invention using N single inverters, in which the input transformer 10
The secondary winding 13a corresponding to the number N of inverters is
13n are provided independently, and a rectangular pulse signal is simultaneously applied to each of the transistors Q ₁ , Q ₂ , . . . Qn via each of the resistors R16,
Secondary windings of output transformers 20a, 20b...20n provided on the emitter side of transistors _Q1 to Qn are connected in parallel, and DC output is taken out through a rectifier and smoothing filter 16 consisting of diodes _D1 and _D2 . Thus, the bases of the transistors Q ₁ to Qn are connected to each other via their respective resistors R ₀ .

The operation of this embodiment is also similar to that of the embodiment shown in _FIG . ₁ ~
Among Qn, when the transistor with the shortest base storage time, for example transistor _Q1 , turns off first, the other transistors in the on state are The base charge is discharged,
Forced to turn off.

In this way, even if the number of inverters to be driven in parallel increases, the interconnection of the bases of each transistor through the resistor R ₀ allows other transistors to be turned on and off in conjunction with the turning on and off of the transistor with the shortest storage time. Can be turned off.

FIG. 6 shows another embodiment of the present invention using two push-pull inverters. , the rectangular wave pulse signal P′ applied to the transformer 32 is caused by phase inversion.
180° phase difference. The input transformers 22, 32 have two independent sets of secondary windings 22a, 22b and 32.
a, 32b, and a resistor R22 or R
32 through each of the transistors Q ₂₀ , Q ₂₁
Alternatively, Q ₃₀ and Q ₃₁ are controlled to be turned on and off alternately. The output transformers 40, 42 are equipped with a center point tap, and the output transformer 40 has transistors Q ₂₁ ,
The output transformer 42 receives push-pull drive from transistors Q ₃₁ and push-pull drive from transistors Q ₂₀ and Q ₃₀ , the secondary sides of the output transformers 40 and 42 are connected in parallel, and a rectifier consisting of diodes D ₁ and D ₂ And it is taken out as a DC output through a smoothing filter 16. In addition, to prevent current imbalance due to differences in storage time, the bases of transistors Q ₂₀ and Q ₂₁ are connected via resistor R ₂₀ , and the bases of transistors Q ₃₀ and Q ₃₁ are also connected to resistor R ₃₀ . Connected via.

Therefore, the transistors Q ₂₀ and Q ₂₁ are turned on during the half cycle during which the rectangular pulse signal P rises.
Regarding the transistors Q ₃₀ and Q ₃₁ which are turned on during the half cycle during which the rectangular pulse signal P' rises, the other transistors are turned off in response to the turning off of the transistor with the smaller storage time. In response to turning off a transistor with a short storage time, other transistors are also turned off at the same time, so that current imbalance does not occur.

FIG. 7 shows another embodiment of the present invention using three push-pull inverters, and the input transformer and output side rectifier circuit are omitted.

In this way, when the push-pull inverter has three or more circuits, the transistors Q ₂₀ to Q ₂₂ or the transistor Q ₃₀
~ By interconnecting the bases of each transistor in a so-called star connection from the base of Q ₃₂ through the resistor R ₂₀ or R ₃₀ , the transistor
Transformers 40 and 4 are connected with intermittent current depending on the transistor with the shortest storage time among Q ₂₀ to Q ₂₂ or transistors Q ₃₀ to _{Q 32} , respectively.
2 and 44 can be push-pull driven in parallel.

Fig. 8 shows another embodiment of the present invention using two circuits of inverters known as a so-called half-bridge type, in which the power supply voltage is divided using capacitors C ₁ and C ₂ and a input transformer 50,
A rectangular pulse signal P and a phase-inverted pulse signal P' are applied to 52, and the transistors Q ₅₀ ,
By alternately controlling the combination of Q ₅₁ and Q ₅₂ and Q ₅₃ on and off, the output transformers 54 and 56 are driven in parallel, and half of the DC voltage applied between terminals 18a and 18b is applied to the secondary side of the output transformers 54 and 56. In order _{to prevent} current imbalance due to differences in storage time, _there is _a I am trying to connect it through a resistor _R50 .

FIG. 9 shows _another embodiment of the present invention using three half-bridge _type inverter circuits. This is an additional half-bridge having a transformer 60. When three or more half-bridge circuits are provided in this way, transistors Q ₅₀ , which are controlled on and off simultaneously, are added.
By connecting the bases of Q ₅₁ , Q ₅₄ or Q ₅₂ , Q ₅₃ , and Q ₅₅ to each other through the resistor R ₅₂ in a so-called star connection, the storage time of the transistors whose bases are interconnected can be reduced. In response to the transistor with the smallest value, other transistors can be simultaneously turned off.

FIG. 10 shows another embodiment of the present invention using two inverter circuits known as a so-called full bridge, in which transistors Q ₆₀ , Q ₆₁ , Q ₆₂ ,
A bridge is formed at Q ₆₄ , and the rectangular pulse signal P and its inverted signal P' applied to the transformers 60 and 62 with center taps cause the transistors facing each other on the opposite side to
Q ₆₀ , Q ₆₃ and Q ₆₁ , Q ₆₂ are turned on and off alternately as a set, and the output transformer 64 outputs positive and negative rectangular pulses having the same magnitude as the DC power supply voltage.

Transistors Q ₇₁ to Q ₇₄ , input transformers 70, 7
2 and an output transformer 74 are similarly constructed.

For these two sets of full bridges, transistors Q ₆₀ and Q ₇₀ , Q ₆₁ located on the same opposite side
The respective bases of Q ₇₁ , Q ₆₂ and Q ₇₂ , and Q ₆₃ and Q ₇₃ are connected to each other via a resistor R ₆₀ , and therefore, between the transistors on each opposite side used in the left and right full bridges. Even if there is a difference in storage time between the two, the transistor with the longer storage time is forcibly switched off in conjunction with the on/off of the transistor with the smaller storage time, so even if two or more full bridge circuits are combined, , no current imbalance occurs.

In each of the above embodiments, the bases of the transistors are interconnected through resistors, but the present invention is not limited to resistors, and any attenuation means such as diodes can be used.

As explained above, according to the present invention, a switching signal is applied to the bases of at least two transistors from independent secondary windings of an input transformer, and each of the transistors is connected to each other via an attenuation means. Therefore, even if transistors with different storage times are driven in parallel, the other transistors can be forced to turn off at the same time in response to the off state of the transistor with the minimum storage time, and the off state An effect can be obtained in that current imbalance caused by variations can be reliably prevented with a simple circuit configuration.

In addition, since the storage time can be ignored, it is easy to increase the capacity by using multiple small-capacity transistors, and in particular, it is easy to realize parallel operation of small output transformers, so switching The degree of coupling, which is a problem when the frequency is increased, is improved by using a small transformer, further improving the efficiency of the entire device.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional single inverter.
Figure 2 is a circuit diagram of a conventional single inverter that drives transistors in parallel, Figure 3 is a circuit diagram and input/output waveform diagram for explaining the influence of storage time of transistors on input/output, and Figure 4 is a diagram of input/output waveforms. A circuit diagram showing an embodiment of the present invention using two single inverters, FIG. 5 is a circuit diagram of another embodiment of the present invention using three or more single inverters, and FIG. 6 is a push-pull inverter. 7 is a circuit diagram of another embodiment of the present invention using two circuits of push-pull inverters, and FIG. 8 is a circuit diagram showing the main parts of another embodiment of the invention using three push-pull inverters. FIG. 9 is a circuit diagram of another embodiment of the present invention using two circuits of the half bridge,
FIG. 10 is a circuit diagram of another embodiment of the present invention using two full bridge circuits. 1... Diode bridge, 2, 16... Smoothing filter, T ₁ , 10, 22, 32, 50, 52,
58, 60, 62, 70, 72...input transformer,
T ₂ , 12, 14, 20a, 20b, 20c, 4
0, 42, 44, 54, 56, 58, 64, 74
...Output transformer.

Claims (1)

[Claims] 1 Input a switching signal of a predetermined frequency,
A transformer having at least two independent secondary windings on the secondary side, at least two transistors that are turned on and off by signals from each of the secondary windings, and an emitter load for each of the transistors. An inverter circuit comprising an output transformer connected thereto, the bases of the transistors being interconnected through attenuation means.