JPS6340824Y2 - - Google Patents

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Publication number
JPS6340824Y2
JPS6340824Y2 JP11282987U JP11282987U JPS6340824Y2 JP S6340824 Y2 JPS6340824 Y2 JP S6340824Y2 JP 11282987 U JP11282987 U JP 11282987U JP 11282987 U JP11282987 U JP 11282987U JP S6340824 Y2 JPS6340824 Y2 JP S6340824Y2
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JP
Japan
Prior art keywords
strip
width
high dielectric
conductor
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11282987U
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Japanese (ja)
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JPS6345916U (en
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Priority to JP11282987U priority Critical patent/JPS6340824Y2/ja
Publication of JPS6345916U publication Critical patent/JPS6345916U/ja
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Expired legal-status Critical Current

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Description

【考案の詳細な説明】 本考案は、絶縁材と帯状導体とを交互に積層成
形した回路基板用積層母線内に高誘電体チツプか
らなるコンデンサを直接埋設するようにし殊に作
業性の良好なコンデンサ内蔵型積層母線に関す
る。
[Detailed description of the invention] The present invention has particularly good workability by directly embedding a capacitor made of a high dielectric chip in a laminated bus bar for a circuit board, which is made by laminating insulating materials and strip-shaped conductors alternately. Concerning a laminated busbar with a built-in capacitor.

I.C等の大規模集積化並びに回路基板に対する
これら電子部品の高密度実装化に伴ない、これに
より構成される電子回路への電源給配電路及び信
号電路は、高周波ノイズ等からの悪影響を受ける
ことの無いように低いインダクタンスと高い分布
容量を持つ低特性インピーダンスを備えるような
ものが強く要望されるようになつて来た。積層母
線は、その導体間に誘電率の良好なフイルム状の
絶縁材を介在せしめる構造を持つ点で斯かる電源
給配電路若しくは信号電路に適用して最適と云え
るものではあるが、介装すべき絶縁材として通常
使用される誘電材料では得られる分布容量に限度
がある。そこで、この間の問題を解決する一便法
として、上記介在絶縁材に特殊な高誘電材料を使
用するような試みもなさえているが、これは主に
コスト的な面で実用に供し難いものがある。
With the large-scale integration of ICs and other electronic components and the high-density mounting of these electronic components on circuit boards, the power supply and distribution paths and signal lines for the electronic circuits constructed by these devices are subject to adverse effects from high-frequency noise, etc. There has been a strong demand for devices with low characteristic impedance, such as low inductance and high distributed capacitance. Laminated busbars have a structure in which a film-like insulating material with a good dielectric constant is interposed between the conductors, making them ideal for use in such power supply distribution lines or signal lines. There is a limit to the distributed capacitance that can be obtained with dielectric materials commonly used as insulating materials. Therefore, as an expedient method to solve this problem, attempts have been made to use a special high dielectric material for the intervening insulating material, but this is difficult to put into practical use mainly due to cost considerations. There is.

本考案は、電子回路の電源システムに用いられ
るこの種の積層母線内に多数の高誘電体チツプか
らなるコンデンサを直接的に組入れることによ
り、極めて良好な電源システムを設計可能な回路
基板用コンデンサ内蔵型積層母線、殊には製品の
低コスト化を達成可能な高い作業性をもつ新規な
回路基板用コンデンサ内蔵型積層母線を提供する
ものである。
This invention has a built-in capacitor for circuit boards that enables the design of an extremely good power supply system by directly incorporating capacitors made of a large number of high dielectric chips into this type of laminated bus bar used in power supply systems for electronic circuits. The object of the present invention is to provide a new type laminated bus bar with a built-in capacitor for a circuit board, which has high workability and can reduce the cost of the product.

本考案のコンデンサ内蔵型積層母線は、絶縁性
接着材を介して帯状導体間に介装すべき高誘電体
チツプの形状を層間絶縁材および帯導体の幅と同
等かまたはそれより大きな幅となるように形成す
る。該チツプ幅が帯状導体および層間絶縁材と同
幅である場合には、該導体および絶縁材の長手方
向の側縁に切欠部分を適宜形成するかまたは高誘
電体チツプが位置する領域に適数個の孔を設け、
斯かる切欠部分または孔に半田若しくは半田クリ
ームの如き導電性部材を付着させることにより該
チツプの両面とそれに隣接する帯状導体との接合
処理を簡便に行なえるようになる。また、高誘電
体チツプの幅が層間絶縁材および帯状導体の幅よ
り大きい場合には、該チツプの突出部分で上記の
如き接合処理を容易に行なえるもので、いずれに
しても上記チツプとこれを挟むように実質的に配
置される帯状導体とで形成される平板状のコンデ
ンサに対する組立作業性が著しく高められるもの
である。ここで、高誘電体チツプとしては例えば
薄いセラミツク板を適用することが出来るが、こ
のような部材は一般的にもろく割れ易い資質であ
る為、組立て時等の作業に際しては慎重な取扱い
を要するが、本考案の上記の如きチツプ形態を採
用することにより、その組立て並びに帯状導体間
との電気的接続処理等の作業性は良好であつて、
特性の優れたコンデンサ内蔵型積層母線を得るこ
とができる。
The laminated busbar with a built-in capacitor of the present invention has a shape of a high dielectric chip to be interposed between strip conductors via an insulating adhesive, so that the width is equal to or larger than the width of the interlayer insulation material and the strip conductor. Form it like this. If the width of the chip is the same as that of the strip-shaped conductor and the interlayer insulating material, an appropriate number of notches are formed on the longitudinal side edges of the conductor and the insulating material, or an appropriate number of notches are formed in the area where the high dielectric chip is located. Provides several holes,
By adhering a conductive material such as solder or solder cream to the notch or hole, it becomes possible to easily bond both sides of the chip to the strip-shaped conductor adjacent thereto. Furthermore, if the width of the high dielectric chip is larger than the width of the interlayer insulating material and the strip-shaped conductor, the above-mentioned bonding process can be easily performed on the protruding portion of the chip, and in any case, the above-mentioned chip and this The assembling work efficiency for a flat capacitor formed by strip-shaped conductors substantially arranged to sandwich the capacitor is greatly improved. Here, for example, a thin ceramic plate can be used as the high dielectric chip, but such materials are generally brittle and break easily, so they must be handled carefully during assembly and other operations. By adopting the above-mentioned chip form of the present invention, workability such as assembly and electrical connection processing between strip-shaped conductors is good.
A multilayer bus bar with a built-in capacitor with excellent characteristics can be obtained.

上記特徴に加え、本考案のコンデンサ内蔵型積
層母線を製造する場合には、前記高誘電体チツプ
をスペーサを介在させるかまたはさせないで多数
個のそれを予めリリースペーパー付きのテープ状
層間絶縁用接着材で挟み込んで実質的に高い誘電
率を備えた層間部材として簡便に形成可能であ
る。次いで、リリースペーパーを剥ぎ取つて帯状
導体をそれぞれ上記チツプの両面側に接着した段
階で斯かる積層体の外装を樹脂コーテイング処理
に付し高能率で製品の生産性をを向上させ得る。
In addition to the above features, when manufacturing the laminated bus bar with a built-in capacitor of the present invention, a large number of the high dielectric chips are bonded in the form of a tape with a release paper for interlayer insulation in advance, with or without a spacer. It can be easily formed as an interlayer member having a substantially high dielectric constant by sandwiching the material between the layers. Next, at the stage where the release paper is peeled off and the band-shaped conductors are adhered to both sides of the chip, the exterior of the laminate is subjected to a resin coating treatment, thereby improving the productivity of the product with high efficiency.

以下、図面に示す実施例に従つて本考案を更に
詳細に説明する。
Hereinafter, the present invention will be explained in more detail according to embodiments shown in the drawings.

第1図〜第4図は、本考案の一方のコンデンサ
内蔵型積層母線の実施例を図解したもので、高誘
電体チツプの幅を帯状導体の幅より大きくしたも
のを適用する点に大きな特徴がある。すなわち、
第1図および第2図において、1および2は銅板
からなる帯状の導体で、それらの各長手方向の一
方側には回路基板に実装する為の多数の端子1
A,2Aが適宜のピツチ及び必要なオフセツトを
備えるべく形成されている。これら両導体1およ
び2の間には高誘電体チツプとしてのセラミツク
板3と絶縁スペーサ4とを交互に多少の間隙を設
けるかまたは設けずに絶縁性接着材5を用いて介
装結着させるものである。この場合、少なくとも
セラミツク板3は導体1,2の幅より大きな幅を
備えるように形成し、帯状導体1,2の長手方向
上端縁に突き出たそれぞれのセラミツク板3の両
面部分に半田または半田クリーム6を付着して各
帯状導体1,2の上端縁とセラミツク板3の上端
部における各面とを個別に結合するようにする。
両帯状導体1,2はこのようにその間にスペーサ
4とセラミツク板6とを介在させるから、各端子
1A,2Aは回路基板に対する実装時に支障を与
えないように第2図の如くそれらの基部で一線に
並ぶように曲げるのが好ましい。7は斯かる積層
体の外装に形成した絶縁性コーテイング層を示
す。コーテイング層7の形成は、端子1A,2A
を保持しながらポリエステル樹脂、ブタジエル樹
脂、アクリル樹脂或いはエポキシ樹脂等の資質か
らなる絶縁性粉体樹脂に臨ませ、端子1A,2A
部分を除いた積層体の外周部位にこの粉体樹脂を
一様に付着させた後、加熱して該粉体樹脂の溶融
固着化を行なつて絶縁性コーテイング層7を高能
率で形成可能である。
Figures 1 to 4 illustrate an embodiment of one of the laminated busbars with a built-in capacitor according to the present invention, and the major feature is that the width of the high dielectric chip is larger than the width of the strip conductor. There is. That is,
In Figures 1 and 2, 1 and 2 are strip-shaped conductors made of copper plates, and on one longitudinal side of each of them, there are many terminals 1 for mounting on a circuit board.
A, 2A are formed with appropriate pitch and necessary offset. Between these two conductors 1 and 2, ceramic plates 3 as high dielectric chips and insulating spacers 4 are interposed and bonded using an insulating adhesive 5, with or without a gap provided alternately. It is something. In this case, at least the ceramic plate 3 is formed to have a width larger than the width of the conductors 1 and 2, and solder or solder cream is applied to both sides of each ceramic plate 3 protruding from the upper edges of the strip conductors 1 and 2 in the longitudinal direction. 6 is attached so that the upper edge of each strip-shaped conductor 1, 2 and each surface of the upper end of the ceramic plate 3 are individually bonded.
Since both the strip-shaped conductors 1 and 2 have the spacer 4 and the ceramic plate 6 interposed therebetween, the terminals 1A and 2A are connected at their bases as shown in FIG. It is preferable to bend them so that they line up in a straight line. 7 shows an insulating coating layer formed on the exterior of such a laminate. The coating layer 7 is formed on the terminals 1A and 2A.
Terminals 1A and 2A are exposed to an insulating powder resin made of polyester resin, butadiel resin, acrylic resin, or epoxy resin while holding the terminals 1A and 2A.
The insulating coating layer 7 can be formed with high efficiency by uniformly adhering this powder resin to the outer circumference of the laminate except for the parts, and then heating it to melt and solidify the powder resin. be.

セラミツク板3はもろく割れ易い性質である
為、本考案では、第3図の如く、リリースペーパ
ー8を有する二枚のテープ状絶縁性接着材5でセ
ラミツク板3および絶縁性スペーサ4を両面から
単に挟み込むように構成した。このような手法は
第4図に概念的に示した工程図から明らかなとお
り、各工程の作業性を著しく簡便化でき、作業能
率の向上を図れる。絶縁性スペーサ4はこの実施
例に従えばセラミツク板3と交互に配列するよう
にしているが、該スペーサ4の大きさを変更する
か若しくはこのスペーサ4を使用せずセラミツク
板3のみを介装することなどによつて、所望の分
布容量を形成可能である。
Since the ceramic plate 3 is brittle and easily cracked, in the present invention, the ceramic plate 3 and the insulating spacer 4 are simply bonded from both sides using two tape-shaped insulating adhesives 5 having a release paper 8, as shown in FIG. It was configured to be sandwiched. As is clear from the process diagram conceptually shown in FIG. 4, such a method can significantly simplify the workability of each process and improve work efficiency. According to this embodiment, the insulating spacers 4 are arranged alternately with the ceramic plates 3, but the size of the spacers 4 may be changed or the spacers 4 may not be used and only the ceramic plates 3 may be interposed. A desired distributed capacitance can be formed by, for example,

すなわち、第4図1に示すように、帯状導体
1,2の幅および長さに合致したリリースペーパ
ー8を有するテーパ状の絶縁性接着材5を予め多
数用意し、同図2の如く、それらの一枚づつにセ
ラミツク板3と絶縁性スペーサ4とを交互に貼り
付ける。この場合、セラミツク板3とスペーサ4
との相互間に僅かの間隙が出来るように配列し、
後工程で行なうキユアリング時に生じる接着材5
の熱収縮を吸収し得るように対処するのが好まし
い。次いで、それらの上面に同図3のように他の
リリースペーパー8付きの接着材5を貼り合わせ
ると第3図に示すような状態を得ることができ
る。リリースペーパー8はこの間の工程で各接着
材5の他面にゴミ、油などの異物の付着する虞を
防止すると共に上記貼り合わせ作業を容易化する
ものである。上記のセラミツク板3、スペーサ4
および接着材5の貼り合わせ作業は、各部材を第
1図〜第3図の配置形態を取るように適当な治具
等の併用による手作業或いは自動的な貼り合わせ
処理を行なうことが可能である。このような貼り
合わせ処理を了えた段階で一方面のリリースペー
パー8を剥ぎ取つて露出した接着材5の面に同図
4のとおり一方の帯状導体1を接合し、同図5の
如く、同様に他方面のリリースペーパー8の剥ぎ
取りと他の帯状導体2の接合処理を行ない、爾
後、この積層体を強固に接合させる為に加熱プレ
スに挿入して加圧加熱しながらキユアリング処理
に付す。このような積層体に対する一体化工程の
後に、第1図および第2図に示した如く、それぞ
れ突出したセラミツク板3の上端部分において隣
接する各導体1,2の上端縁との電気的接続を行
なう為に半田または半田クリーム6の付着処理を
施すこととなる。最後に、同図6のように積層体
の外装として粉体絶縁樹脂による既述の如きコー
テイング層7を形成して製品を高能率で製造する
ことが出来る。
That is, as shown in FIG. 4, a large number of tapered insulating adhesives 5 having release papers 8 matching the width and length of the strip conductors 1 and 2 are prepared in advance, and as shown in FIG. Ceramic plates 3 and insulating spacers 4 are alternately pasted on each sheet. In this case, ceramic plate 3 and spacer 4
arranged so that there is a slight gap between them,
Adhesive material produced during curing performed in the post-process 5
It is preferable to take measures to absorb the heat shrinkage. Next, as shown in FIG. 3, another adhesive 5 with a release paper 8 is attached to the upper surfaces of these, so that the state shown in FIG. 3 can be obtained. The release paper 8 prevents foreign matter such as dust and oil from adhering to the other surface of each adhesive 5 during this process, and also facilitates the above-mentioned bonding operation. Above ceramic plate 3, spacer 4
The work of pasting together the adhesive material 5 can be done manually using an appropriate jig or the like, or automatically so that each member takes the arrangement form shown in Figures 1 to 3. be. After completing such a bonding process, the release paper 8 on one side is peeled off and one strip-shaped conductor 1 is bonded to the exposed surface of the adhesive 5 as shown in FIG. Then, the release paper 8 on the other side is peeled off and the other strip-shaped conductor 2 is bonded, and then, in order to firmly bond the laminated body, it is inserted into a heating press and subjected to a curing treatment while being pressurized and heated. After such an integration process for the laminate, as shown in FIGS. 1 and 2, electrical connections are made between the upper end edges of the adjacent conductors 1 and 2 at the upper end portions of the protruding ceramic plates 3, respectively. In order to do this, solder or solder cream 6 must be applied. Finally, as shown in FIG. 6, the above-mentioned coating layer 7 made of powder insulating resin is formed as the exterior of the laminate, thereby making it possible to manufacture the product with high efficiency.

上記実施例において、高誘電体チツプとしての
セラミツク板3の幅の帯状導体1,2の幅より大
きく形成してそれらの上端部分の領域でコンデン
サを構成するに必要な電気的接続処理を行なうよ
うにしたが、このような手法に代えて第5図〜第
8図の如き接続方法も極めて有利である。すなわ
ち、その第一の手法としては、第5図および第6
図に示すように、セラミツク板3Aおよびスペー
サ4Aの幅を帯状導体1,2の幅と同幅に形成
し、然もセラミツク板3Aが配列される領域の帯
状導体1,2並びに接着材5Aの例えば長手方向
の中央部分に図示のような共通の穴9を適宜数設
け、前記実施例のような各部材の貼り合わせ処理
後に穴9に半田または半田クリームの如き導電部
材10を詰め込んで各導体1,2とセラミツク板
3Aとの各対面域で導通を取ることである。ま
た、第二の手法としては、第7図および第8図の
ように、同じくセラミツク板3A、スペーサ4A
の幅を帯状導体3Aおよび接着材4Aのそれと同
幅に形成すると共に、セラミツク板3Aが配列さ
れる位置の導体1,2と接着材5Aとの上端部に
共通の切欠部11を形成してセラミツク板3Aの
上端部分を一部露出させ、次いで第1図、第2図
に示した既述の手法で半田または半田クリーム1
2を付着させて両者間の導通を図ることである。
これらの手法はいずれも実質的には前記実施例と
同一な工程で高能率に製造できるが、殊に第5図
〜第8図の構造によれば、セラミツク板3Aおよ
びスペーサ4Aの素材節約化と各部材の貼り合わ
せ処理が容易に行なえるという利点を有用する。
これらの実施例でも既述の如く、スペーサ4Aを
排してセラミツク板3Aのみにするか、或いはス
ペーサ4Aとセラミツク板3Aの長さ寸法を任意
変更するか又はそれらの厚さを変更するかそれら
いずれか一方若しくは全てを考慮に入れて仕様に
最適な分布容量を製品に具備させるように構成で
きる。
In the above embodiment, the width of the ceramic plate 3 as a high dielectric chip is formed to be larger than the width of the band-shaped conductors 1 and 2, and the electrical connection process necessary to form a capacitor is performed in the upper end region of the conductors 1 and 2. However, instead of this method, the connection methods shown in FIGS. 5 to 8 are also extremely advantageous. That is, the first method is as shown in Figures 5 and 6.
As shown in the figure, the width of the ceramic plate 3A and the spacer 4A is formed to be the same as the width of the band-shaped conductors 1, 2, and the width of the band-shaped conductors 1, 2 and the adhesive material 5A in the area where the ceramic plate 3A is arranged. For example, an appropriate number of common holes 9 as shown in the figure are provided in the central portion in the longitudinal direction, and after the respective members are pasted together as in the above embodiment, the holes 9 are filled with a conductive material 10 such as solder or solder cream, and each conductor is 1 and 2 and the ceramic plate 3A in each facing area. In addition, as a second method, as shown in FIGS. 7 and 8, a ceramic plate 3A and a spacer 4A are also used.
is formed to have the same width as that of the band-shaped conductor 3A and the adhesive material 4A, and a common notch 11 is formed at the upper end of the conductors 1, 2 and the adhesive material 5A at the position where the ceramic plate 3A is arranged. A part of the upper end portion of the ceramic plate 3A is exposed, and then solder or solder cream 1 is applied using the method shown in FIGS. 1 and 2.
2 is attached to establish electrical continuity between the two.
All of these methods can be manufactured with high efficiency through substantially the same steps as in the above embodiments, but in particular, the structures shown in FIGS. This method has the advantage that each member can be easily bonded together.
In these embodiments, as described above, the spacer 4A is eliminated and only the ceramic plate 3A is used, or the length dimension of the spacer 4A and the ceramic plate 3A is arbitrarily changed, or the thickness thereof is changed. It is possible to configure a product to have a distributed capacitance that is optimal for the specifications by taking either or all of them into consideration.

本考案は、以上の説明から分るとおり、セラミ
ツク板からなる高誘電体チツプを必要に応じて絶
縁性スペーサと共に予めリリースペーパー付きの
絶縁性接着材で挟み込んで実質的に一体的な高誘
電率を有する層間絶縁体を簡単に構成できるの
で、複数の高誘電体チツプの組立時に於ける作業
性を好適に高め得る。そして、個々の高誘電体チ
ツプを各帯状導体との接合処理は、帯状導体に対
する高誘電体チツプの付き出し部分か該導体に設
けた切欠又は透孔の部分に半田又は半田クリーム
の如き導電部材を付着させることにより簡便高能
率に行える。また、斯かる積層母線の外装は粉体
樹脂による絶縁コーテイング層で得られる為、外
装形成作業を高能率に達成し、製品の低コスト化
を一層高めることが出来る等、電子部品の高密度
実装に伴なう回路基板への良質な電源供給もしく
は信号授受の電路手段として非常に優れたコンデ
ンサ内蔵型積層母線を提供できる。
As can be seen from the above description, the present invention has a high dielectric constant chip made of a ceramic plate that is sandwiched between insulating adhesive materials with release paper in advance, together with insulating spacers as necessary, to create a substantially integrated high dielectric constant chip. Since the interlayer insulator having the above structure can be easily constructed, the workability in assembling a plurality of high dielectric chips can be suitably improved. Then, in the process of joining each high dielectric chip with each strip conductor, a conductive material such as solder or solder cream is applied to the protruding portion of the high dielectric chip to the strip conductor or the notch or through hole provided in the conductor. This can be done easily and efficiently by attaching . In addition, since the exterior of such a laminated busbar is obtained by an insulating coating layer made of powder resin, the exterior forming work can be achieved with high efficiency, and the cost of the product can be further reduced, allowing for high-density mounting of electronic components. It is possible to provide a laminated bus bar with a built-in capacitor that is very excellent as a high-quality power supply to a circuit board associated with the above-mentioned circuit board or as an electric circuit means for transmitting and receiving signals.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例によるコンデンサ内
蔵型積層母線の概念的な部分切欠平面図、第2図
は第1図のX−X線拡大断面図、第3図は第1図
および第2図に示したセラミツク板と絶縁性スペ
ーサとをリリースペーパーを有する接着材で両面
から挟持する態様を示す部分切欠拡大斜視図、第
4図1〜6は第1図のコンデンサ内蔵型積層母線
に対する製造工程図、第5図は本考案の他の実施
例によるコンデンサ内蔵型積層母線の帯状導体と
セラミツク板との導通構造を示す部分平面図、第
6図は第5図のY−Y線拡大断面図、第7図は同
じく他の導通構造を示す部分平面図、そして第8
図は第7図のZ−Z線拡大断面図である。 1,2:帯状導体、3:セラミツク板、4:絶
縁性スペーサ、5:絶縁性接着材、6:半田また
は半田クリーム、7:絶縁性コーテイング層、
8:リリースペーパー、9:穴、10:導電部
材、11:切欠部、12:半田または半田クリー
ム。
FIG. 1 is a conceptual partial cutaway plan view of a laminated bus bar with a built-in capacitor according to an embodiment of the present invention, FIG. 2 is an enlarged sectional view taken along the line X-X of FIG. 1, and FIG. A partially cutaway enlarged perspective view showing how the ceramic plate and the insulating spacer shown in Figure 2 are sandwiched from both sides by an adhesive having a release paper, and Figures 4 1 to 6 are views of the capacitor built-in laminated busbar shown in Figure 1. 5 is a partial plan view showing the conduction structure between the strip conductor and the ceramic plate of a laminated bus bar with a built-in capacitor according to another embodiment of the present invention; FIG. 6 is an enlarged view of the Y-Y line in FIG. 5; A sectional view, FIG. 7 is a partial plan view showing another conductive structure, and FIG.
The figure is an enlarged sectional view taken along the Z-Z line in FIG. 7. 1, 2: band-shaped conductor, 3: ceramic plate, 4: insulating spacer, 5: insulating adhesive, 6: solder or solder cream, 7: insulating coating layer,
8: Release paper, 9: Hole, 10: Conductive member, 11: Notch, 12: Solder or solder cream.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] それぞれ端子を突出形成した複数の帯状導体を
それぞれ層間絶縁材を介して積層し、かつ、外装
を絶縁被覆するようにした回路基板用積層母線に
おいて、上記層間絶縁材の間に介装されかつ上記
帯状導体の幅と同幅又はそれより大きな幅を有す
る多数の平板状高誘電体チツプを設け、該高誘電
体チツプの幅が上記帯状導体の幅より大きな場合
にはこれら各高誘電体チツプの上記帯状導体に対
する付き出し部分で、また、上記高誘電体チツプ
の幅が上記帯状導体の幅と同幅の場合には該帯状
導体に設けた切欠或いは透孔の部分においてそれ
ぞれ導電性部材を設けて各高誘電体チツプと帯状
導体とを接合するように構成したことを特徴とす
るコンデンサ内蔵型積層母線。
In a laminated bus bar for a circuit board, in which a plurality of band-shaped conductors each having a protruding terminal are laminated via an interlayer insulating material, and the exterior is insulated, the conductor is interposed between the interlayer insulating materials, and the above-described A large number of flat high dielectric chips having a width equal to or larger than the width of the strip conductor is provided, and when the width of the high dielectric chip is larger than the width of the strip conductor, each of these high dielectric chips is Conductive members are provided at the protruding portions of the strip-shaped conductor, or, if the width of the high dielectric chip is the same as the width of the strip-shaped conductor, at the notches or through holes provided in the strip-shaped conductor. 1. A multilayer bus bar with a built-in capacitor, characterized in that each high dielectric chip and a strip-shaped conductor are joined together.
JP11282987U 1987-07-23 1987-07-23 Expired JPS6340824Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11282987U JPS6340824Y2 (en) 1987-07-23 1987-07-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11282987U JPS6340824Y2 (en) 1987-07-23 1987-07-23

Publications (2)

Publication Number Publication Date
JPS6345916U JPS6345916U (en) 1988-03-28
JPS6340824Y2 true JPS6340824Y2 (en) 1988-10-25

Family

ID=30994070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11282987U Expired JPS6340824Y2 (en) 1987-07-23 1987-07-23

Country Status (1)

Country Link
JP (1) JPS6340824Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6682894B2 (en) * 2016-02-10 2020-04-15 富士電機株式会社 Insulation busbar, method of manufacturing insulation busbar, and electronic device

Also Published As

Publication number Publication date
JPS6345916U (en) 1988-03-28

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