JPS6340358A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6340358A JPS6340358A JP61184820A JP18482086A JPS6340358A JP S6340358 A JPS6340358 A JP S6340358A JP 61184820 A JP61184820 A JP 61184820A JP 18482086 A JP18482086 A JP 18482086A JP S6340358 A JPS6340358 A JP S6340358A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- potential
- threshold value
- voltage
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000010355 oscillation Effects 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にバイポーラ型トランジ
スタの回路によりＭＯＳ型トランジスタのしきい値電圧
の制御を行う半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which the threshold voltage of a MOS transistor is controlled by a bipolar transistor circuit.
従来、この種の半導体装置では、ＭＯＳ型トランジスタ
のしきい値・が製造条件に左右されるので、回路設計上
そのしきい値の余裕度を大きく取る必要があった。Conventionally, in this type of semiconductor device, since the threshold value of a MOS transistor depends on manufacturing conditions, it has been necessary to provide a large margin for the threshold value in circuit design.
上述した従来の半導体装置は、ＭＯＳ型トランジスタの
しきい値電圧がリソグラフィ精度、拡散精度等により左
右されるため、このしきい値を回路設計上大きめの設計
余裕を取り、かつ出来上った製品等についても特性上に
余裕をもなせる必要があった。In the conventional semiconductor device described above, the threshold voltage of the MOS transistor is affected by lithography accuracy, diffusion accuracy, etc. It was also necessary to have some leeway in terms of characteristics.
本発明の目的は、このような問題を解決し、しきい値電
圧を制御できるようにしてＭＯＳ）−ランジスタの設計
、製造上の余裕が少くても動作できる半導体装置を提供
することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve such problems and provide a semiconductor device that can control the threshold voltage and operate even with a small margin in designing and manufacturing a MOS transistor.
本発明の楕或は、ＭＯＳ型トランジスタとノくイボーラ
型トランジスタとを含み、基板電位の内部発生回路を有
する半導体装置において、前記ＭＯＳ型トランジスタの
基準しきい値電圧と入力された所定基準電圧とを比較す
る比較回路と、この比較回路の出力に従って交流出力電
圧が可変される発振回路と、この発振回路の出力を整流
して直流電位とする整流回路と、この整流回路の出力に
従って前記基板電位を制御することにより前記ＭＯＳト
ランジスタのしきい値を制御する制御手段とを備えるこ
とを特徴とする。An aspect of the present invention is a semiconductor device including a MOS type transistor and a Noku Ibora type transistor and having an internal substrate potential generation circuit, in which a reference threshold voltage of the MOS type transistor and an input predetermined reference voltage are an oscillation circuit whose AC output voltage is varied according to the output of this comparison circuit; a rectifier circuit which rectifies the output of this oscillation circuit to obtain a DC potential; and control means for controlling the threshold voltage of the MOS transistor by controlling the threshold voltage of the MOS transistor.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示すブロック図、第２図は
第１図の回路図である。本実施例は、リング発振器から
なり入力電流により交流出力レベルが可変される発振回
路１と整流回路２とから電位レベルの異なる基板電位を
発生する。又、基準となるＭＯ５型トランジスタＱ１の
しきい値電位発生回路３は、基板電位によってそのしき
い値が制御されている。電圧比較回路３にはこのＭＯ３
型トランジスタＱ１のしきい値電位と、基準電位入力端
子６から入力される基準電位とが与えられるので、その
比較結果を発振回路１に入力し、この発振回路１の出力
発振電圧を制御している。この出力発振電圧は、入力コ
ンデンサをもつ整流回路２で整流されてレベル変換され
た直流電圧となり、基板電圧としてＭＯＳ）ランジスタ
Ｑ□に供給されている。FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram of FIG. 1. In this embodiment, substrate potentials having different potential levels are generated from an oscillation circuit 1 and a rectification circuit 2, which are composed of a ring oscillator and whose alternating current output level is varied depending on the input current. Further, the threshold potential generation circuit 3 of the MO5 type transistor Q1 serving as a reference has its threshold value controlled by the substrate potential. This MO3 is used in the voltage comparison circuit 3.
Since the threshold potential of the type transistor Q1 and the reference potential inputted from the reference potential input terminal 6 are given, the comparison result is inputted to the oscillation circuit 1, and the output oscillation voltage of this oscillation circuit 1 is controlled. There is. This output oscillation voltage is rectified by a rectifier circuit 2 having an input capacitor to become a level-converted DC voltage, which is supplied to a MOS transistor Q□ as a substrate voltage.
以上説明した様に、しきい値電位と基準電位との比較結
果を基板を介して帰還される事により、基準となるＭＯ
Ｓ型トランジスタの基板電位を変化させ、設計上許容出
来る範囲内でＭＯＳ型トランジスタのしきい値を制御す
る事が出来る。As explained above, by feeding back the comparison result between the threshold potential and the reference potential through the substrate, the reference MO
By changing the substrate potential of the S-type transistor, it is possible to control the threshold value of the MOS-type transistor within a design-allowable range.
以上説明した様に、本発明は、基準電位とＭＯＳ型トラ
ンジスタのしきい値とを比較し、基板電位を制御して、
基準となるＭＯＳ型トランジスタに帰還させる事により
、ＭＯＳ型トランジスタのしきい値を所望の値にする事
が出来、回路設計上の余裕度を増す事が出来る。As explained above, the present invention compares the reference potential and the threshold value of the MOS transistor, controls the substrate potential, and
By feeding back to the reference MOS transistor, the threshold value of the MOS transistor can be set to a desired value, and the margin in circuit design can be increased.
第１図は本発明の一実施例を示すブロック図、第２図は
第１図の回路図である。
１・・・発振回路、２・・・整流回路、３・・・比較回
路、４・・・しきい値発生回路、５・・・基板電位発生
端子（基板）、６・・・基準電位入力端子、Ｑｌ・・・
トランジスタ、Ｒ１・・・抵抗。FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram of FIG. 1. DESCRIPTION OF SYMBOLS 1... Oscillator circuit, 2... Rectifier circuit, 3... Comparison circuit, 4... Threshold generation circuit, 5... Substrate potential generation terminal (substrate), 6... Reference potential input Terminal, Ql...
Transistor, R1...resistance.
Claims (1)
を含み、基板電位の内部発生回路を有する半導体装置に
おいて、前記ＭＯＳ型トランジスタの基準しきい値電圧
と入力された所定基準電圧とを比較する比較回路と、こ
の比較回路の出力に従って交流出力電圧が可変される発
振回路と、この発振回路の出力を整流して直流電位とす
る整流回路と、この整流回路の出力に従って前記基板電
位を制御することにより前記ＭＯＳトランジスタのしき
い値を制御する制御手段とを備えることを特徴とする半
導体装置。In a semiconductor device including a MOS transistor and a bipolar transistor and having an internal substrate potential generation circuit, a comparison circuit that compares a reference threshold voltage of the MOS transistor and an inputted predetermined reference voltage; an oscillator circuit whose AC output voltage is varied according to the output of the circuit; a rectifier circuit which rectifies the output of the oscillation circuit to obtain a DC potential; and a rectifier circuit which controls the substrate potential according to the output of the rectifier circuit. A semiconductor device comprising: control means for controlling a threshold value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61184820A JPS6340358A (en) | 1986-08-05 | 1986-08-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61184820A JPS6340358A (en) | 1986-08-05 | 1986-08-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6340358A true JPS6340358A (en) | 1988-02-20 |
Family
ID=16159860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61184820A Pending JPS6340358A (en) | 1986-08-05 | 1986-08-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6340358A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6094068A (en) * | 1997-06-19 | 2000-07-25 | Nec Corporation | CMOS logic circuit and method of driving the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57199335A (en) * | 1981-06-02 | 1982-12-07 | Toshiba Corp | Generating circuit for substrate bias |
-
1986
- 1986-08-05 JP JP61184820A patent/JPS6340358A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57199335A (en) * | 1981-06-02 | 1982-12-07 | Toshiba Corp | Generating circuit for substrate bias |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6094068A (en) * | 1997-06-19 | 2000-07-25 | Nec Corporation | CMOS logic circuit and method of driving the same |
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