JPS6340075U - - Google Patents
Info
- Publication number
- JPS6340075U JPS6340075U JP13346786U JP13346786U JPS6340075U JP S6340075 U JPS6340075 U JP S6340075U JP 13346786 U JP13346786 U JP 13346786U JP 13346786 U JP13346786 U JP 13346786U JP S6340075 U JPS6340075 U JP S6340075U
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- signal
- signal path
- outputs
- path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は、本考案のビデオ信号出力回路の一実
施例の回路図であり、第２図は、本考案のテレビ
信号出力回路の他の実施例の回路図であり、第３
図は、本考案のビデオ信号出力回路のさらに他の
実施例の回路図であり、第４図は、従来のビデオ
信号出力回路の一例の回路図である。
１：ビデオ信号出力回路、２：ビデオ信号源、
３：ビデオ出力端子、４：テレビ出力端子、５：
ＡＶテレビジヨン受像機、１０，２０，３０，４
０：第１の信号径路、１１：第２の信号径路、１
２：ＲＦモジユレータ、２２：トランジスタ。
FIG. 1 is a circuit diagram of one embodiment of the video signal output circuit of the present invention, FIG. 2 is a circuit diagram of another embodiment of the television signal output circuit of the present invention, and FIG.
This figure is a circuit diagram of still another embodiment of the video signal output circuit of the present invention, and FIG. 4 is a circuit diagram of an example of a conventional video signal output circuit. 1: video signal output circuit, 2: video signal source,
3: Video output terminal, 4: TV output terminal, 5:
AV television receiver, 10, 20, 30, 4
0: first signal path, 11: second signal path, 1
2: RF modulator, 22: transistor.
Claims (1)
に分岐し、一方の第１の信号径路は前記ビデオ信
号をそのまま出力し、他方の第２の信号径路はＲ
Ｆモジユレータを介して前記ビデオ信号をテレビ
信号に変換して出力するビデオ信号出力回路にお
いて、前記第１の信号径路にトランジスタ素子を
含むバツフア回路を介装して前記第１の信号径路
の出力端側から入来する信号の逆流を阻止するよ
うに構成したことを特徴とするビデオ信号出力回
路。 The video signal output from the video signal source is branched into two, one first signal path outputs the video signal as it is, and the other second signal path is R
In a video signal output circuit that converts the video signal into a television signal via an F modulator and outputs the same, a buffer circuit including a transistor element is interposed in the first signal path, and the output end of the first signal path is A video signal output circuit characterized in that it is configured to prevent reverse flow of signals coming from the side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13346786U JPS6340075U (en) | 1986-08-29 | 1986-08-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13346786U JPS6340075U (en) | 1986-08-29 | 1986-08-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6340075U true JPS6340075U (en) | 1988-03-15 |
Family
ID=31033813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13346786U Pending JPS6340075U (en) | 1986-08-29 | 1986-08-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6340075U (en) |
-
1986
- 1986-08-29 JP JP13346786U patent/JPS6340075U/ja active Pending
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